 Namaste. Welcome to the session design of asynchronous counter. At the end of this session students will be able to analyze and design asynchronous counters. These are the contents of this session. Now, let us know about the counters. Counter is a digital circuit which is used for counting elements, objects, operations in industries or any applications in terms of clock pulses. Both registers and counters belong to the class of sequential circuits. Now, let us take a pause and recall what do you mean by registers. It is a sequential logic circuit with a group of flip-flops used as buffer registers for temporary storage of data and registers are also used for shifting the data in various applications. Counter is the widest application of flip-flop designed mostly using JK and T-flip-flop because JK and T-flip-flop can be used in toggle mode. In counters, counting operation takes place in binary number system and counter output is decoded into decimal number system. Now, let us see types of counter. Counters are used in sequential devices or systems where operations are performed in a certain sequence. The basic types of counters are asynchronous counter and synchronous counter. In case of synchronous counter, output of first flip-flop drives the clock of second flip-flop and output of second flip-flop drives the clock of the third flip-flop and so on. In case of synchronous counter, there is no connection between output of first flip-flop and the clock input of the next flip-flop and so on. In asynchronous counter, all the flip-flops are not clocked simultaneously whereas in case of synchronous counter, all the flip-flops are clocked simultaneously. In case of asynchronous counter, designed implementation is very simple even for more than a number of states. But in case of synchronous counter, designed implementation becomes tedious and complex as number of states increases. Asynchronous counters are slower because the clock is given to the next flip-flop from the output of the first flip-flop whereas in case of synchronous counter, these are faster because of clock is given simultaneously to all the flip-flops. Asynchronous counters. It is also known as ripple counter since clock pulses applied are propagated from one flip-flop to next flip-flop. It is the simplest type of counter and also known as serial or series counter. A flip-flop has two states. Therefore, a group of n number of flip-flops will have two raise to n states. Sub types of counters as up counter which counts in ascending order then we have a down counter which counts in descending order and there is one more type of counter up down counter which has both facilities of up counting and down count. Now, let us see the design of 2-bit asynchronous up counter. Now, let us see two table first. So, as it is a 2-bit asynchronous up counter means here we are using 2 flip-flops and when 2 flip-flops are used there will be 2 raise to 2 number of states and these states let us consider as a 0 0 0 1 1 0 and 1 1. So, in the true table you can see inputs outputs and state changes. So, here in case of output we have q 2 and q 1 which is representing output of each flip-flop. So, the output of first flip-flop is represented as q 1 and output of second flip-flop is represented as q 2. In the column of outputs the output of first flip-flop that is q 1 is changing each time when clock is given, but q 2 is changing its output only when output of q 1 is high. So, here you can see output of q 2 is changed when output of q 1 is 1. So, here you can see there is a transition in output of the q 2 only when q 1 is 1. So, after this the output will be again 0 0. So, cycle repeats. In the last column that is state changes we have n c and t. So, n c represents no change. So, whenever there is clock applied and if there is no transition if transition remains same as 0 to 0 or 1 to 1 then there is a no change and when there is a change from 0 to 1 or 1 to 0 it is in a toggle mode represented by t. So, according to this table we have designed here as we know that in case of asynchronous counter the basic clock is given to the first flip-flop and the clock to the next flip-flop is given from the output of the first flip-flop ok. And as we are using here jk flip-flop. So, jk flip-flop is in toggle mode by connecting it to the high jk of both flip-flop is connected to high that is logic 1. So, here you can see there is a negative a triggered clock and output of first flip-flop that is q 1 why q 1 because the transition of q 2 happens only when output of q 1 is 1. So, we are giving here output that is normal output as a clock to the next flip-flop. So, here we have q 1 and q 2 output. So, let us consider output of q 1 and q 2 are 0 0. So, this is representing decimal 0. So, we are decoding this 0 0 binary into decimal 0 when next clock is given q 1 is going to toggle. So, it changes from 0 to 1 and output of q 1 that is 1 is given to the second flip-flop. So, there will be no change because here we require the negative a triggered clock, but as output of q 1 is 1. So, it is taken as a positive and hence there will be no change. So, according to this table you can see there is no change for the q 2 and there is a toggle for the q 1. So, as q 1 is changed from 0 to 1 and this 0 1 is decoded as decimal 1. So, here you can see how it is decoded it is from MSB to LSB q 2 to q 1. So, 0 0 then 0 1 when next clock pulse is given the first flip-flop is going to make the transition that is from 1 to 0 and when output of q 1 is 0 that is applied as a negative a triggered clock and hence q 2 will also change its output from 0 to 1. So, there is a transition. So, here you can see there is a toggle mode when next clock is given and this 1 0 represents decimal 2 and hence when next clock is given then we have the transition from 0 to 1 and 1 to 1 and this is represented as 3 and when next clock pulse is given again the recycle get repeated. So, in this timing diagram you can see at the first clock there is a transition from 0 to 1 for the first flip-flop then for the second clock there is transition for the second flip-flop and the first flip-flop also at every clock pulse for the negative a is q 1 is going to change its output, but q 2 will change when there is a transition of q 1 is 1. Similarly, we can design to beat a synchronous down counter. So, in case of down counter we have down counting as 0 0 1 1 1 0 0 1. So, from this truth table you can see there is a always transition in case of q 1 and the q 2 will make the transition when output of q 1 is 0. So, here you can see when output of q 1 is 0 then only the second flip-flop toggles. So, let us see the operation of 2 bit asynchronous down counter with this logic diagram. So, when initially the output is 0 0 it is decoded as 0 when next clock pulse is given what will happen here is the first flip-flop is going to make the transition that is 0 1. So, here q 1 is nothing but 1 at the same time q 1 bar will be 0 that 0 is applied to the next flip-flop. Hence, next flip-flop will also do the transition from 0 to 1. So, hence from 0 0 the next output will be 1 1 that is decoded as 3. When the next clock pulse is given there will be always transition from the first flip-flop. So, q 1 will be 0 but q 1 bar will be 1 and hence there will be no change at the output of q 2. So, q 2 remains same that is 1 to 1 and this 1 0 represents 2. With the next clock pulse again there will be transition of q 1 from 0 to 1 and when it is 1 q 1 bar will be 0 that is applied as a negative a triggered clock and hence q 2 also changes from 1 to 0. Hence, this works as a down counter. So, similarly we have a timing diagram here. So, whenever there is a negative a triggered clock there will be always transition for the q 1 that is output of first flip-flop and q 2 will change when q 1 having output 0. So, there will be transition in case of second flip-flop only when q 1 is having 0 output. Now, let us see design of 2 bit asynchronous up-down counter. So, 2 bit asynchronous up-down counter is nothing but combination of up counting and down counting. So, we know that for up counting the normal output is connected as a clock to the next flip-flop and for down counting the complemented output of first flip-flop is connected as a clock to the next flip-flop. So, to have up and down both counting we have connected output of q 1 and q 1 bar with the help of OR gate and also this AND gate having one control input known as a M. So, M is a mode control. So, when mode control M is 1 then it works as a up counter because 1 is applied to the upper AND gate. So, it is always activated and when M is 1 then lower AND gate will be having 0. So, lower AND gate will be always disabled. So, it will do up counting and when M is 0 0 is applied to the upper AND gate. Hence it is disabled and 1 is applied to the lower AND gate. So, it will work as a down counter. So, in this way you can design asynchronous up counter down counter and up down counter also. These are the references. Thank you.