 Hello and welcome to the series of video lectures on the subject digital techniques for secondary IT students. I am Dr. Srisal Gajbar and in this video lecture we are going to implement half-subtractor and full-subtractor circuits by using Verilog HDL language. So at the end of this session you will be able to implement half-subtractor circuit by using Verilog HDL. You will also be able to implement full-subtractor circuit by using Verilog. So software that we are going to use for simulation is model sim student edition. You can download this software by using this link which is provided here. It's a free software so any one of you can download and run the Verilog programs. The first circuit that we are going to implement is half-subtractor circuit. So half-subtractor circuit is a combinational circuit that performs subtraction of 2 bits. So this circuit needs 2 binary inputs and 2 binary outputs. So this is a block diagram for half-subtractor circuit. There are 2 inputs A and B and the outputs are D that is difference bit and bar output bit. So this is a truth table. So from this truth table one can find out the logical expression for this output that is D as well as for BO. Here you can see the implementation diagram for the half-subtractor circuit. So the D in this case is equal to AX or B whereas BO can be given as A bar into B. So this is implemented here. So basically we are going to use these equations for implementing our Verilog program for this circuit. So this is the Verilog module definition for half-subtractor circuit. Here our module definition will start with the module keyword. The name for this module is given as half-underscore-subtractor. Inside the bracket the list of inputs and outputs are given. So the inputs here are A and B whereas the outputs are D and BO. In these 2 lines the inputs and outputs are defined. In the next 2 lines we start with the assign keyword, we are going to assign the difference D equal to AX or B. So what is going to happen here? The bitwise XOR operation between A and B is going to happen and this value will be assigned to the D. Similarly the bar output will be calculated as A bar and operation with B and this will be assigned to BO. And we are going to end our module definition with the end module keyword. So this shows the test bench for half-subtractor circuit. Here the inputs are shown by using the reg data type whereas the outputs are defined by using the wire data type. Reg because we want to store some values in the inputs. The next line shows the instantiation of the half-subtractor module. So half-underscore-subtractor. HS1 is the name of the object and inside bracket we have passed the arguments that are required here. Then similar to our previous circuits initial begin and between initial begin and end we are going to provide all possible input combinations to test the correctness of our module. And finally we are going to write the end module. So on your screen these are the modules for half-subtractor circuit as well as the test bench for half-subtractor circuit. So let us compile. Let us see our compile is successful or not. And as you can see here our compile is successful and there are no errors in this case library and inside library we will go to the test half-subtractor simulate then go to the add to wave all items in region. You can see here there are two inputs to our half-subtractor circuits A and B and there are two outputs namely D and BO. So you can see here D and BO. So I have simulated the output and here you can see the simulation results for A and B both 0 0 the difference is 0 and the borrower output is also 0. For the input combination 0 1 that is A is 0 and B is 1 both the difference bit as well as BO that is borrower output both are 1 right. So this also verifies our truth table of half-subtractor. For input combination 1 0 you can see the difference bit is 1 whereas the borrower output is 0. And finally for the input combination 1 1 you can see the difference bit D output D is 0 and the B output is also 0. So this verifies the correctness of our module definition for half-subtractor circuit. Now pause the video for 1 minute and write down the answer of the given question. The correct answer in this case is work library. So all the files that are necessary for simulating are available in this work library. So the next circuit that we are going to implement is full-subtractor circuit. This is the block diagram for full-subtractor circuits. It's a combinational circuit which will have 3 inputs and 2 outputs. It is going to perform the subtraction of 3 bits and the inputs here are A, B and borrow input that is B in and the outputs here are B out that is borrower output and the difference bit. So this is the truth table for the full-subtractor circuit. You can go through the truth table. So the difference in this case comes out to be B in XOR operation with A, XOR operation with B whereas the B out comes out to be A bar B plus A bar B in plus B into B in where B in nothing but the borrow input. So these 2 equations we are going to implement in our module definition. So this is the verilog module definition for full-subtractor circuit. The module definition start with the module keyword. These are the list of input and outputs. The input and outputs are defined here and here these 2 lines are important for implementation purpose. So here we are going to write assign diff is equal to A, XOR, B, XOR, B in. So which is going to assign the XOR operation between these 3 bits A, B and B in and this is going to be assigned to the diff which is our output. Then this B out is written as A bar and operation with B, this is odd with the A bar and B in and this is again odd with the B and operation with B in. So this right hand term will be evaluated and the output calculated will be assigned to the B out here. So we are going to end our module definition with the end module keyword. So this is the verilog test bench for verifying the correctness of the full-subtractor module. So this is also a module definition. So test bench is also a module here. So module test underscore full-subtractor. Similar to the previous videos where we have written the test benches, the inputs in this case will be defined as a rect data type because you want to store the values there in the inputs and the outputs will be defined as a y data type. The next line will instantiate the object of the full-subtractor module. So full-subtractor space fs1, fs1 is the name of the object and this is, these are nothing but the list of, these are nothing but the arguments. So the arguments here are a, b, b in which are inputs and b out are nothing but our outputs. So once again between initial begin and end, we are going to provide all possible input combinations. So on your screen, these are the two module definitions. One for full-subtractor circuit and one for its test bench. I have saved this file with the name as test underscore full-subtractor.v. Let us compile, let us check our compilation is successful or not. As you can see, there are no errors and warnings, so our compilation is successful. Let us go to the work library and in the work library you can see there is test underscore full-subtractor, let's simulate it, let's go to the add to wave, all items in regions. So here you can see there are three inputs namely a, b and b in, two outputs diff and b out, so let's run the program. So this is the simulation output and you can see here for the inputs 0, 0, 0, both the diff as well as b out is 0, 0. So for the next input combination that is 0, 0, 1 we get the outputs diff as 1 as well as b out also as 1 because you are doing 0 minus 1, so that is why both will be 1, 1. For the next input combination 0, 1, 0 we can see both diff and b out are 1, 1 and similarly you can verify the correctness of our full-subtractor module from these waveforms. So these are the references. Thank you very much.