 We start with the new topic today, power estimation and control in CMOS VLSI circuits. The idea behind power estimation will be very clear to you, but before that let me tell you what I am going to talk in this lecture. I have following points in which I will elaborate this. Not necessarily one lecture, it may be more than one lecture, may be two or three lectures, but today we will start on that line. We will start with introduction, then we will say why power and what is the relevance. Then we will talk about device parameter variation and impact on design. And then we also talk about impact of CMOS logic style and then the leakage impact on design styles. We will look into very important aspect which is worrying most for designers is the interconnect power. And then we will conclude. Now this slide is from IBM which shows a system performance of any electronic system performance and the way we said they said it is called an integrated approach. So if you see from the bottom side, you can see there are things we are giving different colors technology, chip level, system level applications. The basic idea for those study is that if you look at the performance and we look into the technology generation over the years. For example, as I said we started with technology way back in 1960s, we went for SSI, MSI, then we went to LSI, VLSI and now we are continuing ultra large-scale or called advanced VLSI circuits. So if you look at the technology generation nodes from technology side and we see look the performance, it clearly shows what was expected by the scaling theory which is the green color. And that was expected as the technology start improving that is from nodes of 113 nanometer, 90 nanometer down to 28 nanometers now. This was expected performance. The industry is that reddish one you know which is recently one sees it is already tapering down now. It is not improving. And if you see the worst performance of this chip which is much below which is called the slow chip performance. So frequency no longer now dominant the performance of the driver because the technology is driven by something else. The advances will come from entire performance stack rather than only frequency of the circuit or frequency of the device. So if you look at the right side, you can see that the technology essentially is one is talking about memory options, we are talking of which memories, then we are also talking about packaging possibilities, we are talking of cooling, we are talking of at the chip level compiler support, we are looking for multiple cores, SMT accelerators, power shifting interconnect circuits. Higher level we may look for dynamic optimization, then we are looking for threads fast like multi thread circuits are very common these days program is divided into multiple parts and multi processors actually to multiple threads and the circuit can be made much faster. Then there is a faster computation migrations, power optimization compiler support and then the finally at the application level we are looking for languages, software tuning and different technology programming or performances. So if you see the as you go from technology level to application level, there are different ways in which optimization can be actually attained. Now what is the challenge of today, one can see from here this is another IBM slide which has the four important problems in the VLSI design or VLSI system realizations. One is the performance which we have been talking years and years after speeds. So this is a microprocessor speed clock frequency which is as per the ITRS source the frequency against years which is shown here to 2060, 18 or something. We are expecting something like 10,000 gigahertz kind of approach or more than gigahertz of approach and if you look at the other parameter of variable is called power management and this is the where this whole lecture is going to be. So I other day also said you that there are three kinds of circuit which worries us in design. One of course is we say active power related to active when the device or circuit is performing and the other like a mobile phone we have a power which is called standby power. So if you look at the gate length versus delay one can see from here that the active power increases as the gate length decreases from say 1 micron down to 100 nanometers or if we go further below the active power will keep on increasing. However if you see the standby power the slope of standby power with the gate length reduction is so steep that sooner by you know already we have crossed a level when the standby power is larger than the active power and around the so many watts per seconds per centimeter square say the 100 to 200 watts centimeter square at this point by typically around 0.04 micron technology one finds that the standby power is almost equal to the active power and that is more worrisome for us because if you reduce the device by scaling channel length to say 25, 22 nanometers one can see the active power on power may not really increase drastically because the slope is not very high whereas if you look at the standby power by then it will actually overshoot so much that the standby power will be larger than the active power which essentially means that even if we are not performing you are your battery is draining the power. So this is one of the major challenges of today the third problem which we are worried about is the variability. The way it happens that the no process or no design or no technology can control the variability in the processes since we are now becoming a sub 90 nanometer technologies the variation in thresholds variation due to the variation in process parameters on off current trans conductance which are the basic parameters of a MOS transistor they themselves vary. For example in the case of FinFET one sees that if the spacer thickness is different the on current will be most affected compared to any other this. So one is worrying now that if there is a variation in the process itself which leads to circuit parameter variations then the chip performance will be extremely varying and if that so happened one does not know how to design because some devices which may run faster some may become slower independent of what design one does and therefore this is another issue of worry when you start designing a advanced VLSI circuit. Now the fourth if not the it is not directly related to design area per se but which is worrying us most is manufacturability. So if you scale down your features from say as I said 90 nanometer down to say 22 or 16 or 11 or 7 the major worry as I see and everyone is seeing is the lithography problems. The pattern which will become shown on the left when I actually printed on a silicon number of times as the mass may increase to 30 mass for a actual chip manufacture. So it is not transferred as the rectangles or the pluses or whatever symbols you make or whatever shapes you make and if that happens for a transistor if the W bile changes whole performance of the circuit will change. So to transfer an image to a accuracy of what in the some nano some 90 nanometer processes is become another issue of worry ability. So these are the growing challenges they are all interconnected to some extent through device and process. However this part of the course which I am now talking is more interested to know about power management though as I keep saying that none of one cannot say each three of the other ones are not affecting the fourth one. Everyone is affecting the other one and hence the issue. Now what is existing low power design techniques? So one can see from here if you look at the flow diagram of a chip design we start from a system that which is essentially co-design hardware software co-design customizes and here we design algorithms. Then in the next level of hierarchy is architectural where essentially we are controlling or we are trying to optimize things based on scheduling, pipelining and binding and third which is the most popular hierarchy level from where most of the circuits are nowadays designed from their IPs is the RTL RTL level RTL level register transfer level and once you know the IP which has is you have RTL code then probably you all that you need to know there is to clock getting state assignment real timing and things of three timing and things of that kind. If you go this is essentially one group which essentially we say it is more on the software side the whole that is RTL architecture system is more on the software side control though we have to always do hardware software co-design but essentially still it is more software design. If you go down the second triangle below one can see from here the RTL level can then go to logic and essentially we are trying to see that the circuit is any digital circuit is consist of some kind of a logic connected logic blocks connection and you can see the power probably can be affected or changed for low power by logic restructuring or technology mapping and finally the logic is consisted of the transistors and transistor design requires including the circuit design and then the layout and re estimation from layout the logical performance or circuit performance. Now these essentially means you are there optimizing fan outs buffering transistor sizing and also glitch eliminations. Now one can see from here that at different level you are actually working differently to reduce the power. We being more from the say circuit side our always attempt has been to reduce power using physical and logical block restructuring or optimizing the transistors themselves. However the other part of this course solely or surely we will talk about the upper part of this from RTL to system and they also will look into pipelining, binding, scheduling, clock gating and assign state assignments to see how to reduce the power. This is another standard graph available on the net standard figure where do you really can save your power. So, there are I just now give you the hierarchical level from system to physical. So, of course this figure is slightly need to be modified now because the this was at least this was essentially available for 90 nanometer designs, but this numbers may slightly modify for lower than 90 nanometer nodes. One can save power 10 to 15 percent of the power by just transistor sizing proper fan out that is using logical effort putting placing them properly partitioning properly and how to distribute clocks and certainly how to minimize the glitches. If you can do this then probably one can save up to 15 percent of power using what we call physical design. Now that is basically transistor level design where optimization can be tried circuit level design. Then the next level next 10 percent of the power can be minimized at the logical level where you can actually can decide as we saw you know you can have a branching, you can change the gates, you can logically restructure, you can then actually map the technology and you can say some parts are critical. So, you need not have higher thresholds or I mean you need not a lower thresholds. And then also we can rewiring pin ordering and phase assignment can be done if we do that another 10 percent power can be minimized. Then the at the RT level or RTL by properly optimizing the gating clock gating, pre-competition operation isolation and state assignment and re-timing blocks probably we can say another 15 percent of the power very large amount of power can be actually minimized at RTL level. So, by then the first last three hierarchy probably you can go up to 40 percent. So, one can see that even with all the effort we do in the discussion we do hell of it in the design and we keep showing you slides about the physical, logical, RT level designs the best of approach even there can get you around 40 percent of optimization on power saving. The remainder power can be really worked out well by at the higher levels of hierarchy in design which is behavioral and system design. So, in behavioral as I said shriveling the task, threading the task and binding them at given time then pipelining and looking for performance using behavioral how much data to be required when and how to minimize that. So, if you look at the behavioral representation of the logic you are implementing or system you are implementing some of those standard methods can be used to reduce another 30 percent of the power which is very large power reduction compared to the first last three one which only could be add up to 40 percent. And to a great measurement the system level design can be particularly algorithm based designs or using custom chips away or custom ISAs away designs available and using more SOC or SIP kind of technique using hardware co-ware designs hardware software co-designs probably one can do even the remainder 30 percent or at least another 10 to 15 percent of power can be minimized right there. So, when I say I have opportunity of power saving I must realize that there are different places of any logical in a system design where power can be minimized. However, as being what I am and as being most of my colleagues for the design course which is more circuit oriented from our side we will continue to work mostly for last three one art level logic level physical level design approach where the power can be minimized. I am not saying that the other two are not relevant, but this course probably will not because this course is taken care by other people in the computer science area. So, one can again see timing time required to do optimizations this is called inverted matrix system. So, if you look at this for example, a transistor level possibility the parasitic extraction accurate timing analysis circuit level simulations and you may it may take hours and it may actually add to 10 percent of error in calculations in as designing and it takes hours actually. Actually logic circuit level or transistor level design is very long if you have to run spies or specter or model same kind of equivalent of that and then it takes hell of a time if the circuit is large. Then the next level at the gate which is probabilistic simulation gate level simulation sampling and compaction ASIC library models by putting these probably you can do power estimation much faster related in hours and the error can be around 10 to 20 percent up to 20 percent error with this two together can lead to. At the RT level things can be done in minutes and you can do micro models you do HDL simulations and very quick synthesis can be done to actually do RT level designs for power optimization, but you may lead to another 15 percent of error in your all your designs. The fourth architectural you have a entropic bands architectural simulation IOs and memory accesses they are decided architectural level and if you particularly look for entropy minimization I think you have another 10 percent of it may do very fast calculations for you to reduce power but will take 25 percent error bars on that because it is mostly statistical things goes there and it is very difficult to control exactness on that. The finally at the system level you may do very very fast instruction level models IP core models stochastic models and program if you have all this the realistic estimation expectation can be made but possibility since you do very fast quick thinking quick analysis you have largest amount of error possible in your design. So, having told that what are the challenges for system people and having told that power is the major criteria of design if you see our earlier courses I have in my earlier VLSI design course I used to draw a triangle this triangle this triangle has three corners one of them is essentially what we say power the other is speed and the third is area so when I am designing a simple IC integrated circuit I see that this forms power speed and area forms a triangle what triangle essentially means so if I am optimizing anything let us say I want to minimize the power so obviously what can say if I reduce the power down the speed means actually delay so it may actually lead to larger area or lower speeds or area being same so or the on the contrary if you want to improve speed that means you reduce the delay then the you may require much higher power to generate and if you still want both power and speed speed be faster power be minimal then probably you may at least have to give larger area on the chip that means the yield and the number of chip per unit area will be smaller which means the cost of chip will increase so essentially this optimization is also not very very simple in most cases we have to do tradeoff we say okay this much power and this much speed is possible at given package area or given chip area and that is what the best designs probably could be and this optimization of course we have been trying and particularly for MOS circuit this can be understood at least the power speed can be understood very quickly from you let us say I take a case of CMOS inverter this is a P channel upper device this is N channel device and it has an input capacitance of Cn and I am putting an input Vn which is a step and I am picking up an output voltage V0 across the net output capacitance or load capacitance here so basically what we are saying the speed is decided by charging and discharge transition as we looked earlier that is time taken to charge the capacitor and time taken to discharge the capacitor propagation delay essentially for input to go to the output is tphl plus tpllh by 2 average delay to improve this tpllh or tphl we say actually increase the currents and if you want to increase the currents for discharge and charging transient these devices must provide you that large currents but the current in MOS transistor is proportion to W by L for a given silicon technology and given technology node where COX is fixed so we figure it out that the only way to improve currents in design is to increase W by L but if I increase W by L essentially I am saying larger area and if you have a larger area the input capacitance will also increase so we figure it out that by increasing the current which essentially we improve the speed we actually landed up in larger area but apart from area if the currents are larger in a circuit and as we shall see later the power is essentially proportion to current so larger the current dissipation larger is the power dissipation so at attainment of a higher speed was at the cost of larger area and at times larger more due to larger currents and at times larger area so when I design a circuit or a chip I am really looking to optimize such that I do not give too much of a power but I still improve speed and I do not have to really reduce my increase my area if I can do that then what is I have done an optimal power optimal design so as I say our ultimate m is to say 0 W per centimeter square power density speeds of infinite hertz and area probably 0 which is the ultimate values one probably can think but how best we can achieve three together is the effort in all circuit design and therefore and also the system design so we start with the first thing we look into the power from the transistor side is coming from the device okay and so while low power devices would be required in our designs so the fact is there are practical reasons what are those practical reasons reducing power requirement of high throughput portable applications because you know after all if you have a portable like PDA if you have a mobile or any of this iPads or iPods or tablets you are carrying them in your hand and there is no additional power supply coming from anywhere so internal battery itself is essentially trying to give the power and you also want for example these days newer tablets or smartphones if we will show you some slides on that they are doing multi functions too many functions including video audio camera and also do digital normal processing internet and of course telephone at the end of the day and we are reading books out of it and we are we are doing all kinds of processing on a tablet or smartphones and many other phones as well so since your throughput is very high and the it's a portable and the battery is limited we are looking for device which will reduce power okay that means the battery can last longer before it's recharged the financial reason is very important at the end of the day we all look for money so here is the problem the larger the power dissipation you do the package has to actually dissipate that much power and because of that since the packaging cost goes higher with the number of pins and the size because to manage it not simple so financially it is not very great thinking if you have a larger packaging cost for to get that extra power which you are looking or so we need to reduce the power simply because the packaging cost we want to reduce also we if you do not have larger this we can also achieve memory saving because you don't have to keep keeping data because something else has to be done in between the third which is what most of us believe is the reason of thinking for us is the technology reasons for example if you have very high density appearing on any chip being used you can see the chip has a larger thermal dissipation around the temperature of the silicon areas may increase and many of the functions may not remain those functions because of the ill performance of the device itself due to heat so if you look at the portable applications market of portable application is growing rapidly over the years of course this is the old graph from Intel one can see 95 we are around 500 millions per units millions of units today in 2000 this is more than 2000 millions units are required for cellular market and in India itself has the largest cellular market of course density it's not that high even now for the population but the number of cellular phones are really much higher than even US market as of now and therefore you must have observed that most of the cellular companies are trying to buy to enter Indian market and the result of course is well known everyday newspaper is just talking about it so here is a smartphone just look at the smartphone blocks inside if you look at a system there are of course there are not just eight blocks some of them are included in this but general major blocks in a smartphone are the following there is a display which all of your CS which is called the the center one is called bus bus structures so we have a display then we need a processor to do all the jobs so we have a processor then you need to have connectivity externally so you are looking for a usb connection it can be your system should be able to connect to any other internet or any other drives or anything which is the usb connectivity for that that's one something like connectivity is something different from some of the smartphones like i'm told between samsung and ipad or iphone that that's major difference or between ipad and samsung tablet that's the difference tablet has a usb connection then we of course need a receiver transmitter at that frequency of operation because that's what a cellular data is coming or going so it's unique from the antenna connection to receiving transmitting system and these are of course online high frequency things going on however there is other area where data has been to be processed for example you have a lot of memory interface because some data has to be stored some data has to be temporarily stored before it is passed on like you have sms messages going on and then you are receiving in between and they do have an interface between stopping between mail for these sms and phone together and you need data to be cached somewhere and there are a lot of memory interfaces required for the data to be stored temporarily or permanently then there are blocks like image processing after all every these days have a camera and even if not camera you may have internet which may have a figure most of the video pictures or video disc so you need to process that data and therefore in the image processor has is a part of any smartphone these days then to get this audio video data in a proper format which can be done processed we need an audio codec and a video codec so if you look at the any smartphone block diagram these are the major electronic block which constitute the working of a smartphone these are typical specification which smartphone gives for a specific list for example you have a processor pd processor you have typically if this on then it is 1.2 volt battery is required text is 1 volt phone is 1 volt image of course 1.2 volts camera requires 1 volt supply playback is required 1 volt game requires 1.2 volts standby required 1.2 volt and in off mode we do not want any power okay this is a power requirement shown here power dissipation i am talking about power dissipation in the receiver processor of course is the first one in the case of transmitting receiving system you have power supply requirement on on when 1.2 text you need 1.2 volt supply and for the access remixes of this your you need small much smaller power is 0.8 camera is not on when you are transmitting receiving a data except when in standby you still need 1 volt supply if you look at the display almost except for the case when the you are you are listening phone you do not need display because you are not seeing the display and therefore that can be stand down to 0.8 volts supply but the all other places except for standby and off mode you want 1.2 volts supply now if you look at power dissipation image code image processing chip part then except for the processing access of the internet everywhere else image processing requires 1.2 volts there is no game when you are doing already your data stored so you do not need power in standby or off state and if you are the rest of the power dissipation except for the PIM access and the standby this you require constant power camera when you are actually doing this camera requires much lower power because you may not actually operate it but you want to use in between any data to snap and transmit then you need some camera beyond so these are called power domains and power modes for a smartphone chip so one for any system for example this is a system I chose to explain a smartphone but you make any other system you will have to first design that system level this and then break it into architecture or at least system subsystem blocks and then you will have to choose an architecture to implement this and from there probably you will be able to get such a power domains and power modes for a chip and then start looking that okay since you require power supply sometimes you do not require power sometimes so the circuits which will operate when need not in some cases may not have a larger power dissipation required in some case they are larger power and therefore corresponding power dissipations can be managed I already said I may repeat again fully functional mode of a smartphone where all power domains are on and working full VDD a texting mode where the image processing and the rest are turned to a low voltage mode a phone mode when the transmit block is fully on a PIM access mode when the image processing is turned off camera mode when the image processing and displays are on playback mode when the display unit is fully on game playing mode when the processor display units are turned on the rest can be switched off and a keep alive mode that is stand by mode when the processor is on transmitting is low and still on for any time and of course off mode means you actually switch off your mobile phone here another interesting picture of the same you know many of the circuit will come back this later again when the device is in the sleep mode there are three basic part where power is consumed when you start a device that is called wake up power wake up power mode when it is operating all the time we say it is active power mode and when you are you are not fully switching it off but keeping in a standby mode then it is called sleep mode power so if you look at typical low power design guide this is a figure which gives you some idea where the power is going to be controlled so for the sleep mode the power dissipation is rather smaller and can be managed relatively relatively simply the second power consumption comes from the is vested in the wake up and this is transient kind you suddenly wake up all circuits have to turn on from their off modes and they actually have a much more transient power dissipation during and it does not it does not finish very fast or something though externally you feel only milliseconds or something of that kind but nanoseconds but actually it takes milliseconds and the power dissipation is not very small it is a transient power and it actually takes quite amount of power which integration wise will be larger than the standby mode power and of course the largest power will be consumed when the device is fully on and among them which for a smartphone for example not all system will be on but on average some will be on all the time except for the off mode and in that case the power will be constantly consumed so what is the driving force for low power battery limitations so one says driving forces for low power battery limitations come from the fact that you know in 97 we have a maximum power wattage for 1.2 and in 2012 it is 3 watts of power is required actually more right now it is a 4 and half watts of power is required currently so if this is the power requirement the battery maximum power and capacity increases only 10 to 15 percent per year three batteries shown here one of course is standard nickel cadmium though people used to say it is a workhorse battery right from 60s to 90s it is still working and still available of course but you can see its power this is capacity is not increasing very much it is going from 10 to 20 25 maximum whereas the other possibility was nickel metal hydride kind of batteries and after 90s people have started working on it and we are going from 30 watts sorry 3 this per this to this and if you look at the rechargeable lithium ones it is around 60 watt per this so what we are trying to tell you that as the year progress the required battery improvement is still below the power requirements and therefore there is always a gap between the power demand and power supplied by the battery so one basic idea is that can we if we cannot improve the battery of course rechargeable will require quick recharging that is one possibility which we are anyway using but the other method probably could be can we then minimize the power requirement itself and if power and capacity decrease is not increasing with this rate per year then probably we can have a battery which can last longer for your work but that is what I keep saying that the low power circuit is demanded simply because there is huge limitations coming from available batteries as of now one of course joke I always say why work on VLSI why not work on batteries probably if you get a patent on a better battery it may fetch you lot of money and maybe it will revolutionize everything ahead before we start really working on it let me tell you what exactly has worked over the years on a scaling law when you start scaling from say micron 5 micron down to 22 nanometer process at different technology nodes we are scaling voltages as well as we are scaling dimensions and therefore corresponding process has been scaled but as we kept selling earlier in our first history chapter or per history perspective chapter we said voltage is not scaling with the scale law and therefore fields are increasing even if the lengths are reducing and that is our major worry and that is what the reason why power distribution is increasing the second of course as we still have reduced voltages we went from 3.3 to 2.1 to 1.5 to 1.2 0.8 0.6 0.5 I think there are some chips available now with a half a volt supply so there are effort are going on and to great extent we are successful however voltage scaling below 0.4 or something will be very very difficult task because firstly the noise margins will be so low because the thermal noise at room temperature itself is around 4 kT by Q or 4 kT and which means around 100 millivolt is a typical noise even without anything and if the temperature start heating on the wafer which it will because of a higher number of devices on chip this number may actually be larger and if this total noise power is increasing then the signal power and noise power may be comparable and one may not be able to differentiate between an off state and an on state of a digital logic. Therefore all said and done voltage scaling may not be the final option though it is because in every power dissipation if see voltage term will appear i into v so v reduction is definitely going to reduce the power and there is no denying on it. However as I said it is not scaling as the other scale other factors being scaled and therefore power is not getting minimized to that new node which by law of scaling should have. The second method which has worked in design of a low power circuit is essentially design methodologies. We have started looking into power of a design flow than tools and we start trading areas for low power. Instead of speed we are always trying to trade now on a area because most of the low power designers do not mind giving little bigger chip but they certainly need low power whereas many other high performance circuit may do otherwise they may say we do not mind too much of a power dissipation but we want higher speeds. So we are trading on either of them and for that we are looking for design flows we are actually looking for everything which is right from system level down to a logic or transistor level we are actually designing what we call power of a design. For example major work is right now power of a design is to data transfer from one point to the other through an interconnects and people are looking for whether it should be driven by current modes or it should run by voltage modes and what kind of power can be saved by using part of analog blocks inside. So yes there is a trick going on to reduce the power by what we call power of a designs. The other of course is change the architecture so that the data required does not require every now and then to flow from different places and we will see that architecture design play a lot of this in reducing the power. Then the another circuit level method which one is looking into to reduce power is what we call plower down techniques. We are trying to use clock dating essentially it means whenever you need a data you clock the data else do not allow it to work on constantly. So that no data transfers still it is required so as if the clock average clock is flowing down and hence at least the dynamic power is minimized and of course there are other techniques of dynamic power management which is being tried using many other techniques we will see in this part of the lecture. Then the fifth possibility of reducing which has worked is dynamic voltage scaling based on workload. This is called appropriation of voltage at different say more than one voltage which we call dual VDD or dual VTH kind of approach in which we can assign voltages VDD supply value from say let us say you are working on one volt. So some circuit may require 0.6 some may do 0.8 and some at the best of it may require 1 volt or 1.2 volt whichever is available to you. So we say power management using voltage scaling can be tried at different workloads. In doing so we may also actually scale the threshold voltage we say a dual threshold or multi threshold circuit can be tried threshold can be actually controlled using number of weights and one will see how to scale the VTs so that one can do lower dynamic power dissipation. There is a constant effort going on on the RTL logic which we write or do logic synthesis can be reduced the power during RTL. RTL essentially represent the module which does some kind of a function. So can we see that a function is one which is simpler function compared to a larger function. Can we synthesize such a logic using a much different way which will reduce the net power consumption because the amount of logic synthesis amount of logic transfers it will do will be lower. And of course one simplest way of doing things what people are doing right now at least using the cell library design technique we already have pre-designed blocks with low power dissipations. And design such library functions you keep resizing them if necessary W bile may be changed which reduce capacitance which changes the thresholds and also layouts of the transistors. Using all this you can create logical blocks of which are slightly better optimized and you have large number of library functions which gives you variable power dissipation and corresponding speed and areas. So this is what has been tried or this is what has worked so far and based on this essentially one can see that one will be able to reduce the I mean effort to make the low power dissipated chips and we will continue with this effort ahead. This is an interesting figure which many of the designers VLSR designers do not look at it but this is a system design point of view. Here we are plotting power versus time that is essentially I am plotting energy. So instead of just looking into energy power we should actually start looking into energy dissipation because that is something which battery has to provide. So what do we do there? We say there is a line which say average power. This is my average power this line and we say this is essentially governed by the battery lifetime. So let us say battery is drawing so many so battery has a capacity of so many ampere hours and for your circuit the net current requirement for different blocks sum up to some currents. So we say that okay average power ampere hours if given to you. So how many hours you want battery to last correspondingly that much average power or current should be drawn from the battery. So once we decide this this line can be drawn. Now once you say this is your average power to be given by battery for a given time for a given lifetime of a battery the next worrisome problem is peak power. So one some part of the circuit or block at times may overshoot your average powers as shown here and this peak power related to of course the how much maximum one can allow these peaks to go is decided by heating up the device essentially leading to thermal failure and there are also reliability issues. I am not sure whether we will be able to talk technology here as much larger the transients occurring a peak power occurring there is another worry right now going on increase of local power densities which may lead to what we call electro migrations and that may open the interconnect lines. So there is a huge reliability issue if the peak power is very large. The third point of interest is the RMS power which is related to cycle by cycle power. Now this RMS power essentially is the power because if there is a variation in the power requirement of a chip then one should worry about the not just the average power but we should also worry about the RMS power for every clock cycle how much is the power really delivered is essentially very crucial because that will decide the net power dissipations. So you can design a circuit which has a lower RMS power requirement and you can design a circuit which requires higher RMS power requirements cycle to cycle. So some cycle may require larger power some may not and therefore one can probably manage low power by actually adjusting your RMS power every clock or at least number of clocks if not every cycle clock. Finally as I keep saying at the end of the day why we always worry so much about power one should really worry about the power into time which essentially means that we should worry more about power delay product rather than either speed or power. So if you want a larger speed so lower delay and you want a low power so we are now trying to say if you want to minimize energy essentially you must reduce the power delay product and if you can do that your battery will last longer this is essentially because please remember battery supplies energy and this is stored by the process of battery itself ionization initially and therefore how much energy you consume will decide the battery life and therefore the effort in the power low power design should really actually shift to low energy designs in many cases which may be more relevant parameter. Now if you look at this is a Hayes paper on appearing way back in American scientist journal this is a computer and the very nice interesting article if you happen to read this September 2002 Mr. Hayes has given a very interesting comparison there. Now he is talking about let us say because you can see since it was old one so it is a Pentium 3 he is talking about the 500 megahertz Pentium 3 70 which is which is put which has a system has a PC which we are talking is a 17 inch monitor 150 200 watts power it consumes server requires around 300 watts power. So this Pentium chip may require around 15200 server may require 300 watts of power main frame may require 10 to 20 kilowatts of power the author means they are home the he is talking on holes he has two computer two CPUs two monitors laptop three printers scanner plus miscellaneous peripherals he holds and if you add all this nameplate ratings okay you have around 2.4 kilowatts maximum power including peripheral 700 watts typical usage is 150 to 171. So if we average over 10 days 77 watt is 10 days average 9 percent total consumptions. So one can see you seem to believe that the power even if you are using PC at home where is a good fan so there is no thermal dissipation is problem so much how much power really we are consuming when we are actually using a that means you are using 200 150 to 200 watts of power are equivalent of a bulb which is constantly usage by you and then average if you do not use longer time computers hopefully these days this number is not valid because almost 90 percent of the students and faculty as 90 percent of their time is on computers and therefore this wattage probably may be very very high compared to what 77 average he is talking about may be as much as 770 may be the numbers now he is of course talking of power consumption in USA we can do similar analysis for India again this is 2001 paper so please take it later pinch of solver 2012 but all the same this gives the numbers all office equipment consumes 74 terawatts hours per year about 2 percent of us total adding telecom increases to 3.2 percent power down and sleep modes could save 2340 terawatts of power terawatt hours technology has dramatically improved power cost of computing in yak require 18000 vacuum tubes 174 kilowatts roughly 10 watt per tube today's microprocessor is 100 million transistor plus 100 watts roughly 1 micro watt per transistor of course nowadays it is not that low or that high in all processors so since we can reduce technology dramatically this cost one can see that even then the 3 percent of the net power consumption goes into only computing at homes okay and talking to people okay so one has to worry now that when we are when we talk about power dissipation and power I mean reducing the energy we talk of hell of others but no one talks about computers no one talks about mobile but the number right now is so high increasing day and day out that worry may start now that this 3.2 percent may become as high as 25 percent sooner and then people will suddenly woke up and say oh there is a energy classic my mobile is not working okay so how can we quantify quality of design this may be one last slide for the day when I design a chip or when I design a system want to compare designs quantitatively on a level playing fields you know you cannot have two different people designing at two different tools at two different technology then compare so there are two few things we should have common so that we can compare two characteristics we care most about delay and power consumption these are the two specs we must look into and we know that delay and power are related and therefore first thing you must compare any design on these two parameters CMOS logic operates by moving charge from one point to the other during on and off capacitors and therefore we are looking for fast energy transfer implies higher power consumptions means faster logic gates so if you are looking for higher speeds you in build situation is you have higher power consumption these are few slides which we may come back again this is the old size the die of this microprocessor has increased size for example we started with 2 mm by 2 mm size chair this 2 or 3 and now we are talking of 2 centimeters chips by now so 2 or even more p6 is already 2 by 2 centimeters and maybe the next version now 4 quad 4 with p6 on this ethylene has something like 3 centimeter by 2.6 centimeter size chips so there is a 7% growth per year of the size and 2 a growth in last 10 years because the die size is increasing the number of transistors which are going on them is increasing and therefore the power dissipation is increasing per chip and this you can see I keep saying die size always increases because Moore's law has to be satisfied so we are only increasing 7% but actually one expects 14% die size increase if we have to follow Moore's law that the transistor density doubles every year if you look at the clock frequency then you can see by 2000 we are already cross gigahertz and one believes that we may are looking of course I am not very sure whether to this of course is only arrow but by 2030 or something one is expecting that we may work on k bands 60 kilo gigahertz chips one has to keep your fingers crossed because what power dissipation they will talk we have no idea as of now so elite micros you can see doubles every two years this is again Moore's law in other form if you look at the power in microprocessors 4004 the first microprocessors to Pentium probe p6 old slide from Intel all that I am trying to say you that it went from say 0.2 watts now we are talking of something like 30 watt to 40 watt per chip and if you look at the increase in between 8086 there was reduction in power but then now it is increasing day in and day out power deliver and dissipation will be prohibitive if we continue to go by the straight line as shown then the power dissipation will be extraordinary and here is the last graph showing that power density by 2000 we have already temperatures which are power density equivalent of a hot plate we are reaching a place which is 200 watt per centimeter square which is roughly like a nuclear reactor power density and if we continue to grow as we are looking for it will be 1000 watt per centimeter square which is like a rocket nozzle temperatures power density so if you are really look very if you are designing a chip with anything the first worry is how to avoid power densities of these two we are already here we are trying to dissipate this power itself and if you unfortunately reach on these lines one doesn't know how will you really reduce the or dissipate the power and how how the cooling methods can be employed is too high and we remember higher the temperature junction temperature rises leakage current increases the concentrations of p and n also increases and finally the junction breaks down because one say there is no junction both both side equal concentration of carriers occur so at higher junctions higher temperature junction device may not operate so we must keep temperature junction school okay so these are the kind of power we are going to work on to reduce the device this is my last slide for the day we will look into CMOS alone right now there are other technologies but this course is strictly following as if we continue to work on CMOS chip design so we are looking for reduction in power in dynamic power which is essentially charging discharging capacitances then we are looking for when the transition occur p channel turns off and n channel turns on vice versa occurs both are any one is off the other is on but when they switch over both are on for a while and that time we say it's a short circuit current then there is a static current particularly in analog and also in saturated load or unsaturated load and mass inverters or those kinds which are mostly popular in HEMT or gallimars and devices so there is a constant power supply to ground connection we say that is a static power consumption and particularly like in a bias circuit in an analog has to be constantly on because even if your defam is not amplifying signal is not there this keeping defam at a particular biasing point has to be on all the time so there is a static current dissipation in most of the chips right now and that has to be taken care and finally if not the last I would say the major worry of 2010 above is this power which we call a off power which essentially occurring because of the leakage we believe when the Vn is less than threshold volt than threshold voltage then the device is off but in real life the threshold definition itself says that from the when the band bending is actually two times the Fermi potential phi f then only but essentially that means the inversion should have occurred when the surface potential is equal to the Fermi potential but the actual definition says two phi f which means even below Vgs below Vt there is a sub threshold leakage sub threshold current flowing and that is the major leakage worry because the slope of sub threshold slope in the new devices is too high and therefore the leakage is very high it is not 60 volt per decade or 60 millivolt per decade that is our major milliamp per decade so this is major worry for us the other of course is the source drain have a diode forms a diode with the substrate so there is a reverse bias diode leakage currents because of the doping we are going to use now this reverse leakage current should be very high and then there are many other leakage current and one of the top leakage current possibility is the gate oxide tunneling or it may be what we call griddle gate induced threshold current or the currents because of what we call change in double values and things of that kind so if you see if I want to reduce a CMOS power in which the static power of course one may say is not there at least dynamic power the short circuit power and the leakage power essentially occurring because of the static current leakage current and charging the charging currents that should be minimized during the process but when you reduce the currents we know from our theory that the charging current or a charge current reducing will improve will decrease the speed or increase the charging time or discharge time so the circuit will become slower so for a given speed what else can be done to minimize power this is what in this course ahead we will be able to talk on all these fronts what are the ways we can actually minimize the power thanks for the day