 Hello and welcome to this presentation of the STM32L4 flexible static memory controller. It covers all features of this interface which is used to connect external memories such as NOR Flash, NAND Flash, SRAM and PSRAM. The FSMC controller integrated in STM32L4 products provides external memory support through two memory controllers. The NOR Flash PSRAM controller and the NAND memory controller. This enables the CPU to communicate with external memories including NOR and NAND Flash memories, PSRAM and SRAM. This interface is fully configurable allowing easy connection with external memory or other parallel interfaces. The benefits of the FSMC controller include not only RAM and flash memory space extension, but also the ability to interface seamlessly with most LCD controllers which support Intel 8080 and Motorola 6800 modes. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules containing embedded controllers or high performance solutions using external controllers with dedicated acceleration. The FSMC controller offers two independent banks to support separate external memories. Each bank has an independent chip select and an independent configuration. Each bank features programmable timings, a configurable 8 or 16-bit data bus and can access memory in asynchronous or burst mode for synchronous memory such as NOR Flash and PSRAM. Synchronous memory can be accessed at a maximum frequency of HCLK divided by 2. The FSMC controller supports a wide variety of devices and memories. It interfaces with static memory mapped including static random access memory or SRAM, read-only memory or RAM, NOR or one NAND flash memory and PSRAM. The FSMC also interfaces with NAND flash memories and supports error code correction or ECC for up to 8 kilobytes of data read or written. Three interrupt sources can be configured to generate an interrupt when a rising edge, falling edge or high level is detected on the NAND flash ready busy signal. Furthermore, the FSMC interfaces with parallel LCD modules supporting the Intel 8080 and Motorola 6800 modes and is flexible enough to adapt to various LCD interfaces. The external memory space is divided into fixed size banks of 256 megabytes each. Two external memory banks are dedicated to the FSMC. Bank one is connected to the NOR PSRAM controller and bank three is connected to the NAND controller. Banks two and four are reserved. Bank one is used to address up to four NOR flash memories or PSRAM devices. This bank is split into four NOR or PSRAM sub banks of 64 megabytes each with four dedicated chip selects to interface with. Eight or 16-bit synchronous or asynchronous NOR flash in multiplexed or non-multiplexed mode. Eight or 16-bit asynchronous SRAM and ROM. Eight or 16-bit synchronous or asynchronous PSRAM memories. The FSMC outputs a unique chip select signal to each bank and performs only one access at a time to an external device. The external memories are connected to either the NOR PSRAM controller or the NAND controller and share address data and control signals. The NOR PSRAM controller allows configuration of various timing parameters for the supported memories. Address setup phase, duration of the first access phase. Address hold phase, duration of the middle phase of the access cycle. Data setup phase, duration of the second access phase. Bus turnaround phase, duration of the bus turnaround phase. Clock divide ratio, number of AHB clock cycles, HCLK, within one memory clock cycle, CLK. Data latency, number of clock cycles to be issued to the memory before the first data transfer. And access mode. Bank 3 is used to interface with the NAND flash memory. It is divided into two memory spaces, common memory space and attribute memory space. Both spaces are similar. The common memory space is for all NAND flash read and write accesses except when writing the last address byte to the NAND flash device where the CPU must write to the attribute memory space. This allows you to implement the pre-weight functionality needed by certain NAND flash memories by writing the last address byte with different timings. Each memory space is subdivided into three sections. Data section, 64 bytes, used to read or write data from NAND flash memory. Command section, 64 bytes, used to send a command to NAND flash memory. Address section, 128 bytes, used to specify the NAND flash memory address. The FSMC generates the appropriate signals to drive NAND flash memory. The address, data and control signals are shared with the NOR-PSRAM controller. The command latch enable or CLE and address latch enable or ALE signals of the NAND flash memory device are driven by address signals from the FSMC controller connected to address line 16 and address line 17 respectively. The ALE is active when writing to the address section and the CLE is active when writing to the command section. The FSMC NAND memory controller includes support for the following features. Error code correction. The ECC algorithm can perform one-bit error correction and two-bit error detection per 256 to 8,192 bytes read or written from or to the NAND flash memory. It is based on the Hamming coding algorithm. Three interrupt sources can be enabled to detect a rising edge, falling edge or level on ready busy signal output from NAND flash memory. Weight feature management. The controller waits for the NAND flash memory to be ready before starting a new access. Each memory space, the common and attribute can be configured with different timings for the NAND flash's command access, address write access and data read write access. The attribute memory space is used for the last address write access if the timing must differ from that of previous accesses in case of ready busy management. Otherwise, only common space is needed. Four parameters are used to define the number of HCLK cycles for the different phases of any NAND flash access. Setup time, wait time, hold time and data bus high Z time. The NAND controller offers three interrupt sources, rising edge, falling edge and high level detection on the FSMC INT pin when it is connected to the ready busy signal from the NAND flash memory. The FSMC is active in run, sleep, low power run and low power sleep modes. An FSMC interrupt can cause the device to exit sleep or low power sleep mode. In stop zero, stop one or stop two mode, the FSMC is frozen and the content of its registers is kept. In standby or shutdown mode, the FSMC is powered down and it must be reinitialized afterwards. Wearable applications require low power management together with a high quality user interface. This can be achieved using the STM32L4 FSMC to connect the display thanks to its flexibility and widely programmable parameters to interface with LCD modules. In addition, the FSMC or QUAD SPI interface may be used to access an external flash memory containing all of the graphical content needed such as background images, high resolution icons or fonts to support multiple languages. Additional audio data for ringtones can also benefit from the large space offered by the external flash memory. Thank you.