 Hello everyone, in the last 6 years we saw I just introduced the concept of in this we also discussed the simple flow in summary that is what do we do first first we load up the library we read the design we set the design constraints and perform the steps of perform the compile. Now, I will take up each of these steps and expanded and present this these steps in much more detail. So, the first thing that we should start with is the library the outline of this lecture is I will discuss the concept of library how these libraries are designed and we move into that and then how the standard cell is selected and combined to form the standard cell library we see the important AC and DC parameters of the standard cell we look at a different library views and then we will go very deep inside in the library file that is the format of the standard cell which is written by the school got led with the short form for liberty. So, we will look at both combination and differential cell then we will move on to design compiler again and I will now introduce how to start design compiler and then since we studied we study a lot about library in this lecture I also touch upon how to set library in design compiler. So, the concept of digital standard cell library is that obviously, it is very clear that any logic function p based using small limited cell like man more and or more. So, the group of the set of these three design limited cell is called digital standard cell library of course, these are digital standard means they can they are primitive regular standard cell like more for example, library is just a term used to use for a collection of these cells. Now, as I mentioned before that we are not looking into how these cells are designed we looked at we looked into the design of these cells between into the in unit 1 and unit 2 that how we set the design using digital, but the designing and there is a process called characterization in the circuit has been taught together. We would during this course we will see how to use them we will assume that these cells are available for us in library format in the proper format and we will see ok what is inside that and how to use it. Now, digital standard cell library contains logic gates which implement the basic building of it. So, now any circuit can be built with minimum basic logic gates we could say that the smallest number of gates. So, the requirement by design compiler is that any standard cell library. So, before you embark on any standard cell library you know should have minimal number of cells and that minimal number is it should contain or and inverter NAND and NOT. This is the minimum number of cells you should have to implement any logic function this is the requirement by Chenosses design company, but is this number enough to do an effective design no. So, although you could start from a minimal library, but the larger and most more comprehensive with respect the better will be your results. The more flexible you give the tool more flexibility to tool cells and therefore, the circuit the resulting circuit will have better area and better timing. Now, in a in a typical let us say 19 nanometer or 65 nanometer technology in industry typically the standard cell library will have at least 200 cell. Let us see how how what is contained in those 200 cell. So, first let us see a Boolean logic let us talk about Boolean logic of it. Boolean logic is simply a set of functions defined on a binary value variable. Now, variable values depending on what tool we are using, what location we are using can be defined in several different ways. One we wrote through calls on a high low VDD VSS or depending on the voltage they will be 2.5 volts 2.5 volts is the maximum voltage and all that. Logic function simply performs the given set of variables in functions and logic function will perform transforming. Just refreshing the concept of basic logic with inverter and and all and not to be distributed. Similarly, you have NAND, NOR, ZOR and X0. Now, how do we choose what cells should go into the standard cell library? How is it chosen? So, first rule is that apart from the minimal function set that is AND, OR, NOR, NAND and NOR there should be a lot of complex functions also to make sure the design is optimal. For example, you would come across MUXS. Now, as we go back and we will see that a MUXS is much more area efficient when done with transition period as compared to normal three months. Therefore, it is very essential and MUXS is a heavily used logical example. So, it is very very important to have MUXS. Again ZOR, XNOR, AND or INVERSE, simple AND ORS or AND. So, it is very useful to have all these different kinds of I would say composite function to have an effective design. Also, let us say let us talk about AND or INVERSE. So, if let us say you want to implement AND or INVERSE function, you would typically need AND or an INVERSE, INVERSE. If your digital array does not have a corresponding AYC. Now, if we go back on paper and try to design a cell, a circuit with AND, a NAND gate, a NOR gate and an INVERSE, you will realize that corresponding CMOS circuit of composite AND or INVERSE is much more small. So, if you see the first example here, the left hand side, this example here, the left hand side, it is this is the circuit on the left hand side is optimized to represent the circuit on the right hand side and it is shown that area goes lower. So, do not worry too much about how the area number came out to be fixed for four, there are just some numbers here. But it is, it can be shown that using efficient logic design, efficient CMOS design, the composite circuits have lower area when implemented in CMOS directly as compared to building that circuit from gates. That is why you will see, you will notice in the database that they are very, very lot of different kind of things, implementing different functions. A lot of them will have INVERSE in the end, because the basic CMOS logic is inverted that is a two input NAND gate is smaller in area compared to a two input NAND gate, because the NAND gate will require one more total inverter. You will not have, you will have lot of INVERSE functions, you will also have inverted marks and so on. Plus, cells perform in same function should be present with multiple inputs that is for example, if you have a two input NAND gate, you could also have two three input and four input NAND gate ideal. I have not seen five input gates till now in the library because the cell becomes much larger and it loses its effectivity, but there are lot of cases where four input NAND, four input NAND, three input or three input NAND, there are used lot of times for the tool. So, you should, you should give the tool enough flexibility. So, we should also have two input, three input, four input type of variants for a particular function. Again, if order for cells to be able to drive large number of other cells connected, let us say now you have multiple fanouts here. A cell is driving N number of outputs. Now, a cell, a basic cell will not have that much drive strength to drive so many outputs. We will see how that affects timing or transmission in later time, but obviously a cell with a big driver at the output stage will not be able to effectively drive a multiple fanout a lot of minutes right. So, the cell has to be strong. How do we make cell strong? By increasing W by L the ratio of the output stage by having multiple by having a strong inverter at the output stage. So, we should have some cells which can effectively drive high power. Now, assuming that so let us go to the first slide in here. You have let us say F functions, F cells which represent different complex functions. You have M variants of each of the M meaning you have two input, three input, four input, three, you have different type of drives of a particular cell. So, the total number of cells N would be F into M into K. This is a very gross simplification of the number here, but N is usually 800 to 253 that is there are at least 200 cells in a particular natural identity. Let us take an example an AND gate. So, there let us say there are two input AND gate. So, it will be the AND gate and it will be something like this A and D2 which tells us that the function is AND the inputs are two. If you have three input it will be AND 3, the fourth input it will be AND 4. Now, there will be at least there should be at least two or three variants of AND gates which represent different drive strength. Now drive strength is represented by the suffix. So, there will be a cell called AND 2 x 1 which means drive of 1 AND 2 x 2 means drive of 2 double the current drive of AND 2 x 1 AND 2 x 4 that means the drive is now closed as represented in this figure. So, you have a NAND gate of 1 x drive and if you try to use this to drive to try to use this to drive these 4 inverters there then you will find that the transmission here this transmission here is not so good, but if you use a 4 x in as depicted in right side suffix if you try to use a 4 x in with a higher drive it is easily drive 4 inverters and the transmission is very good compared to this case. So, this is the use of the high drive. So, we saw the logic states and at the logic states 0 is represented is called a low logic level can be represented by L or 0, a high logic level it can be represented by H 1. There is one more logic level called Z which means high impedance state it is a state where input is different from the output and output is not driven by these typically a state of a high state inverter and it is not active. The transitions can be represented by symbols like LH low to high transmission, HL high to low transmission or X. Now X is X as a logic level means you do not know what is there only on the known it can be either high it can be low, but at some point of time you do not know what is there. This is very useful in synthesis I will go on to give you some examples in the next lecture about how it could be. It is very many common very much common in the position in the state X. Now let us look at some of the parameters DC and so we will talk about DC parameters for related to digital cells. So, first very important parameter is the voltage transfer characteristic and we saw I saw for an inverter. So, voltage transfer characteristic could be plots the V out output voltage again the input voltage is the V D3 of an inverter. It tells us what is the function dependent input and output voltage the output high voltage nominal the output high voltage nominal value is represented by V OH and it is typically V DD because we want complete swing. So, the high logic level voltage is represented by V DD. Output low level voltage nominal is again it could be mostly V 0 or V taken it is represented by V O and there is something called switching power point voltage which is necessary less than half or where V out is equal to V DD. So, for a perfectly larger inverter V out is equal to V in the pattern at V DD by 2 at this space. So, it is called switching power voltage. There is there is something called output high level minimum voltage. So, V OH min now the 2 things output high level minimum voltage and output low level maximum voltage V O L max and V OH min are the points on the curve where the slope is minus 1. So, the slope is minus 1 at this point and at this point. So, we take these 2 points we take the take the value on the bi-axis. So, V OH min is the output. So, the the concept is that what is the output value what is the voltage value on the output and the minimum value of voltage on the output when the output is high. The nominal value of voltage when the output is high is V DD as we discussed in the previous slide V OH min represents the minimum value of the voltage and output is low. Similarly V O L max it gives us the maximum value of voltage when output is low. The minimum value the nominal value of voltage when the output is low is V SS this is the maximum value. Again we have VIH min and VI L max input minimum high voltage and input minimum the maximum low voltage. So, VIH min is the highest input voltage at slope minus 1. So, again at slope minus 1. So, we take V O V O max and V O L max and what is the V in value is the VIH min. Again we take the V OH min and what is the VIL value it will be VI L max. So, I will I will it will be clear how these values are used in the next slide. Now, all of these values V OH min, V O L max, V OH min, V L max are used to determine the noise margin of the noise margin on the higher side that is when the noise is high. It is simply V OH min minus VIH min that is it tells us that this is the level of disturbance the cell can tolerate and not it will not affect the functionality of the cell. Now, let us say one inverter is driving other inverter and the output value of first inverter let us say there is a case like this where you have one inverter let us say one inverter is driving another inverter and the value at this point at the output of the first inverter has some noise on it. Now, the NMH value that is V OH min minus VIH min that is the noise margin on the higher side will determine how much noise can this this inverter call it. So, now, let us say that the the in the maximum let us say that output is of this inverter is high that input is low and there is a noise on it which causes the input to be slightly greater than 0. Now, if the if this disturbance is within the tolerance limit within the noise margin limit the output of this inverter will not show any difference it will simply ignore the noise, but if the noise is above that threshold it will cause disturbance at the output output will go from high to low for some amount of time which is determined by the amount of noise. So, these two things here NMH and NMH actually determine the those threshold those noise margin. So, NMH is the maximum input noise voltage which does not change the output state when its value is subtracted from the input high level voltage. This is the maximum input noise voltage which does not affect the output state when its value is subtracted from the input high level voltage. So, let us say the input high level voltage is not VDD it is VDD minus X. So, now, this X the maximum value of this X is nothing, but NMH if the disturbance goes beyond this maximum value it will affect if the disturbance remains within this value the disturbance will be ignored. Similarly, NMH the noise margin on the low side is the maximum input noise voltage this does not change the output state when added to the input level. So, on the higher side any noise which causes the voltage to drop down from VDD is a noise it may might cause disturbance on the lower side any noise which causes the VSS that is 0 value to be increased and it does not does not increase beyond NMH VFR. All these values 0 H max, VIH min, VIH max and so on noise margin inside they do not matter for synthesis. Why because synthesis is not the process does not take into account noise anywhere. Noise is purely an effect that comes after physical design of them, after place and out is done. We see that noise is part of static timing analysis now, now a days in the external vacuum technology. In fact, this is still about 90 nanometer if I remember correctly we did not do any noise analysis. We assumed the VDD levels of between high 1, 2, 3, 4, 5, and the noise was not a bit concerned. So, the noise analysis was not part of our implementation but now it is a very important part of a system because the technology has been changing in fact, so many gates in a certain area. So, there is the noise is a real clear danger now, but still as far as synthesis is concerned we do not need to worry about these values. They will they will come and when we start the subject of static timing analysis. So, it is only an effect after place and out is done not before. So, synthesis does not take into account any noise. Static leakage still look at another parameter static leakage current when the output is at high state you could say when the output is a high or low high. So, any gate any gate will just because of there is the whenever the transfer is off it does not necessarily mean the current is 0. There is some leakage current as we technology shrinking this leakage current is becoming more and more significant. This is why even when your most of the devices are off they still consume some power. So, but again this this value leakage is not losing significant. Then leakage power consumption at the output since the current is I leakage I leak the power is VDD into I leak. So, the power consuming the output is off. The leakage is when I say that it is not part of synthesis there is there is in fact, one place where leakage comes into play is there are different kind of cells available in the library usually. So, let us say a library typically a deep sub micro library from let us say 65 only longer typically have two or three flavors of cells. One of the these flavors are based on the special voltage of the device. So, you could have a high VT cell a low VT cell and a standard VT cell. So, we go back to the standard cell selection content selection. Apart from these three F M M K you have one more factor which is the special voltage of the cell. So, a high a cell which has a high special voltage will have less leakage current go back to unit 1 and 2 and then see this slide will find the output via VT. So, high VT means low leakage current a standard VT device means leakage current will be slightly higher than high VT and there are low VT cut devices which have highest leakage current, but again the low VT is the faster. So, the cell with a lower special voltage is faster, but more leakier. So, we discussed right the power and speed they are also they also fight with each other. So, the speedier the cell faster the cell the more leakage. So, you have one more factor here that you should have cells with different function with different number of inputs, different drive strength and nowadays we also have cells with different different VTs. So, for example, we took an example of an an2 gate. So, there will be an an2 X1 HVT an2 X1 SVT and 2 X1 LVT. So, I am not sure if the battery you are using has multi VT cells these are called multi VT cells and now they are. So, they are used in synthesis you could choose to do. So, what we do for example is we choose to do synthesis only with high VT cut. So, we ignore a standard VT and OVT to make sure as our design is to start with it has least power, least leakage power. So, it is not it it can be used in synthesis, but it is not necessary. So, if your library has multi VT cells then you could choose to use that in synthesis. Then again you have the we talked about leakage power connection, leakage is also we need to. This is just different some type over here this these are just some different values whenever output is low or output is high usually we take average of both those. Now, let us look at AC parameters. So, just summarizing the DC parameters. So, typically at synthesis stage you will not see any of these values VTC VTC is not VTC is used to derive the noise margins, but it is not part of the library and typically not used in synthesis noise data. So, out of these DC parameters what synthesis is used is if you want to enable monthly VT synthesis that is you want to choose what VT or you want to reduce the power of the machine then the design compiler will try and select between different VT devices. For faster for critical parts which are which you need to be fast for high frequency part high performance part it will typically use low VT cells for all other that we use typically high VT cells. So, that is the balance of power. Now, let us look at AC parameters. These are very very important parameters. These are the typically the parameters you would actually see inside the library file and which you would use use a lot. So, first is the right transmission time the unit is nanoseconds symbol is TR. Now, right transmission time is the time it takes for a signal to rise from 0 to 1 from or from 10 percent of VDD to 90 percent of VDD. So, we say that TR is the time it takes the signal to go from 0.1 VDD to 0.9 VDD. Now, the 0.1 and 0.9 is we call this 10 90 it could also be you could also have a 20 18 or 30 20 is just a convention it is fixed for a particular unit fixed for a particular library. So, for a particular technology definition the time it takes for a driving pin to make a function from K VDD to 1 minus K VDD. Usually K 0.1 as I told K is 0.1 we call it 10 19, K is 0.2 it is 28 and so on. But the choice whether it is 20, 80 or 10 19 should be made right at the starting and it should be common to all the time. Otherwise the analysis the time in calculation the delay calculation could be wrong. It is a very very important parameter we will see how do we use this. Again corresponding there is a full transition time parameter. So, time it takes for a driving pin to make a transition from 1 minus K VDD to K VDD propagation delay. Now, transition times are limited to one signal. The propagation delay by definition is the delay is a time taken for input to go to reach output to affect the output. For example, in a buffer the input drive is the output drive is now we need some reference points on these voltage signals to calculate the time. So, the reference point typically is 0.5 VDD. So, the time it takes for the output to reach 0.5 VDD from the input reaching 0.5 VDD is called the TP or propagation delay high because output is going low. CPL would be when output is going low. So, this is the time difference between input signal crossing a 0.5 VDD and correspondingly the output signal crossing 0.5 VDD when the output signal is changing from low to high. Propagation delay from high to low is similar therefore writing difference. So, whenever the output signal is going to low and process 0.5 VDD from that we subtract the time at which input crosses 0.5 VDD. Now, please note it is not necessarily that input and output will function on the same time. For an inverter the input will rise, but the output will fall. So, that the time a calculation is done that done in such a manner that whenever input rises to 0.5 VDD from that point to the point a output falls to 0.5 VDD. So, the 0.5 VDD is the middle VDD point. Again average supply current, this is the power supply current, average value for particular time V, usually supply peak current these two 5 and 6 are not used to process it. There is dynamic power dissipation, this is the average power consumed from the power supply. So, is nothing, but IDD average that is the average current drawn by the device into VDD. I will not go into 8 it is not used 8, 9 you could read it yourself 8, 9 is not that useful for for switching. Again you have a switching power power, you have a switching rise power as well the energy dissipation. So, instead of reading fault power let us call it switching power. Switching power is the energy dissipated on a on a transmission. So, you have a so every gate will have some inherent capacitance at the output that we saw. For example, 9 gate will have 2 input 9 gate corresponding may have a 4 C as a 4 C capacitance where C represents the capacitance of each capacitor. So, it is every gate has some input inherent output capacitance plus we add the load capacitance whatever the interconnect is describing whatever plus the input capacitance of the gates is describing. Any transmission on an output will cause some power dissipation on those circumstances. So, this switching power resistance that I will have one lecture dedicated to power. So, we will we will see a lot of switching power there we will discuss in detail about of different kind of power what is important for us what is significant what is more. And again there are so till now we saw that these these these things rise transmission times, fall transmission time propagation delay these are kind of delays that is these are the property of signal of output let us say output is transmission from and it takes a certain amount of time. So, let us say there is an inverter the input goes high output goes low. Now, there are two important things here one is that delay between input changing and output changing which is presented by propagation delay. Second is the transition time of the output how good the wave form of output is. For example, if we go back and see this case now in this case the output is taking is taking lot of time going from 0 to 1. In this case the output is taking less time compared to this case. So, the so rise the transition time and the propagation delay they both are delays transition is nothing, but a thought of a delay. Since the wave form the more time it will take for output to reach to we delay or or delay. Now, here we start looking at not the delay part, but the constraint part. That means, constraint is the minimum there is some limitation on signal changing if the signals do not change within that time the functionality is not there. So, one of them is clock pulse width it could be in the higher side of the lower side it is typically used for clocks and latches and memory. So, if the pulse width let us say pulse width high is less than a particular value then this plus clock or the latch will not function correctly. The time interval doing with the clock signal is high or low so that it ensures proper operation of a plus clock or a latch. Now, clock pulse width is not a major issue for plus clock. The usual the CMOS clocks are very very fast we can switch very very quickly and they do not have a very strict pulse width requirement. This clock pulse width requirement is very very critical for memory for full custom memory. Now, memories are usually very high density circuits and to write or read into memory location takes a bit of time and therefore, they have stringent requirement on the clock pulse width. Setup time set up time is a is a constraint for sequential elements. Setup time is a time minimum time in which the input data to a sequential element must be stable before the activated the clock. So, this is the minimum amount of time before which let us say the clock arrives at some time at time t. Now, the minimum amount of time such that the data data should change before the clock arriving at t the restriction this restriction this minimum amount of time needed is called the set up time requirement it is a constraint it is not a delay please note it is not a delay it is just a constraint. So, if the signal changes let us say the set up time is T s u. So, if the clock at the rise of t the data should arrive latest by T minus T s u if it does not then the flip clock operation is not going. Similarly, we have hold time now this is a time. So, data should change only after T h again the minimum amount of time. So, if you notice that take a clock a clock signal now before and after there are two limits. So, that so the time before this is the before this is the before it is a set up time and the time after it is the hold time this is the hold time this is set up and this is hold. So, in fact, if you add up T s u and T h the set up time requirement and a T h time requirement it tells you that whenever clock changes for a flip clock there is a window before the clock and after the clock the before window is called set up time window after window is called the hold time window the signal the data signal should not change in this window. If it changes the operation of that flip clock or latch is not guaranteed set up time and hold time you will see a lot of equations on this using the set up time and hold time, but everything starts from this basic difference again. So, these are constraints clock impulse set up hold there are constraints they are not delayed now we talk about delays of sequential elements. Now in combination element for an inverter for example input the way output means that the delay is the definition oftime taken by signal from going from A to Z for flip for sequential element it is the clock that affects that transition that is the clock change data let us say for flip clock that it does not output remains stable with respect to of the data state if the clock is off only when there is a proper trigger in clock the data is affected on the key. So, the timing the delay is defined from clock. So, so the clock to output time only for flip clock or latch latch two types of time the combination also and we are talking about the frequency time. So, right so the clock to output time is PCLJQ is the amount of time that takes the output signal to change after clock activated the clock. So, after clock active edge comes whenever output changes this difference is called clock to output. Now there are two is very specific time constraints for flip clock or latches with asynchronous set of input. Now asynchronous set of reset is exactly same as data because data signal data pin is also synchronous asynchronous set and reset is exactly same as data. So, flip clock is a synchronous set of reset for example, a flip clock has the data pin and a synchronous set. Synchronous reset will have its own set of and whole time constraints very similar to data, but in the case of asynchronous the situation becomes different. Now the functionality for a clock such that whenever asynchronous reset becomes active data becomes 0 or whenever asynchronous set becomes active data becomes 1. In respect of what the clock is in respect of what the data pin is in respect of the state or any other pin an asynchronous reset going active will cause the output to be 0 stated or this is there will be some delay, but but when the important thing is when the reset is de-asserted. So, when the reset is de-asserted the next clock edge let us go to next sentence. The next clock edge that comes will produce will affect the output because the reset is de-asserted. Now there is a minimum time between reset getting de-asserted and the next active clock edge that should be met. This timing constraint is for recovery. So, this minimum time in which set of reset must be held stable after being de-asserted before next active edge is the clock edge. So, after these edges get de-asserted the minimum amount of time after which the active edge clock can come is the recovery time. So, recovery time if you notice is just like setup it is that the reset is de-asserted first then the clock is arrived. It is very similar to setup data gets setup first then the clock is arrived. Similarly, responding to hold another removal again the de-assisting is important for timing constraint assertion is not. The minimum amount of time in which the asynchronous set of reset when to a flip clock or a latch must remain enabled after the active edge of the clock is arrived. So, after the active edge is acquired the minimum amount of time during which this should remain de-asserted is called de-remover it is just like hold. So, setup is equivalent to recovery removal is equivalent to hold. So, a flip clock so, accommodation circuit is pretty simple a hand gate is pretty simple it just has let us say 2 input and gate A B output is there this there only 2 or 2 parameters there of importance and that is timing parameter the delay from A to Z and the delay from B to Z that is it. But a flip clock on the other hand has the propagation delay from clock to Q is setup in hold time for D if the reset is asynchronous recovery and removal for reset. So, it has somewhat more it has. So, apart from combination apart from propagation delay the difference between combinational sequence from timing clock to Q is that sequential elements have timing constraints it has timing checks built into it. So, we have to make sure that our design after being laid out properly after the basic analysis time it meets these timing constraints for all the sequential elements and this is what static timing analysis is all about the big subject again that is some further. Now, there are apart from the regular propagation delays output going high output going good there are some some typical propagation delays for tri-state and further output going from high to Z from low to Z from Z to high from Z to low this is very typical to for tri-state this is not used for any other type of circuit because only a tri-state inverter a tri-state buffer has a Z state. So, it is very similar to regular propagation time. Now, apart from the timing constraints the difference of the propagation delay we also have something called the inherent circuit design parameter for example, there is input pin capacitor pin. So, it is the load and there is a type of it should be defined throughout the input pin capacitor pin. The input pin capacitor pin should be for example, a non gate or let us say an inverter you are driving an inverter voltage V capacitor pin software inverter inverter input pin as you know that in the CMOS circuits the input is usually connected to gate or that gate has some capacitor pins so that this is the capacitor pin problem. Now, input pin capacitor pin is the property of the design is the property of the design similarly there is output pin capacitor pin these are the properties like proper propagation delay. Then there is also a constraint that is something called maximum capacitor pin this is the maximum capacitor pins you define it is defined as the maximum capacitor pin a gate output pin problem why not why this is very limited number we will consider why maximum capacitor pin problem it is very very important. So, now let us see let us talk about operating conditions. Now, let us see levels of operating condition process temperature and operating ok here it is a frequency is given let us the process is not given there is one more thing called frequency ok let us talk about ok this process is not mentioned here, but let me mention the process also. So, the process can be we have also discussed this is earlier process can be slow or fast or usually process is represented by two alphabet code the first represents the state of the M1s the second is the state is about to be known. So, a slow process a slow slow process for example, S S S is that P MOS is also slow and M MOS is also slow. The process is the term actually represents the variation that happens in M1. H it is manufactured there are number of chips on a particular basis and all the chips do not function at similar speeds, because even a slight unique in manufacturing parameters even a slight difference going from secondary to secondary will cause the T MOS or the the the functions to be fast or slow. So, one thing is process second thing is power supply that is. So, typically you create your chip you will create a design to get certain VVV for example, it is what I am going to do. But the power supply it might happen that power supply gives a voltage which is there will be a voltage drop from the power supply. The power supply will go through certain by before reaching your design or before reaching the cell in your design it goes through a number of meshes it goes through pads it goes through the the connecting wires. So, there will be a power supply drop there will be a J at all. So, typically the voltage that you get at your design VDD is slightly lower than the the VDD applied outside. There is a operating temperature now this V chip is being operated in hot environment the temperature will be more for a particular chip if it is sitting in a cold area then it will be lower. So, this will also affect the speed of operation. And in operating frequency operating frequency the design is that again. Now the standards and labeling usually most of the cases called for the seek of description of the poles. Let us say that the standard cell has now a cell a CMOS converter for example, if it is manufactured in slow process would be slower compared to the past process. And if it gets a power supply which is lower than VDD it will again goes lower. Now let us say it gets an operating temperature of 125 it will still becomes lower it was writing temperature means more delay. So, what we define is we define corners or operating conditions and we try to capture the full limit of variation. That means, we have libraries the standard cell has to be a 1.2 volt process for the 1.2 volt technology for example, let us say let us choose 19 nanometer and write it let us say that 19 nanometer design will work for 1.2 volts we are designing a tip for 1.2 volts. Now we need to make sure that the chip works below 1.2 volts because most of the person designing will not be getting 1.2 volts because it is a 5 higher term. So, we define that ok the chip should be in center plus it should work for a slow process also it should work at higher temperatures. So, now we have three things P V and D we choose P to be slow we choose P to be slow we choose voltage to be minus 10 percent to 1.2 minus 10 percent of 1.2 is 0.7 or whatever we can choose anything lower than 10 percent also, but typically it is 10 percent. So, 1.2 volt the 10 percent means 0.2 it is a crack 0.2 from 1.2 to 1.2 or it is from 1.2 to 1.2 you could choose also lower than that it depends on the type of the type of type of market we are targeting. So, usually it is minus 10 percent. So, we choose a lower voltage we choose a slow process we choose a higher position and now we get one standard cell library on that. So, for example, for this this particular application we have one standard cell library which is 1.0 volts 1.28 volts at 125 degree temperature and at slow process. On the other hand we choose a standard cell library now there will be a standard cell library which will pass for all the people. It will be at minus 40 degree it will be at a voltage 10 percent higher than V dd 1.2 plus 10 percent of 1.2 becomes 1.32 and the the process it chooses is fast. So, both CMOS and CMOS will be fast. We choose two end of the spectrums and verify that our design works for all values in between. Now please note synthesizers will not do this. A tool like prime time which is for static time analysis makes sure the process of static time analysis makes sure that your design works on all operating conditions which are defined by the process by your application. Now how do we take care of this in synthesis? So, in synthesis we always choose a library which is on the slower side because synthesis is the output of synthesis is a net list which is optimized for speed. So, we need to make sure that our design even when the NMOS CMOS are slow even when the voltage is not V dd it is 10 percent less than V d even when the temperature is high at 25 degree our design should meet the time requirement. Our design for example, if I operate in V 20 300 our design should reach 300 at slow slow lower voltage and higher voltage. So, for synthesis so, when you go on and see your library you will see that every standard for library there will be multiple corners the file. So, there will be let us say you have 19 nanometer generic library, there will be 19 nanometer generic library at slow slow 125 3 and 100 degree load, there will be a library 5 at pass pass minus 40 c and 1.32 load, there will be a typical library at 1.2 load 25 c and typical NMOS CMOS out of all the flavors available to you after all the operating conditions available to you choose whatever is the slowest and do synthesis on that. The summary is that synthesis is always done at the slowest level SS low voltage high temperature this is the key. Rest all operating conditions are used in time management we will see a lot more of that in unit 4 or unit 5. Now, the library data that is the standard cell usually comes from some sort of internet can be external it could be internal for example, the carburetion lab TSMC itself gives standard cell libraries which are qualified on its own arbitration process. So, we put that as an external layer many companies have internet teams that develop standard cell or a particular company. Now, what is delivery mode what do you get? So, we see here that we will see that to complete design of library is a set of files which are delivered to customer or user user will be us in this case at next level. Set of this set of data is called deliverable there are two types of deliverables. Views and if views are fine these are needed by design flow of processes in this library. So, the views are actually the files which are used by the EDA tools to do the job. Second is documentation reports obviously, we would need some kind of documentation to we will need the data sheets to make intelligent noise right this is not directly used by the human deliverable format. The views here might not be view deliverable by humans might be by electronic, written by the individual. This figure here tells the different types of deliverables which are there. So, a cell library comprises of cell logic models containing cell functionality. This area timing power this is used for this is the one which is used for this. So, this this thing here is very important this is called usually a dot lift dot l i d. So, the l i d it is short form for liberty, liberty is a format and this data is represented we will detail into that. So, it contains what does the liberty dot lift contains? It contains logic model it contains for each of these standard cell if you tell what the functionality is it will contain the pin capacitors for all the pins it will contain the time information what is the delay of way to that for example, it will for sequential cell it will contain the suspense also it will contain the area of the cell. So, it will contain all the information that is needed by this in also design compiler or the synthesis tool. Second level comes cell physical model. Now please note that design compiler the synthesis tool is actually not worried about the the physical model of the cell it just needs to know the area it is not placing the cell it is just it just needs area to optimize it does not need any other area information it does not need to coordinate it does not need to be in the location whatever is needed by the physical design tool. So, this this thing here the physical model is used by the physical design tool used by the physical design tool again there will be now there will be layout of the cell. So, cell layout cell schematic how we see the answers This is again used by the back end tool used to the layout tools will use the layout on build different layer different polygons from this come to the GDS it goes to the boundary for monoclocking. Lastly you need to have a bedrock models and prime cell level models size model this is used to simulate the design at different level. So, bedrock model is used for function combination to verify that the design needs the function representation many people also do size on some part of an idea to make sure that the electrical parameters are good they form the looking fine. Usually size is done on a smaller level it will not do size at a cultured level because it is very very time consuming. So, the size is usually done for mostly it is done for very specific programming for analog it is definitely size is available. So, a standard cell will have a total model, a bedrock model, a layout model and an abstract model which tells size and location there there are the used. So, in standard cell set the system coding that the system will be able to use in logic synthesis as I mentioned this is part of this the first part of this. Logic synthesis use this once we have done the logic synthesis timing which is timing if timing is okay we will put the physical system based on that based on that we will use this physical model that is the layout data it might also use you could also use size it. Now, again we verify if the timing is okay yes or the line is finished the two different levels of timing check here 1 and 2. Now, 1 is called pre layout since obviously it is before physical synthesis 2 is called post layout there are lot of differences between a pre layout timing check and a post layout timing check we will see a lot more detail in unit 5 about the pre layout and post layout timing check, but the thing to note here is that synthesis is a pre layout process the output of synthesis is an at least between both the layout. So, we concentrate in this unit we concentrate here timing check at pre layout level and the process of synthesis we concentrate on this unit. So, if we talk about the levels the logic libraries have timing power let us see the. Now, the same logic model level it contains I am talking about dot layer here it contains cell name, pins, pin cell, pin direction, functionality, timing power or any other parameter needed by the ED2 for example, capacitor systems, but the process of generating the cell logic model is called characterization. So, characterization means that we will see where I will mention the characterization will come later also. It means that for a let us say I am designing an AND gate inputs AB output Z. Now, I need to find out what is the delay from way to the how do I do that? I apply some input waveform at A I observe the value at Z let us say keeping B constant let us say keep B at 1 for an AND gate. So, anything on A will be reflected on that, but how do I choose the transgenetic what value do I choose? So, this process is called characterization where a range of values is applied on you and a range of waveforms will be observed at Z and then we will calculate the transition at Z we will calculate the delay at Z and so on. And we will put all this data in the cell logic model in the liberty part in the quadrature. So, the characterization goal is that it compute cell parameter that is delay output current or you could say that you know output waveform is a current waveform or output waveform depending on the input variables which is output load input slew means transmission which slew means transmission. So, so typically the characterization is performed for various combination of operating condition. Obviously, you have one liberty time each for different operating condition. So, we will first fix process we will fix voltage V 6 temperature V 6 PVD then we will vary two things. For example, we will vary input slew input transition and output load and now for let us say we have 5 values of input slew and 5 values of output load. So, for a particular PVD we will have 5 plus 25 output waveforms for each corner for each combination for each cell and for each combination of input and output. So, this produces a different set of graphs different set of vector waveforms at different processes at different inputs slew at different output gap. So, you see X here is output gap Y here is input slew and now we put all this data we we we put all this data we choose this number of points we calculate the value we put all this data in the liberty time we thought that how do we do what does liberty time look like we will do. But just try and appreciate here just try and notice here is that how much data is generated. For a central inverter let us say there are only 2 3 operating conditions for 3 operating conditions where simple inverter from input to output from A to Z choose 5 and 5 5.1 2 2 5 and 4 output gap is a function you have 25 values of delay and transition expand this. Now, there are 100s of cells there. So, there will be 1000s millions of timing loss in the liberty time. So, this characterization is not a small drop that is why you have you have dedicated tools doing that for for all the all these 100 cells and this characterization is done at 5th cell makes sense you need maximum accuracy. One more view is called the SRAM view you have the SRAM view of the cell. So, SRAM view as the name suggests it contains the minimum data it is needed for based on the model. So, let us say for example, you have a layout view of a cell while I leave this in the exercise to find out what cell it is. Now, for this what is needed typically for layout for using this you do not need the external information. So, only external the pins where the metal layers that talk to the external world are are kept in less all in this corner. You have VDD, GND which are the power pins or if you they can have the power pins and since this test when it is used A and B are connected by it is connected. We do not need to know what happens in GND. So, these are preserved A, B and B are preserved let us call it this for layout. But when so, this is abstract view it is used for this is used for layout or for based on the nothing, but when the data goes to boundary you replace this abstract view by layout view. Why is this done? The lesser the information a view has usually the faster would be the EDA to 14. If the EDA tool is given hundreds of parameters and it needs less printing I mean why why give it hundreds give it less so, that the view is faster in reading the files in interpreting the data. Now, there is something for naming convention it is a global naming convention when you go to the industry you will found out everybody is using these naming convention to make the job easier. The dot link is the short form for liberty with the technology library source file and it says source file. Key limit is physical library source file. DB is nothing, but a lib which is compiled it is a binary format it is not readable by a it is compiled by a synopsis tool and synopsis tool will be. So, DB wherever you see DB it will be the combined binary format of the corresponding text format. . Now, we will see this in lot more detail we will see an example of this. So, as I mentioned that L A business you will need to have a format it is converted to DB as you also should as you also should you will need to be. So, before a dot link can be used it must be combined. So, you can use in fact you can use same to the end of by the it is a very simple command you read tell it you read tell it the library file and you write tell it. So, the input is s p playdance dot link output is s p playdance dot link. So, it is a very simple process. Most of the times when you go to the library library store it will see that every library file has a link on a DB already there. If not then you can use this in commands to write the DB or not a picture. Now, let us look at example data sheet of a particular type of an AND gate. This is an AND gate usually a data sheet will have a logic symbol which tells you what that gate does. It gives you the trip table where you have values of inputs and what is the value function of a particular game. It has a naming convention. So, this is an AND. So, it tells us that there is a AND to send and there is a high driver cell also AND to be a two input AND gate. It also gives you the number of gates and IO 2 special IO 0. It does not give you the form of the key how many gates it uses. So, input and AND gate will typically use the AND plus inverter in the school gate. It gives the design parameters. It will tell what is the capital set input. It will tell how much output load can the cell drive. So, for example, AND to AND drive 25 units of load AND to be supposedly high drive AND it also tells you what are the relationships from A B to Z for both of these cells in nanosecond. It gives you the resistance also time it takes. So, there are three four things here. In principle drive, drive resistance, in principle call, call resistance. So, we will see how these values are represented in the file, how are they used. This is a typical data sheet for a particular class. Let us look at one way or another. Very simple. I am assuming most of you are familiar from now. So, an AND to gate will have module definitions, inputs, outputs. The output is declared as register. Whenever any of the input changes the output gets A and B. This is the there is one more way of doing this. You could replace always by the hand statement, find S is equal to A and B in that case there is no way to define the S will be not a register, but I will. So, you could write, you could write the definition in the number of things, number of definitions. Now, let us look into detail into a library, into a plotless file, which is read by design compiler possible. So, the library definition file any example.lib is broken into two sections. One is the header which defines the most of the common values for a lot of parameters and then an individual cell section. A cell's definition will define the attributes about the cell. So, that is going to be a function of the time. So, let us start looking. So, this is it a library header. The library always starts with a library syntax, which is the name of the library. Technology tells us what type of delay model is the library. The delay model tells us what type of delay model we are talking about. I will go deeper to this again in the following slide. Then these values here, these default values here, define the defaults for input print capacitance, in output print capacitance, in output print, in output print output and output print capacitance. It defines the output print capacitance. Now, these are default values. That means, if any particular cell for example, there is I define a cell, but I do not define the input cap. In that case, if the input cap of the cell is not defined, it will take the default time. So, it is a good practice to have these, since if you miss any particular attribute, then that will not be given, it is not zeroed in. So, if you miss out the input cap definition for an inverter, it will take some value which will define the default. Then it defines the time the units, timing unit, resistance unit, voltage unit, current unit, capacitor unit. So, the units are defined here. Then the nominal operating condition will be found. So, nominal process 1, nominal temperature 25, nominal voltage 5. Obviously, voltage will have the unit of voltage temperature of nominal temperature. And the process in here tells us that nominal process 1, and I will come to this. Now, further in the header, we can define. So, now, we can also define different operating conditions. We say that, okay, we define one's worst-case condition that you see. The process is now 1.5, temperature is increased, 670, voltage is decreased. So, the worst-case corner, as we said, voltage is decreasing, temperature is increasing. The process factor tells us that, since the nominal process factor was 1, and the worst-case process factor is 1.5, it tells us that all the delay in this pattern, if the delay was 1 phenomenon, and you choose the worst-case corner, this particular operating condition that we see here, all the delays will get multiplied by 1 percent. So, all the test will get 50 percent load for the worst-case corner. You could also choose something called the operating condition dc main with the worst-case, call it about 3 times right now, I will come to this later also. Again for worst-case c, the temperature goes lower, minus 40, the voltage goes higher, the process is 0.6. So, the faster process factor tells us that, since all the NMOS and TMOS are becoming faster, all the delay, delay values in this particular library for a worst-case corner, for a fast corner, will be multiplied by 0.6 or all the delay will be 40 percent, all the test will be 40 percent faster. This particular case was used, this particular type of writing the operating condition and using the operating condition was used to be as that, it is not in use now. Now, what happens, now this is a very simple model that is, what we are doing here is, we are, we have only one library final, which has data for normal. Now, what a tool does is that, if you choose, if you say tell the tool ok, I am choosing, I am choosing the utility cost, which is the worst-case. What a tool will do, it will use some factor to slow to delay the, to make the delay slower. If you choose the faster corner, it will make the delay faster using the same process factor. But, this is a very simplistic model, which does not serve present-day nanomotive design. Now, in present-day in the industry, what you have, mostly you do not have this, you do not have this, instead you have one file for operating condition. That is, there will be one file for worst-case corner, one file for best-case corner and there is not a single worst-case corner or best-case corner, the things are too much complex now. So, let us say for example, you have to, the two worst-case corner and three best-case corner. So, you will have two worst-case corner files, three best-case corner files and if you compare the delays, in each file you will have separate delays. And now, let us say you are using and now you have to use that, read that for the delay. So, if I want to do this for example, I will only read the worst-case file, the worst-case file. And if I am doing timing analysis, I have to make sure that all, if I am doing a post-day of timing analysis after processing out the exam, I have to make sure that my design works on all the corners design. That is, I will perform that that process five times on two worst-case corners and on three best-case corners. The things can become very clear in unit 5. But for now, you wait, I mean as an assignment, you go back, check your library file which you have, probably you will have a 99-meter generated file function also. Check that you have one library file per corner. Now, let us look at this course, the header, what we looked at. Now, let us look at the, the cell definition. Now, let us look at an An2A. So, this is the text, the starting of the cell. Area is defined here. So, please note, this is just the area number which is written there. We are not writing what is x and what is y. Usually the layout is rectangular, but the synthesis tool, since it is not doing placement, it is not actually placing the cell, it does not need x and y. It needs simply the area. We define the pins A1, B1, O. We tell the direction, A1 is input, B1 is input, O is output. We write what is the input capacitance and we also tell what is the function. So, only output in the last function obviously, the function tells us that it is A1 into B1. So, it is an AND gate. Now, design compiler when it reads this library, it knows that the area of the AND gate is there. It has these inputs, this output and it knows it is an AND gate by this. It does not know it is an AND gate by the name. It knows that it is an AND gate by this function. The name can be anything. Timing has been removed to simplify this. We will see the timing in the coming slides. We will see an AND gate. 9 2 underscore 4 probably means that the drive is 4. It is a high drive AND gate. The area again is 359.1. There are two inputs. It is a two input AND gate. So, it is a 2 underscore 4 capacitance again function. So, function is A1 into B1 and complement is used a single code is used for inverting. Now, please note there is no output capacitance here. There is no output capacitance here. Does it mean the output capacitance is 0? No. Look for the values in the header. So, if the output capacitance for example, is missing the tool will take the output capping cap from here and default value is also 0. So, obviously, it is not. So, if the job of the standard time designers or some people who are doing standard time designations to make sure that there are no real values with the the values are not visible they should not be real. Let us look at a flip flop a sequential set area is something. Let us look at pins. There is a data pin input, there is a block pin input, there is a reset pin input. Q is the output. Now, how do we tell the function? The function here is defined to be i q. This i q is. So, this is the this construct here. We construct this construct here f f is specifically for sequential cells recognized by the tools. So, we tell that f f is always i q comma i q this is the fixed impact. So, we tell that that the next state is data. So, we tell the tool that it is a sequential cell f f the output is i q which is mapped to q i q is mapped to q. The next state on i q is data 1 that is whenever there is a trigger on clock. So, the it is clock done clock 2 whenever clock comes or clock 2 positive edge clock it is a ok. So, there is a negative there is a single code here. So, it becomes a negative edge. So, whenever negative edge comes clock 2 data 1 goes to i q and i q again is mapped to q. So, you tell the tool that this is the flip flop with data pin being data 1 output 1 being q. Clear is r s t 3 it is a it is an asynchronous clear it tells that the inversion on reset it is again this is a single code here. So, it is whenever the r s t 3 goes low q becomes q q is it becomes 0. Now, before before looking at the timing section let us talk about synopsis timing model. Now, representing the pin telling the tool writing the pin direction calculating the output cap input cap or telling the function they are all simple though. Why because there is only one single value the input cap will be a single value the output cap will be a single value. But, what about timing? Timing is not a single value timing depends on how much load are you driving how much load how much transmission you are getting and some other parameters ok. So, representing timing for representing timing you need some mathematical model to calculate timing and to write the timing in the top 5. So, there are two there are I have mentioned three models here linear delay model. So, if you go back to the header here. So, this delay model string here defines what is the model. So, a generic CMOS tells us that it is a linear delay model. If you see something like table look up it means it is a non-linear delay model. If you see piecewise CMOS it is piecewise linear delay model. Now, the first one linear delay model is a very basic model simple model and that is why it is not used for present data problem. But, we will go over this we will leave some foundation there. So, this was non-linear delay model short form we call it NNTN was the most famous choice of models in a couple of years back not in couple three or four years back it was the most popular choice of model. In fact, your synopsis NITM it is in the library will have an ending. So, we look at this in detail we will for presently we do piecewise I have it in serious use, but now in present technologies all these three are not in use. Although NNTM is still used by some other tools not by some of the different systems it might be used for some old tools. This remains most popular, but now it is being replaced by something called CPS or some sort model, but I will not go into this for this purpose for the purpose of this course studying NNTM should be enough. Now, let us look at linear delay model we again go back to the input and then now we see few values here we see intrinsic lines we see intrinsic power this tells us some this tells us that there is a rise delay on Z. So, timing is represented by a timing construct here. So, first thing to note here is related to both the end we have mentioned here that means, this timing construct is valid for the applicable for both delays A to Z and B to Z. There is some delay when Z rises in that intrinsic power means that there is some delay when Z falls. Now, let us see how these values are used there is a rise resistance also there is a power resistance. These two will also determine and let us see how it will be. So, in a linear delay model it involves calculating the any to the process of delay analysis or a delay calculation involves calculating the delay between input pin of a gate and the input pin of the next gate. Therefore, this timing delay includes the interconnect delay also from the drive entrance to the load pin. The linear delay model it divides the total delay of network into 4 physical components and sums them up with a circular delay. So, D total total delay is Di plus Zs plus Zs plus Zs. Di is the intrinsic delay inherent in the gate it is independent of how it is connected. It is independent of how much sign out is there what net length it drives it is simply an intrinsic delay. Again if you remember the intrinsic delay is nothing, but a function of what is the capacitance at the output. Again there is something called slope delay. Now, slope delay is the delay effect caused by the transition at the inputs. If you input is not ideal it will it will take some time to transition from KBBD to 1 more 4BBD. So, it is a slope delay is caused by that. DC is the connect media delay to an input pin is the wire delay. DT is a transition delay caused by the loading of the output. Now, we come about with consist of some wire and some some gates DC is the wire delay. DC is the delay caused by the loading of the gates at the output. It will become clear in the figure. So, let us take this example where we are interested in calculating the delay for this stage for this NAND gate. So, so DI is the intrinsic delay incurred from cell input to cell output from way to C. DS is the slope delay delay at input A caused by the transition delay at D. So, whatever inverter the inverter is driving D there will be some transitionprofile at H and that will effect the delay. DC is the connect delay from the interconnect from C to D the interconnect loading at that. So, we are we are talking about delay from actually A to D. So, it will be A to C plus C to D. So, it is the connect time is from C to D the state transition that takes place here. Again DT is a transition delay which is caused by the output loading that is the loading caused by these two inverters at C. Now, what happens is intrinsic, intrinsic is usually the intrinsic is you will not have information about the interconnect because simply the gates are connected by logical wires not physical wires. Logical wires do not have any capacitance they do not have any resistance. So, any interconnecting calculation will be only being estimated and how do we estimate that DC? So, for now assume that there is some delay with DC delay connected and now let us look at the equation here. Now, so D total so, DI would be so, what we could we could do is what we could do is if you do not want to estimate biodegradient if you take biodegradient to be 0 it will take the value of input to drive an intrinsic fault. So, for the for the rise if you take this plus it will do some calculation with rise resistance and there is a default slope and default slope for a time and rise time because of the effect of because we do not need it, but you can have positive value there is a default sign out load also. So, it will so, if we give if we do not give all the values to the tool the people make some assumption and it will do this equation for linear delay model to calculate the delay. Now, let us look into NLDM non-linear delay model it is a bit interesting compare. Now, a linear delay model prefers from some shortcomings it is not it is not accurate enough to represent present nanometer technology even 90 nanometer is not good enough. So, it is replaced by non-linear because since the linear delay model has a main component to this the delay at the optimal value dvl is being input changing and it is not a gain it is not a straight line it does not vary dvl. Now, NLDM proposes that the total delay has two major components the D cell is a DC. The D cell is again the intrinsic delay typically defined as the 50 percent input voltage to the 50 percent output voltage. Now, D cell is computed can be computed into DC DC in this case is the connect delay it is either calculated with the wire C type attribute and selected by all the DC later for this C type and by all the model. But DC here what it tells us is that DC is nothing, but an estimate based on some input with here the tool with estimate the net cut that integrated. Now, in the absence of DC cell component D transition which corresponds to time required the output finnally. We will see that we will use DC cell and D transition interchangeably depending on how the data is provided it will become clear in the coming slide. Now, as we mentioned in the previous slide there are two methods of computing DC cell the two methods are that the delay is already provided as a lookup table. So, there is a table it has some entries and the table represents the delay value is complete delay value. So, the tool will just do the interpolation we will see how. The second method is we provide two tables proposition table and transition table. There is a delay is not given the delay is set into two parts the first part the propagation represents the propagation delay we saw in the I will go back with the to point out two things we will use here. So, it will have two things one is the propagation delay, the second here and the second is the transition time. So, please note propagation delay is the time difference between input signal crossing 0.5 B to D and the output signal crossing 0.5 B to D. Transition time is the time it takes from the for the output finn to make a transition from KVTD to 1 minus KVTD. Now, DC cell is broken into two parts the propagation. So, they are two tables one is the propagation one is the transition table. Now, to conclude both propagation and transition again with the lookup table. So, that the time between two different signals on the output finn both of the process is required interpolation. So, the typical measurement for D propagation is again 50 percent we mentioned this and thus a D transition value from 10 percent. So, yeah let us let us read this the typical measurement of D propagation is a time from 50 percent input voltage value until the gate output just begins to switch for example, ok yeah. Now, so the output will begin to switch we say that for example, we are using a 1090 to begin. So, we say that the output is beginning to switch at 10 percent of begin. So, the D transition value of going from 10 to 50 percent is added to the D propagation because the D propagation is calculated from the form of 50 percent. Now, look at the two cases if the centrally table directly the centrally table is provided it becomes very simple the D total is D 10 per D. If the D cell is not provided D total D cell is nothing, but D propagation that D transition where the propagation delay is again 50 to 50 and the D transition is the remaining value. So, D total becomes D propagation plus D transition plus D. Let us look at the typical look of table. So, a non-linear CMOS look of table can use either a one-dimensional two-dimensional or a three-dimensional look of table depends on the accuracy we want. Let us look at an example of 2D table. For a 2D table one axis must be input transition time and the second axis can be different one of which usually is the total capacitor move. This is the most famous type of the look of table. Now, this is a 2-dimensional look of table. The format is like this we say it is P 4 plus this name can be written. Variable one is a total output net output. We are saying that the output delay and output transmission both now we are using this method we are using this propagation and transmission method which is most famous. So, we are telling the symbol that my output delay depends on two things. One is the output net capacitor as well as the input net capacitor which is in part of the typical look. And for output net capacitor I have chosen 4 values 5, 26, 27, 28, we need the capacitor. So, input net transition I have chosen 3 values 0, 1, 2, 1, 1, 2. The units can be anything, but it should be consistent the data should be consistent. Typical unit for capacitor from the parent I unit is usually B, S or N, S super second and N second. So, now this look of table tells me that the characterization has been done on well done. 4 on capacitance C on transmission. Now this is the value of x axis environment what about the actual data values these are the actual data values. Now delay timing. So, data is added to the output pin definition. Obviously, the output the timing any function is an attribute of the output. So, we see here that there is an output pin this defines the function. And now the timing constructs starts and you have a table here. Now this table here has 12 values 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 and I am not sure this is some typo here. This should be 12 there should be actually we have these values here. So, they are they are essentially as 12 values each corresponding to one of the one of these. So, for example, at these capacitance of 5 and the transition of 0.01 the output O the output O the rise time the cell rise time is 0.74. So, this is the again at the value at the output net gap of 5 and the transition 0.1 is output 0.4 and the cell rise of 0.75. So, this is this index 1 is always the exact is in this case the value. So, this is the way in which it is mod that is why we call it a non-linear denominator. This is not linear. The more number of points the more accuracy you have it is just a perfect interval the full term. So, now what what synthesis or timing I have this tool will do it is it will know the output it will know the capacitance of the output of the gate. The output of the gate will have its own capacitance plus the fan out capacitance plus the interconnect capacitance which might be estimated and now it knows the input in capacitance it knows the input transition by it will propagate the signal it will know the input function for that value of input transition for that value of output load it will interpolate they will the values will not necessarily correspond to this one there will be somewhere in between and the tool will interpolate. What happens if the tool finds that the output gap lies beyond this now it will extrapolate and since everybody would agree that if there is no data given and the interpolate the accuracy when the extrapolate goes low. Now what what is this value of 200 m this 200 m per charge the transition designer shows this to be the maximum value of the capacitance that this tell get right obviously. And if this time is driving more than this the tool will extrapolate and the results will be inaccurate. So, this 200 define the maximum capacitance that open up with the compressor maximum capacitance or the input transition the max value here 2.0 define the input the maximum transition A 1 and B 1 will have the input. So, these maximum transition is at input and the maximum capacitance of the outputs these limits the maximum limits are called the design transmission the design input transmission. This is the first variety of a system with a driving area system you have to make sure that your design needs all the transmission all the mass function and all the mass transmission only then only after meeting the same thing you can be sure that the delay calculation is accurate. So, the timing data forms the lookup table these groupings of data corresponds to values of index 1 and index 2 to select the value from the group. In this example there are 4 capacity load values change to transmission values there are 4 groups of data with 3 data values per group or 2 to 12 you could choose to read that in whatever way, but please note that there are 4 groups of data when we say that there are 4 groups of data we mean index 1 index 1 define how many groups of data index 2 defines which value to select from that. So, all the 4 things all the 4 things cell drive cell call drive transition call transition will use the same stable will use the same table this is the same table with the given indexing. So, this template is common to 4 all 4 the values will change of this the designer choose 4 capacitive points the transition point and at each of these points the designer calculated the right delay the point delay the right transition the fault and put it in here. So, these are the 4 things cell drive cell point TPSL and TPSL are propagation delays. So, cell drive cell call are propagation delays right transition fault transition are the output values for the output signal the index should be chosen to represent the range of values in the design this point is very very important do not count an accurate timing results if the algorithm has to extrapolate we look at we saw the propagation delay for the propagation delay is similar for combination of these things only the related pin changes let us look at the constraint set up whole time. So, we can use either 2 1 dimension or 2 dimension look up say that usually 2 dimension in both manner. So, set up time please no set up and whole time are between data and the clock pin. So, the 2 things important here are the constraint pin transition which is nothing, but data and the related pin related pin is always clocking the pin the clock index 1 tells us that either the transition values on data index 2 tells us that these are transition values on clock. So, a data pin will have related pin as CLK 2 data falling means that then clock is 3REM 6F clock 2 is falling its a negative as trigger-clock clock 2 is falling what is the set up time? Then set up time set up of time means when clockist falling rise constraint means when clock is falling and data is rising what is the set up time the clock is falling and data is falling what is the set up time. So, these are the 2 setup see this is the set up setup time line constraint set construct here in 15 month what is the type of time. So, this is set of calling timing if use is stable it has 9 values that is total 3 groups 3 groups each group has 3 values corresponding to the group is represented by index value 1 the data within the group is represented by the index value. Now, about index values now you can you can specify index values in a lookup table data and use place holder. So, in this case the template here the lookup table template here and the lookup table template here they contain the real values of the application and condition for example, this will design a use to type time we contain the real type time. But what we could also do is we could use dummy values and fit up the values. So, in this example these are real type transition value and we are filling the delay value here. The second there is one more way of doing this is that the use place holder here and just tell that how many points are there to be such a dummy value. But when it comes to writing the value here we specify the actual values of type variation. This lets us in. So, for example, now let us say 2 sets 2 and this one is low drive other is high drive. The high drive should ideally have should ideally drive a larger type of system. If people using this kind of lookup table this kind of lookup table then this value 200 will change for high drive. Let us say the value for low drive is to 100. For high drive it might be 800. We cannot use the same time here right. So, we can use this particular method this particular method use place holder here and now when it comes to low drive cell we could use we could apply the values here and use the same template for high drive cell again we could use the same template and use the same value we can do this. So, when a. So, there are two ways of doing it depending on how the standard test is going to be used to characterize we can use to define that. But it is important to understand that what are the actual index value. So, if you see index values in a cell drive table that means, these are overriding the ones given in this template. That is how the index values are chosen. The index values are chosen based on it is important not to let tool extrapolate. The left most value of the transition it could be the transition time of fastest cell that is the largest inverter with no load that could be the best transition time available to you. So, you can choose as that is the minimum value. The right most time could be the transition time of the deepest output driving the largest expected load. So, the designer will choose the value in certain way that it can be the the worst transition time he could accept. Similarly, for capacitance the left most most could be smallest spin capacitance you could add some margin to it. The right most should be the largest spin capacitance for maximum allowable panel. You do not need to worry about these you just need to be aware that how these values are used. This this way is with the standard set design. Lastly is the number of indices how many indexes you could choose. For example, how many indexes you could choose? For cat transition how many indexes you could choose? Obviously, the more the number of indices the more accuracy interpreting, but again how much spice are you willing to do? Each corner each data value needs one spice on the system. Most of the characterisation systems obviously are automated you can do it by hand and it just depends on how much accuracy you want versus how much machine time or manner was used. You can spend on the type of the process. Now this is all about libraries. We saw how do we how the broadlet how the data is represented inside broadlet, how the combination cells are represented or sequential cells are represented. We saw the linear data model and the nonlinear data model. We tried to understand how the nonlinear data model is represented inside the broadlet. We saw how set up and hold time some model. So as an assignment please go back open whatever library you have the 90 and 90 data model is in with library. Choose one combination cell choose one sequential cell for both of these cells look at how the data is represented or what is the function given, how the lookup tables have given are you able to understand what is the map type of the value look at the data what is the delay type there and so on. Just just go through this lecture and map it to the to the library you see. Now the question is how do we use the library? So the first step in a in a in a synthesis process is to finalise the let us say I have finalised the synthesis, now how do I use it? So the next few slides are detailed as how do we start the decision and how do we load the library. So running DC, invoking DC is very simple you use DC and SQL shell. Obviously you should have the path set in your environment, you should have some variable set obviously you are you can take help with the lab guy to do this. You can open it and go in but I would recommend starting with the text with the command line. The best practice is that early in the design phase it is good to decide on the design naming convention, the design style, directory structures and revision control system obviously, public project it is very essential. Now there are DC set of files this is the very this is the most powerful of its gots and also this set of time. It is automatically read into DC setup whenever DC shall start it will load up this file. It will try to find this file in this order because it will look look in the root then home then local. It is best used to customise your work environment. Now let us say you are let us say I am in charge of a particular project and five guys and then we are going through the thing. Now I could write up a source and use it so that each of those five guys when they start the DC setup they get the similar environment. So I could set my library is there. This will make sure that each of those five guys is using the same set of library. So I could do that by using this gots and also DC setup file. Example of this in office DC setup file is this it will it is must to have a hash character in the first line of the file. This they are the variables are set here. We will see what each of these variables mean. Search path tagging and target library is synthetic. So this is an example where we are setting up library in the DC setup file. You could set lot of things here. You could set lot of variables here. You could choose not to set up library there it is a coupling. So library setup this is how we set up the library. We set up first we set up the first path. Search path allows the files to be written without specifying directly passing the command. So this is a set of directories in which the DC will look for library or design path during a link process. We will see more details of this. So for example the search path here given dot there are three three things here. Dora search path means whatever is in the code just append to this just append dot and this to this. So if you are reading any design file or reading any library it will search in DC directly if you do not get the complete path. Target library is the actual standard cell library which you want the tool to use to map your design and optimize your design. Compile process will choose inferred cells from the target library. This is a very important word inferred that means if you have written a well of RTL code you are telling the design compiler by the use of target library that use this library use the standard cells in this library to implement that design. Something called synthetic library is the list of design components I told you before design by the collection of a lot of things and synthetic library is just a collection of it is nothing but a design list. So you could use a priority encoder that metacupric and even has a microcontroller and so on. It has lot of sense lot of lot of preconceived fabricated design fabricated and logically fabricated. So you will have lot of different adders you are both multiplied and so on. So this is the name of the library. So it is set like this so synthetic library is set like this DW foundation means the design library. Link library is used during linking pre and post compile all the cells in the design must be in one of the link library. Inferred cells means whatever design compiler used to implement from the target library you could have let us say your design compiler has a PLL. Now PLL is not a cell which design compiler will use to implement and PLL is a very specific cell. Then it is a clock. So you will instantiate a PLL in your design. So PLL or a memory will never be part of a target library because design compiler will not use it to implement a message. However it will be part of a link library because design compiler will use it to link. Design compiler needs to know that if for a memory or a PLL what are the pins? What are the output functions? How do I connect them? It does not need to know exactly what is the functionality of those complex cells like PLL or memory but it needs to know the pin. So it there are these are called instantiate itself. Specific cell instances placed in the RTN. So these will be part of the link library. Link library must always start this indicates that loaded design should be searched first. Or synthetic in target libraries must be included in link library. This is the example. So link library is target library obviously because target library will use when you synthesize because on a net list you will have cells from the target library. So when you all the cells in target library should be part of the link library. So link library has the these designs are loaded from memory. Target library synthetic library. These concepts will be very very clear when you start using design compiler. If you something is not clear at this point you could always code the tool part using it and the pins will become that from here. There is a command called define design lift. It is a directory where DC places intermediate design files. If you compile the log and produce some intermediate design files default is the directory from which you are running the DC. If you do not define this it will dump those files in a present directory. It is very useful to define the design lift to be completed so that you do not have a cluster of data in the present directory. Then check do not use a is a is a command which is which tells a synopsis that with cell design compiler that some cells from my standard from library should not be used. It is a very common practice to not use for example, hydride cell. The hydride cells usually people use in very specific cases because they consume a lot of current. So people use the hydride cells mostly for very very specific cases back to after the placement out has been done. So it is a very useful practice to define hydride cells as don't use. So this is the example this practice here. I guess that is it yeah. So I just summarized what we saw today. We saw in detail we saw the how the standard from library is made up. What type of cells it contains we hydride the multiple right cells by using different functions different sort of different inputs number of inputs for example two inputs one three performance one we saw what are the deliverables standard from library should have it should have a very large it should have a dotlip file it should have a Framar and abstract we should have a layout different tools to use the different use of them we saw inside of a dotlip we saw an example of the data sheet we saw how the cells are modelled inside dotlip dotlip is the most important file which can also be used for simple so we saw in not noting to that we saw how the function is represented for combination we saw how we saw two different time models linear and nonlinear so nonlinear we saw the lookup table and how the delay and transmission number that it is in to there. So it is very it would be very useful very good now to go back open at the library and spend some time in conjunction with this lecture. Thank you.