 Hello and welcome to this presentation of the STM32L5 system configuration controller. STM32L5 microcontrollers feature a set of configuration registers located in the CIS CFG module. The system configuration controller gives access to the following features. Managing the robustness feature. Setting SRAM 2 write protection and software erase. Configuring FPU interrupts. Enabling and disabling I-square. C-fast mode plus driving capability on some I-Os and voltage booster for I-O analog switches. Configuring trust zone security register access. The 64 kilobytes of SRAM 2 is particularly suitable for performance, integrity and safety and low power. Code execution maximum performance when accessed through the C-bus. The SRAM 2 supports parity check. The data bus width is 36 bits because 4 bits are available for parity check. One bit per byte is used in order to increase memory robustness as required for instance by Class B or SIL standards. Class B and SIL are safety standards. Class B is for home appliances and SIL for the safety integrity level. The parity bits are computed and stored when writing into the SRAM. Then they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the break input of the timers. Note that the SRAM 2 parity check is disabled by default. Either 64 kilobytes or upper 4 kilobytes of SRAM 2 content can optionally be retained in standby. The SRAM 2 is also suitable for secure applications. The SRAM 2 can be write protected with a 1 kilobyte granularity. The SRAM 2 can also be read out protected via the RDP option byte. When protected, the SRAM 2 cannot be read or written by the JTAG or serial wire debug port and when the boot is system flash or boot in SRAM is selected. The SRAM 2 is erased when the readout protection is changed from level 1 to level 0. Please refer to the system memory protections training for further details. The SRAM 2 can be erased by software by setting the SRAM 2 ER bit in the SRAM 2 system configuration control and status register. The SRAM 2 can also be erased with the system reset depending on the option bit SRAM 2 RST in the user option bytes. The system configuration register 2 contains the control and status bits linked to safety and robustness such as the SRAM 2 parity error flag and the control bits to direct some error detection events to the timer's break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events include a flash error code correction event, a power voltage detector event, SRAM 2 parity error event and the Cortex M33 lockup state. The system configuration controller manages the selection of the GPIO to the external interrupt or event signal which is used as an asynchronous external interrupt or event with wake up from stop capability. Configuration register 1 contains the floating point unit interrupt control bits. It also contains the I2C FAST mode plus 20 milliamps drive enable control bits. Four IOs can be configured with high drive mode even if they are not used as I2C alternate functions. They can be used to drive the LEDs for instance. The IO analog switch voltage booster is also selected in this register. The CIS CFG is a trust zone aware peripheral meaning that secure and non-secure registers coexist within the peripheral. Trust zone aware peripherals are non-secure after reset. Their secure configuration registers are secure. When trust zone is active, the secure software is in charge of selecting the secure attributes of the following features. Floating point unit SRAM 2, Class B, CIS CFG clock control configuration registers located RCC. Here's the list of Class B features. SRAM 2 parity error flag, definition of events that can lead to a timer break supported by timers 1, 8, 15, 16 and 17. When the registers are configured to be accessed by secure software only, non-secure access attempts return zero on reads. Rights are ignored and an CIS CFG illegal access is signaled to the global trust zone controller GTZC. For security purposes, some readable and writable registers can be dynamically programmed as read only in order to avoid any subsequent modification of their value. Both secure features and non-secure features can be locked against further changes. The CIS CFG CSLock R register enables secure software to lock the setting of the following features. System attribution unit or SAU, secure memory protection unit or SMPU, secure vector table base address, secure exception priority boosting, configuration of bus fault, hard fault and NMI events to generate non-secure exceptions. This register is only accessible by secure privilege software. The CIS CFG CN-SLCKR register enables non-secure software as well as secure software to lock the setting of the following features. Non-secure memory protection unit or NSMPU, non-secure vector table base address. This register is accessible by both non-secure and secure privilege software. Lock applies until the next system reset. Consumer application can request the execution of a secure service by writing a command into the RSS CMD field of CIS CFG RSS CMDR register. Secure services are pre-encoded by ST into a portion of the flash memory called root security service, also known as RSS. When the system is secure, i.e. when TZEN equals 1, this register can be read and written only when the APB access is secure. For more details about the system configuration module, refer to the reference manual for STM32L5 microcontrollers. Refer also to these trainings for more information if needed. Trust Zone Global Trust Zone Controller ARM Cortex M33 Core Memory Protection Timers Inter-integrated Circuit Controllers