 Hello and welcome to the series of video lectures on the subject digital techniques for secondary IT students. I am Dr. Sri Shaileshwarath Kajbar and in this video lecture we are going to study Verilog HDL which is a widely used hardware description language. Since this is an introductory lecture at the end of this session, you will be able to identify the components of Verilog models including modules, instances and ports. You will also be able to identify and choose appropriately the circuit description approach whether it may be behavioral or structural. Verilog HDL is one of the most popular hardware description language alongside its competitor language VHDL. It is not a programming language like CC++ however the syntax of this language is similar to these languages. Unlike CC++ where the aim is to create an executable file for particular application, in this case the aim is to describe a digital circuit. Verilog is used to describe structural and behavioral properties of any digital logic circuit in a textual manner. Verilog can be used for both hardware simulation or logic verification as well as for synthesis purpose. Now before that let us see why there is a need to learn any hardware description language. With the evolution of fabrication technology of digital circuits, problem of realization of complex digital circuits arise where in a single integrated circuit there were thousands of transistors. So designing such a circuit had two problems and this problem was two sided mainly verifying the logic that is simulation of the design circuit and second getting the layout for fabrication that is synthesis which is used for physical realization of that circuit. Hardware description languages handle the above two problems very efficiently and the designer has the flexibility to design a digital circuit belonging to any level of abstraction. Now here the abstraction level may be a system level or top level it may be an algorithmic level or behavioral level it may be a register transfer level or it may be a low level such as gate level. So before starting the Verilog basics one has to understand that everything in Verilog is described in terms of modules and the Verilog allows you to represent the hierarchy of a design. The hierarchy in this case is a tree structure of module instances which start at a top level module and proceeds to leaf modules. The Verilog structures which build this hierarchy are modules as I have told earlier these are the basic building block of any hardware and ports. Ports in this case represent input outputs related to that design. So a Verilog model of hardware is composed of modules. Now whenever you are defining any top level module all the necessary modules has to be instantiated within that module but you cannot define any module inside another module. So nesting of modules is illegal in Verilog however a module can be instantiated within another module. For example consider this figure here system is the top level module as shown in the figure system is the top level module which consists of two other modules namely comp underscore one and comp underscore two. Here comp underscore two also contains another module called as the sub three. So system comp underscore one comp underscore two and sub three are all modules which are required for defining the top level module called as a system. Now the previous figure can be indicated in this case using this diagram. Here as shown in the figure system is a top level module or parent module which has two child modules called as comp underscore one and comp underscore two. Here sub three is the child module of comp underscore two. Now when you are defining a system module first it contains the instances of two modules namely comp underscore one and comp underscore two while comp underscore two instantiates sub three module. Now let us see the basic module syntax. Three modules in very long starts with two keywords namely module keyword and end module keyword. This module keyword is followed by a module name and in bracket the list of ports. The list of ports in this case are nothing but the input output ports. Now inside the module definition first you will define the output input declarations then it is followed by the local net declarations local net in this case is nothing but the wires which are required for the interconnection of the circuit elements and these are followed by some parallel statements which are required for hardware concurrency. Now let us see what is mean by the ports. Ports in very long are very long structures that pass data between parent and child modules. Ports can be thought of as wires connecting modules. The connections provided by ports can be either input output or they can be bidirectional and that you can define in the very long module definition. Now let us say we want to describe a simple AND circuit as shown in the figure. Here A and B are the inputs and O is the output. So the very long code to describe the simple AND circuit can be written as follows. So as stated earlier the module definition will start with the module keyword followed by the module name in this case it is my AND followed by in bracket the list of ports. Now in this case O is the output port which is defined first followed by the two input ports namely A and B and these are defined first in these two lines by using output keyword followed by the name of the output port for this circuit that is O followed by the semicolon you also have to remember that this first line of the module has to be terminated with the semicolon. Then after the input definition input A comma B the last line uses the assign keyword. Here whatever on the right hand side is evaluated and it is assigned to the output O. So the behavior of this circuit is described using this assign keyword. So in this case this AND is nothing but a bitwise AND gate which does the AND operation on two bits which are input namely A and B and the result is assigned to the output variable O in this case. So this is the simple very long module definition for AND gate. Now pause the video for two minutes and write down the answer of the following question. I hope you have written the answer. The answer in this case is as follows here O, X and Y are the ports in this case. Here O is the output port whereas X and Y are input ports. The first line of module definition can be written with the module keyword followed by the name of the module. In this case I have taken it as my circuit one. You can have another name also followed in bracket the list of ports. So O is the output port which is written first followed by the input ports namely X and Y. So any digital circuit in very long can be described in number of phase but there are two widely approaches which are used and that are behavioral or it may be your structural or one may also have the combination of these two approaches also. So let us see each of these approaches in detail. So in behavioral description approach a circuit can be described using logic expressions and very long programming constructs. Here the desired behavior of the circuit is described but not its actual structure in terms of logic gates. So it is the more abstract way to define circuits. Statements like assign are used in this case to define the behavior of a digital logic circuit. Then the next approach is structural description approach. Now in this case a circuit can be described using very long constructs that describe the structure of the circuit in terms of circuit elements such as logic gates. Here a larger circuit is defined by writing code that connects such elements together. Now in this case instances of built-in primitive gates such as AND gate OR gate OR NOT gate are used. So these are the references. Thank you very much.