 Right, welcome back to the final session of the FOS in Research part of this mini-conference. Our final presenter is Julius Baxter, who's an Australian spy currently on mission over in Stockholms, where he's, Alias is a student studying a masters in the system on a chip design. So I'll hand it over to him and we'll learn a bit about the open risk platform and stuff. Yeah, excellent. Thank you. Hello. Yes, my name is Julius and I'm here to talk about the open risk platform, which is hardware, silicon kind of level stuff. So hence the chip. Just quick outline, I'll do an intro, explain what the project is, then I'll talk about why I'm talking about it, which is the recent work we've done on the platform. Then I'll talk about why I think it's a worthwhile or useful thing and why I'm here presenting it to the, like the open source crowd. And then I'll talk about what we plan for the project coming up and hopefully get some questions in at the end. But who am I? I'm from the Gold Coast and went to UQ, did a bachelor of engineering and afterwards through a recommendation of someone in the department there, I went over to Stockholm to the Royal Institute of Technology in Sweden, or Kungliga Tekniska Högskolan, which explains the acronym. And I started working there in April 2008 while I was still doing the masters for a company called Orsoc. And I'll explain about them in the next slide. I primarily work with HDL, so hardware description language, Veralog is my main weapon of choice. I do a lot of low level software stuff, assembly, C stuff. And then I put together lots of systems with make files and bash scripts and stuff. So I do a lot of that as well, to synchronize tools. And I've worked basically on all levels of the open-risk platform from the parts of the tool chain port through to the RTL. I'm the main contributor and maintainer of the RTL for the open-risk chip now. And all the way up to software and UC-Lib C stuff. So I've done a lot of stuff with it. So Orsoc, my current employer, they are a consulting company. And they make open-risk system on chips, I guess, which explains the acronym. And they use that as a platform. So people will come and say, oh, we need this done and we'll use an open-risk processor on an FPGA. Like I have here today, hopefully I'll get a few minutes to do a tech demo at the end and just show you it booting the kernel and doing NFS and stuff. But yeah, they do, so they develop products based on these boards. They also run the open-source hardware community called OpenCourse. I'm not sure if many of you have heard of OpenCourse, but they are, I don't know, what's the equivalent, like SourceForge or something, where they host projects for you and they have a bit of a directory and the emphasis is on open-source RTL level kind of stuff. So open-source stuff that you'll either put into a silicon chip or on an FPGA. So they bought that and I'll give a bit of a history of how they came about to having that in the next slide. But yeah, they do platforms, debug cables, things like that. Yeah, we have a question, but I believe we have to wait for the microphone. Sorry. Just following orders. So when you say RTL, is that the same as HDL? Or is it a higher level of things than HDL? RTL level is basically you're describing what's going on on the clock edges. So you're describing the transfer of signals between different blocks of logic. And when you do RTL design, you can do it in a more abstracted way and hope that the compilation tools or synthesis tools as they're known will infer the tricky stuff you want. Or you can go down and you can describe this as an AND gate and we hook it to an OR gate and we hook that to a flip-flop. So there's a range of abstraction you can have within RTL design with HDL. Maybe I'm not just explaining this correctly, but HDL is a language and RTL is the kind of extraction level at which you're designing. So yeah, just talking about the relationships of signals and some timing information and that as well. An introduction to the OpenRisk project. So OpenRisk stands for Open Reduced Instruction Set Computer Computing. Currently the first implementation of it is called the OpenRisk 1000 and that defines a 32-bit microprocessor architecture. So things like the instruction set, what all the special registers do, what they control, caches, MMUs, bus, or no, not bus interfaces, that's not really part of the architecture space, but then a software ABI as well. And we have, sitting in our repositories, a simulator, so like a transactional level instruction set simulator, an actual RTL level implementation. So that's the thing that you can take and then put into a synthesis tool and run it on your FPGA or do a full ASIC flow and send it to Taiwan with a few million bucks and they'll send you back some wafers. We also have some tools, full GNU GCC toolchain port and NewLib, UCLib-C and the Linux kernel as well as various other real-time operating systems. And a brief history of the OpenRisk project. It was started in 1999 as a bit of a university project by a Slovenian guy called Damian Lampret. And over the next couple of years they got it up and started a little bit of a community around it who developed other things like peripherals that would also go into a FPGA. And if you're not 100% on what an FPGA is, it stands for Field Programmable Gatoray. So it's just a set of logic that you can go in and you can define what is connected to what. And then you can reset that and reconfigure that whenever you like, which basically gives you programmable logic. So they targeted it for that at the beginning, but they did do ASICs with it. In 2003, I think it was the FlexTronics company got on board with them and funded them for a full ASIC flow and they fabricated it and demoed it and it was used in a couple of products. So it's proven in industry and it's proven in silicon. But then the core of the developers there spun it off in 2005 to their own company and basically dropped all development on the OpenCores website and supported the OpenCores website. So in 2007, they said, look, we're going to sell it. And a couple of engineers from FlexTronics who had worked with it and knew the potential of it, they said, well, we'll buy up the website and we'll support it. And that's what ASIC do now. They build platforms and systems based around the open-risk technology. Yeah, so I started work there in 2008 and they'd been kind of running with it for about a year since then with ASIC. But since I started, there's been a lot of kind of fix up in the project. So when the original development team went to FlexTronics, they didn't really keep maintaining stuff on the website. There was an odd patch for the toolchain, I believe, by some people related, but it was really left by itself. And there wasn't an active maintaining community, really. So it also took on that job, really. And I took on that job as well. We cleaned up the simulator and a lot of fixes, the RTL level implementation. So the thing which goes onto the FPGA has been fixed up. I personally did the FPU implementation. A lot of cache fix ups and various bugs in the process. So it's quite stable and sturdy and well done. We've also made it easier to get at it. So this Orpsoc thing is like a reference platform. So you just download it, hopefully have all the right tools installed, press a button, and after an hour or so you get a little programming file that you can put onto your FPGA and run the CPU and run the system. This year, well, this last year, 2010, was a big year. We had a lot of fix up for the toolchain. We've had a customer who has basically funded a big fix up of the toolchain, which was a big step. So that was quite cool. There's a couple of things. I'll explain it again. I'm really wanting to bring this project to the attention of people and hopefully garner some interest and maybe get people to look at lower level designing and open source projects. And of course the Linux kernel port for open risk was basically re-implemented. And I'll talk about our plans to hopefully get that upstream one day and what we're doing with it. So I guess I have a lot of reasons for why you would choose the open risk platform. Maybe from a commercial point of view or even if you're just a researcher or something. There's a lot of reasons why. Oh, I think it's good. This kind of went overlapped it. That's meant to say technology constrained. So I'll go through these other alternatives. There are a lot of other soft core microprocessors out there that you can get. So this is a thing where you can just get it and put it on your FPGA and run it, give it code, give it a program and it will execute and do things for you. And there are alternatives to the open risk. There's a company based in Sweden, started by a guy called Jerry Geisler and they developed the Leon for the European Space Agency about 10 years ago maybe. And they've been continually developing that. So that's actually open source. You can go and look at it. And it's licensed under the GPL. That's all very good. So you can use it for research and whatnot. But kind of closed shop. They don't really foster an open source community there. And also the LeonTuber's LGPL and I think that had a few people playing with it. But they switched to a model where the open source stuff is GPL. So if you're an ASIC company or if you're doing products and you want to then use that on your FPGA with proprietary modules, the stuff that adds a lot of value, the whole thing needs to be GPL. So it's not really an option for proprietary or commercial use really. Or it is if you pay them a lot of money, they'll change the license for you. So we'll give you a version that is licensed differently. The LM32 is written and maintained by the Lattice Micro Semi, another FPGA company. And that, the toolchain have not heard good things about and the license is questionable. Whether you can truly go and do what you want with it after it's, after you've started using it. Then there's MicroBlaze and Nios. Maybe you guys have heard of those ones. They're the big FPGA vendors solutions to soft core microprocessing. But again, they're not really free and open source. Well, they're not open source in the case of the MicroBlaze. Definitely not free if you want to do anything commercial with them. And again, they're technology constrained, which is what that thing's meant to say. There are clones of them, but they're in varying states of decay and half implementation. Well, I think the open risk is good. It's open. So as an engineer, I was always curious about what is underneath? What is going on underneath my code? What, oh, okay, and then why is this stream of instructions doing this? And then, oh, why is the bus doing that? And then, I was always curious. And so the open risk is a good way to, you know, spend a lot of time looking at, well, the open risk project and working with it is a good way to spend a lot of time at staring at wave form dumps and figuring out what's going on there, which is usually pretty hypnotic. It's basically a late 80s MIPS architecture, so very similar to the DLX architecture that Hennessey and Patterson had in their books and very similar to the power PC, the early power PC stuff. And it's an easy platform to get up to speed with. It's not overly complicated. I wanted to say something about RTL-IP, but, well, I guess for maybe for people who aren't really sure of what it is still, it's basically software. It just takes a while to compile and put on the chip. How much time do I have left? Have I gone, like, fifth? So, like, ten minutes left. Yeah, yeah. Anyway, so I think there are challenges facing open source RTL-IP. And yeah, we haven't seen a lot of it, so open cause is the main community for this stuff in the world, right? And sure, it's a reasonable level. You do get some good cause on there, but it's not really the community around it that you see with other open source software projects. And I'm kind of jealous. I want the interest that occurs in other open source projects to occur for this hardware world stuff. And I think there's a lot of attractive elements to it. So I kind of have two reasons why I think it's, or two people that I'm talking to here when I say there's not enough adoption. There's people who do ASICs for a living and there's probably not many of you in here who do that, but it's a very risky business. It's expensive to send your design away to Taiwan to get away for back and then test it. So they don't want any risk. And open source stuff, yeah, sure, it probably works for the most part, but you don't want to get your stuff back and find that there's a bug in it, because it's very expensive. And from the software engineers point of view, so perhaps people like yourselves, I guess traditionally there's been an approach of, well, I can't play with the software. I'm here, I'm just writing the code and it will run on the hardware, but if there's something wrong with the hardware, if I don't like it or if there's a tricky behavior, I can't really debug that. So I have to solve it another way. But now you don't have to. Now you can actually take the thing you're working with, the underlying hardware, and you can go and have a look at what it's actually doing. And you can change that, or you can fix it, or you can improve it. So I think there's a lot of interesting things to be done with that. Did I say it on that one? Like the hardware software co-design. So I think open source processes and IP and that level of design really opens up that world to you. Yeah, I have a bit of a winch here. I say open source EDA is not the best. There's not enough people who do RTL design. And Who at Home has an FPGA board compared to Who at Home has an x86 PC. Not many people. So I think that's why we're not really seeing the big pick up. Motivations for free and open source RTL design, I think FPGAs are becoming better, bigger, faster, more versatile. I also think that there's no reason why a equivalent to what's gone on with the Linux kernel or other equivalent big open source products that have been developed can't occur for the processor industry. I really don't. And like I say, if that was available, and people like Apple or whatever could just go and pull in a free processor from somewhere, or mostly free, just pay for the engineering, but no royalty costs, it would allow them to free up money to do other cool things with their hardware or their phones or whatever. So it's just continued commoditization of this thing. A couple of roadblocks here, I think with this whole approach, if you just want to process and you want to drop it in, you don't care how it works, you're doing something else interesting on your chip or your FPGA, fair enough, maybe this stuff isn't for you. And like I said before, if you're happy to pay our millions, fine, do it. I'm just saying the whole platform now has been rejuvenated, better tool chain, good kernel ports, pretty sturdy. And I really don't think there's too many big roadblocks anymore to having a big, successful open source hardware project succeed. And so I've been working on it for two years and oh, he wants to have my password. I've been working with it for two years and I do think there's a lot of potential with not only this platform, but the idea of doing open source hardware design and having a big collaborative community, engineers in companies, like proprietary companies, or companies doing work with open source stuff, but for proprietary means contributing back to the project, which is basically what all of this Linux kind of world or how it works, right? It's people employed by companies to do something else, leveraging open source, but giving back to the community and everyone benefits. So a bit of a bit of a spiel about what we have now. We've got a kernel port, it's kept up to date with mainline. A lot of useful debugging architectures in there so you can like, I know that's mainly for me, but you can sit there and you can step through a program with that P trace thing. That's pretty handy. Use your libc port so you can run user space stuff pretty well, busybox, gdb server. So it's mainly targeted at embedded kind of use. We do have our simulator working with networking and stuff, which is kind of cool. And open source, I've completely failed to mention the whole open cores, open source hardware, like actual physical hardware thing going on. There's, you know, these boards, the schematics and Gerbers and bill of materials are all on open cores for you to download and you to fabricate them yourselves if you'd like. And there's push button synthesis builds available for this platform. More will come as I get the time. Just a quick mention as well, if you want to know more or see more about open cores or open risk, I'll beat the open day on Saturday hosting a booth. So come along and talk to me and play with the board and crash our kernel. So what's going on in the future is I hope to do more board ports, make it more available to everyone, make it really easy to use because I think that's what you want. We need better testing and everything, but that's so big thing we need is dynamic shared dynamic linking, loading support in our linker. That's one thing we don't have in the tool chain at the moment. And I guess we'll be scouring for a while because we're a bit busy doing lots of other things and it would be great if we could have some enthusiasts or contributors wishing to help out with that. Another one is a QEMU port, which is a really good simulator if you don't know what it is, and that helps us kind of and it helps you as well. You know, if you don't have hardware, you can compile stuff for open risk and play with it on your PC. So we were going to rewrite the actual processor RTL this year, but we figured we would fix a couple of the problems with the architecture as well. And while we were doing that, we thought, well, why don't we add smaller instruction support? Why don't we do this and that? And it kind of bloomed and now we're thinking, all right, next generation open risk processor architecture. So we're really kind of polishing off original open risk, making it a cool viable open source hardware platform, but focusing on the future. So it's a late 80s risk design. We think it's a bit dated. It's still usable, but new things are occurring. Multicore processing is occurring. A much better implementation. So probably no one would use a kernel if it was a big, if it was one C file or something, a big monolithic thing. It's kind of what you're dealing with with the original open risk. I mean, we're improving it, but a much more modular design is required, makes it easier for people to look at it and use it and fix it and test it. An extension friendly. So I think a lot of this FPGA stuff is really only worthwhile when you can add on your your secret source or whatever into the FPGA and have the software easily take advantage of it. And we would want it to, you can do that now, but we want to make that even better. So, do I have time to boot the kernel on the board? If you do it while we take some questions, that'd be great. Does anybody have some questions for Julius? This is downloading the kernel from my computer to the board and then it will boot it. So it's like some bootloader built into the hardware you just power on. Julius, what's the kind of minimum dollar cost of entry for people who would like to hack on open risk? These boards? When you consider, you know, you can buy a Beagle board for 150 bucks, for example, and people can go nuts on embedded arm Linux. Yeah. So, you know, can you use free versions of their of the Achtel tools, etc., etc., so if someone wants to get into it, how much money they've got to spend before they can go play? Just the board cost, which they can fad themselves or you can buy them from OpenCores, which, I don't know off the top of my head, I think it's about 200 euros for the full board, door-to-board with Ethernet stuff and USB debug cable. But then you may have to buy the Achtel program, which is about 40 US dollars. But then all the tools are free and of course you can sit there and you can play with all your, all the low-level RTL design stuff. So, kernel's booting. Yeah, I don't know. There's some weird UI corruption going on there and the DHCP server isn't running, so I've got a manually configure the IP when it comes up. Cool. Anyone else got a question? Cool. We have, anyone want to see CPU input? And then we can do a bit of a mount. Yeah, yeah. So, I've got a Spartan 3AN starter kit from Xilinx, which has got the Spartan 3A 700,000 gate equivalent chip. Do you know how much of that one of these cores would take up? That's a good question. I actually have a similar one and I've been meaning to port orpsock to it. I do have a vertex 5 board and I know that the processor takes up or less than a third, about a quarter maybe? Okay. Fully blown though. That's to run Linux and that's with huge caching. I've increased the cache ability on it to run up to 32k now. So, but hopefully on those Spartans it's not too big and you can optional stuff you don't need like the multiply unit or the FPU and things like that. Okay. But it should fit and should run and you should be able to boot the kernel and play with stuff. That starter board was only about $250. Yeah. I was looking recently. They're about that $100, $200 maybe US but we're a parody now so it doesn't really matter. Cool. Anyone else? Digital and have just put out a Xilinx FPGA board for 200 US for educational use and that's that thing I mean they kind of built it to run microblazer Linux but that would be a really nice platform. It's like a you know brand new Spartan 6, modern FPGA, Ethernet memory that's fully programmable over USB so you don't need to buy a JTAG port and yeah they're $200 if you're buying it from a .edu domain. Supported by the Freesilinx tools. Yeah. So if you're looking for a target for your kind of push button builds if you can do it nicely you also get the digital and guys on board because they're totally up with supporting education etc etc so you might want to have a look at that one. Yeah we've got a lot of requests to do that Spartan 3a starter and I've got the DSP version I presume they're not too different I was going to work on that but in the future hopefully but I just really want to attract people to the project and get people thinking about lower level stuff you know you're not stuck just pushing a compiler and an execute button somewhere so yeah. So what website should we go to to find all this stuff? OpenCores.org that's where it all is yeah maybe I should have put a big ad there. Cool so you want to tell us what you've just done on the screen? I've just booted and I've just catted Proxy pu info and you see a bit of UART corruption there then I've mounted something over NFS then I've executed a hello world over NFS. Cool okay so everybody please thank Julius for his talk. Thank you.