 Welcome to this lecture of the course digital system design with PLDs and FPGAs. In the last lecture we have seen the behaviour of the controller and the structure of the controller how to design the controller and so on. So before going further about the some timing analysis and the design, let us run through those slides very quickly. We have seen in the slide an example of the CPU and as I said the controller job is to give control signal to this data path. And we have taken an example of instruction adding A and B and putting the result back to A, the execution part of it but that is enough to enough for analysis. So essentially it means moving A to this register, B to this register and selecting the operation and moving the ALU output back to the register A. Now that each movement involves enabling, giving a latch signal and upon the clock it moves and disabling. So this is achieved by giving a pulse, same pulse to enable and latch with respect to clock, you know you have a certain timing with respect to clock. And then when the clock comes it is transferred then it is disabled, same thing to B, B enable, latch and the clock comes it is transferred and disabled. The same time give the addition code here as I said there are various units through a multiplexer output comes and rice seed gates are there at the output of multiplexer. The enable signal of that is this one. So you give this enable signal, a latch and the clock comes it is transferred and it is disabled. So that is what is there, move A to TR1 which has a macro stuff which is enabling A, giving latch signal and the clock comes it transferred and disabled A, everything is done moving B to TR2, selecting ALU operation and then moving ALU back to the register A. So basically I said that the possible timing waveforms are shown here, the enable and the latch corresponding latch get the same signal, A enable this one latch, B enable 2 latch, ALU enable and the register A latch. And as I said this waveform itself is a pulse for the first duration of the clocks, second duration of the clock and third duration of the clock. It is little bit shifted as if it is a kind of cooking up the waveform. So that the clock edge comes when the latch is high and I said this looks like little bit of manipulation at this stage. But we will see how in practical circuit this comes very naturally and it works effectively. So the question is that how can we generate these pulses, what kind of circuit can be used, definitely this cannot be from a combinational circuit because some input like add AB code gives to a combinational circuit, it cannot produce a sequence. So it has to be a sequential circuit and the question was that whether we can use a counter to generate this. So assume a counter counts every clock period like 0, 1, 2 then it is enough at the 0th count A pulse is generated for these two signal separately. At the count 1 this is generated, at the count 2 this is generated. So at least for this part of the game a mode 3 counting is enough. So that is what we have shown you have a mode 3 count of which count 0, 1, 2 you put a logic here to look at the present state or the count and decode like when it is 0, 0, 2 signals will be 1, when it is 0, 1 other 2 signals will be 1 and so on. So we write the truth table of this then you like the input is the present state Q1, Q0 outputs are these set of signal definitely this has to be repeated okay. For convenience I am showing it together but assume there is a separate column for A enabled and TR1L. It is not that it is tied together but this happens only for this instruction maybe some other instruction it cannot be together but just for the convenience I have shown like that. And so here this particular signal is a function of the present state so we say output is a function of the present state. So we decode we put an output logic and then decode output as a function of the present state that is how we generate this pulses. And the next question was that is it generate that you know you have some crazy pulse requirement for the controller to work then this structure can it produce. So I have shown some example not maybe a realistic you know instructions waveform but let us assume put some random thing and try whether it can work. So here you need a pulse in the first clock period and the third one in the second one you need second and third and in the third set you need in the third clock period. So as I said it is easy say the first signal is nothing but the decode of 00 or decode of kind of 10 and the second one is a decode of 01 and 10 which when minimise you get Q1, X or Q0. So it really does not matter that you just whatever you know the output logic you know is changed for various decoding to produce the required output that is all what is required and this structure so is quite generic. And it can be used for any kind of controller that means you design a controller for a multiplier divider or some other any application then the same structure is used only thing is that depending on the need of these various transition, various inputs and outputs the next set logic changes for the various transition and output logic changes for the various output in each step you know because that we have a sequence or states this controller is going through and we produce at each state various output as and when required and the sequence itself is in terms of the clock period. So that is very important to understand everything is in terms of the clock period the granularity of the controller is in terms of clock period like we can the least step the smallest step we can do is in a clock period that should be understood. And another question is that whether we do this machine need to count 012 we do not care you know it can count 210 only that the logic is changed. So normally when we design a state machine we are worried about the inputs the transitions and output and we are not very much worried about how this counter counts you know and itself this is not a very in a complex case it is not a very sequential kind of state change may be depending on some input it branches to various state and there it further branches to some state come back to locally come back to the original state and so on depends on the application. So the state transition can be very complex and so we do not care about the state nor we can assign some meaningful like we cannot start saying that 0123 it makes no sense. So that problem data assignment and the controller is also called as I said finite state machine because it transit through the number of finite states for the whole operation. So it is called finite state machine or FSM okay so that need to be you know understood. So and ultimately so we said that it is the counter need not be ordered the state. So we have a step called state assignment so when you normally work we work on symbolic state at the end we assign numerical state and this can be manually done by the designer or tools can do maybe you can do state assignment in such a way that maybe this one of this logic is minimized sometime it is used to solve some timing issues all that we will see later as we progress and essentially when you are designing an FSM we have some specification some timing waveform and we translate that into basically some input state transition that means sequence of states and in each state what are the outputs that is what we are going to design and from there we can derive the next state table and output table. So we start with the specification in terms of description and waveforms then we work out these that waveform into this inputs state transition and output and ultimately we work out the next state table and output table then the structure is known and we can design the controller. So basically that is what is the finite state machine or a controller there is a counter part which need not sequentially count it goes through various states various steps various sequences and at each sequence each step some output is you know decoded which has you know which does a lot of function like enabling a register enabling a counter selecting some path through a MUX and all kinds of things. So that is the function of the controller at the beginning of the lecture I said do not confuse it with the way you write a VHDL or Verilog code and say the finite state machine do a comparison or count or make anything it just make some decision as to go to some particular state produce some output to control the data path ok. It does not do absolutely no data computation at all ok everything is done by the data path combinates the circuit that should be understood well. So we also talked about the Moore and Millet machine and many a times like there is a possibility like we have seen the output is generated as a function of the present state but in principle we can generate the output as a function of the present state and input it is convenient it has some advantages in some specific cases it cannot be done just outright in all cases but in some cases which we will see where it can be generated the output can be generated as a function of present state many a times textbook treat as two machine one is a Millet machine and the Moore machine but as I said it is very like these are kind of textbook cases with one input one output. So it is very easy to categorize like that but in real life there are lot of inputs lot of outputs so we talk about Millet output when the particular output is a function of the present state and input and the Moore output when the output is a function of the present state and input and we need to kind of internalize that process of thinking in terms of the Moore and Millet because if you get used to the Moore kind of output like working that in your mind then sometime you may miss and because the Millet output could be advantages so you should check whether a Millet output can be designed. So let us come back to the slide so this is the three block view as I said you have a state variable flip-flop and next state logic which is decoding the next state from the present state and input and the output logic decoding the present state and input you should keep this in view we use it for analysis we use it for coding maybe use it for solving the issues to think and so three block view is a good kind of abstraction and maybe as I said if you look at these two blocks both get the same kind of input present state and input so we could combine this as a logic so that is shown here you have a logic which comprises of the next state logic and the output logic. So this logic input is a inputs various inputs and the present state and there is a part which decode the next state there is a part which produces various output and this is also useful for analysis and the coding and all that so both should be kept in view the text book shows either some text book show the earlier view some shows this view it does not matter the understanding is important whether but these kind of pictures keeping that in mind will help to sort out the issues analyze and so on. So that is what is you know pictured here so let us come to this kind of part so let us analyze the timing of the state machine and if you take this structure two block view is kind of easy to kind of analyze so here because it is identical to the counter only one part is an output is an extra thing so when we work out the maximum clock period there are two sets of path we have to analyze one path is same as in counter when a clock comes the queue changes and it kind of propagate through the next state logic and the next state come gets ready before the setup time ok. So that is what is shown here you have when the clock comes this present state changes after a tcq time because from d to q it takes so much time to change then it propagate through the next state logic so at this point the data comes here ok but we know that before the next clock edge comes for the proper operation of the flip flop this has to be setup before the next edge the data has to be there sometime before call setup time. So the clock period from this edge to the next edge should accommodate the tcq plus the next tnsl is a timing the propagation delay for the next state logic and the setup time. So the clock period should be greater than the sum of tcq, tnsl and ts and of course we give a margin it is not that even if we take the maximum values it is better to give a margin and we many a times does not worry there are so many changes the temperature change and the power supply changes and all that the power supply voltage changes the timing can change. So it is always better to give a little slack little margin so that it does not violate the clock period requirement but here one other path is there like you view at the same time when the clock comes you see after tcq the present state changes but for the output it takes some output logic delay and output changes here ok. And it looks at least when you add up some here we are adding up 3 terms but here we are adding 2 terms but it need not like it does not matter maybe the output logic delay can be greater than the next state logic delay plus the setup time ok. So we have to consider the maximum delay of the both the paths like that is what I have written here tcq min is greater than max of 2 paths the red path which is the redline here this path register to register or register to output ok. Suppose assume that you add up here you get say 3 nanosecond and you add up this then you get 4 nanosecond and if you choose the 3 nanosecond for the clock period then the state changes happen properly but the output does not change before the output settles the state is changing. So output never get to change properly there could be glitches and things like that so you have to consider this ok. Now once again and f max is the less than 1 by t clock and the slack is like you subtract the maximum path I have shown only this from the clock period but the maximum path from the clock period you get the slack. But one point you should understand when you put a picture like this we assume the output is coming here ok like in this analysis we do not know where this output is going. So we have treated this as the end point when you put such an expression but in real life if this is a controller this goes to somewhere maybe this goes to another registers you know the data input or it goes to some combinational circuit like a select line of a max and that max output goes to a register. So in such cases for the completion of analysis you have to consider complete path from this register through the output logic through the whatever is the combinational circuit following up to the next input of the register ok. The complete then only we will get the picture but when I put a picture like that I have no you know a priori knowledge of that that is why I am writing like this but if there is a path terminating on a register you have to consider the whole path ok. And in a sequential circuit definitely it will terminate in some kind of register other than you know very simple kind of indication or something like that like some lighting up LED or something like that then maybe this analysis is helpful but that you should remember that it goes somewhere and when you analyse you have to analyse from this point all the way up to the end point that you should keep in mind. And so ultimately you have if you find you add up together if you find that the clock period cannot accommodate it then you have to increase the clock period or the frequency has to be reduced to accommodate this whole path to make it work. But the another thing is the whole time violation that we know that at this point when a clock comes the data the rule is that whatever the data was there it should remain there you know it should remain there when a clock comes the data was there that should remain there for some more time called whole time. So, but we know that when a clock comes the data here the old data here will change only after tcq plus t next-side logic so we take the minimum that means the data will change from tcq plus t next-side logic. But there is a maximum value and the minimum value as far as whole time is concerned minimum is the critical kind of timing. So, the tcq min plus t next-side logic min should be greater than the whole time the maximum whole time. So, that is to violate the whole time and as I said there is no clock period here if it violates you have to increase the combination delay why there is no clock period is that it refers to the same clock edge you know because we are the data like a clock edge comes the data here as to remain there for some time. But the data changes at this point due to the same clock edge so we are not like in the clock period analysis we are going from the one clock edge to the next clock edge. But in a whole time violation we are considering the same clock edge like a clock comes the previous data when the clock comes has to remain there for some time. And we are working out because of the same clock edge the data here you know how fast the data here changes it propagates here it propagates there and it changes there that is why the clock period is not there. So, if the whole time violation happens then it is you know it is nothing do with the clock frequency it is you have to increase the combination delay and normally you put 2 like the pictures will show some 2 inverters back to back you put then this problem is solved. So, that is the timing analysis of the state machine almost exactly similar to the counter and the timing analysis of all sequential circuit looks same. But I just wanted to reinforce that fact actually need not be considered separately. But then again for the learning that is useful to reinforce and consider this extra path which cropped up and if you consider maybe the 3 block view that could have been maybe little easy like here you know you have one set of paths here and other set of paths there so whichever way you look at it it is all same. So, that is the timing analysis for the state machine and ok this is the part which I have already discussed. So, let us look at how to go about designing a controller and many times when you design a controller you have some description like if you have a CPU what you have is a data path and you have some instructions and you know what the instruction does ok you may write it in text what the instruction does and now you have to convert that instruction into steps in data path you know how the data path operate in terms of the steps of data path that is again a maybe textual description. But we are already bringing in some sequences some steps or sequences and that is very useful because we are designing a sequential circuit. So, if you can the moment from an instruction to kind of steps or sequences is already we are coming near to the control algorithm. Now the next step is to write a waveform you know that is what we have done we have described like when we took the add instruction we have textually described the sequences like moving something selecting something and so on. Then we put a waveform then so that is what is required now so like when you design the control algorithm the first step is always writing the various sequences writing the waveform and ultimate aim is to design the next side logic and output logic. So, for us the third step is that you think convert this waveform convert this sequences into states and it is almost straight forward because each sequence need a state like that some input comes then it goes to a sequence or some input comes it go through 2 or 3 steps or 2 or 3 sequence in the case of add instruction one instruction came and it just went through some 3 steps. But it may be different that like some input came it goes through 2 steps and it check for some other input then it make a decision to go to a step A or step B and continues and things like that some time it comes back and so on. So, that is designing a control algorithm so let us look at the slide so basically you will have to decide the sequence of operation for various input combination and it is not you know kind of it cannot be done easily from a waveform to a next state table or an output table or the truth table of the truth tables of next state logic and the output logic. And many a times we are not clear there are lot of you know possibilities like in add instruction we could we have moved A to TR1 and B to TR2 we could have done the opposite we could have moved the A to TR2, B to TR1. So, when you work out a sequence there are various other possibilities like there is no kind of it is not very clear at the beginning what all sequences what is the best minimal way of doing efficient way of doing the sequences. So, you have to literally work out we have to work out and we cannot work out in terms of the truth tables and so on okay. So, we need as humans we are good at some kind of graphical tool to think and that is what happens in a software you know that there are flow charts or pseudo codes which helps you in thinking like you have an you are trying you have a vague idea of an algorithm and you are formalizing it in very clearly then graphical tools will help okay. So, we have a set of sequences set of waveforms and then we have to convert that in terms of the state of the controller transition of the controller depending on various inputs and outputs produced at each state. So, all this can be done better done graphically. So, as far as a state machine or controller is concerned there is a graphical tool similar to a flow chart in software and that is called state diagram. So, state diagram helps you to visualize the control algorithm in terms of the state machine behavior that is what is basically done. So, let us look at the that is what written here we use a graphical tool to basically to visualize it is for a human being not necessarily for kind of you know the languages or the software tools. But essentially we will translate those kind of the diagram what is in the diagram to kind of equivalent description for various languages. So, that is a state diagram. So, basically what it means for the state diagram is that what we are trying to represent is we have to represent the states, we have to represent inputs and the state transition like you say a particular input came in a particular state then it transit to another state okay and in each state it produce some output. So, that is what state diagram captures various states various transitions which is the states are represented as an oval or circle maybe like oval is better because the circle is very difficult to draw a proper circle, oval maybe better because we can write something within and at least even if normal human being draw a circle you will end up with an oval. So, maybe we can use oval and transitions will be shown as arrows from this one oval to other oval and we have outputs various outputs in real life there could be 5 to 20 outputs for state machine that is written you know somehow connected to the state because the outputs are associated in each state. So, basically that is the state diagram and we have to from the state diagram we have to derive this next state logic and output logic after doing the state assignment okay that is the basic idea. So, let us look at the state diagram so once again keep this structure in view the state flip-flops the next state logic and output logic 3 block view or the 2 block view and then let us go to the state diagram. So, in the state diagram we have states, transitions and outputs. So, let us look at the states and transition so this is called unconditional transition that means the controller present state was some state may be s0 like if you have 3 flip-flops it means may be 0 0 0 okay 3 0s unconditional transition means when the clock comes the state go to the next state like it transit from 0 0 0 to 0 0 1 or you go back to the diagram it means this present state was 0 0 0 0 and we decoded to produce some output a clock comes irrespective of the input the present state is decoded to the next state 0 0 1 and the next clock comes that is loaded there that is the meaning of this and you are in one state the controller is in one state upon the clock it transit to the next state that is there is no condition it happens on the clock there is no input condition. So, there could like unconditional transition there are conditional transition that means the state machine present state is some state called s0 and now there are inputs you know you look at here this is s0 there is there are a lot of input one input is called enable and if enable is 0 the next state is decoded as something if enable is 1 for the present state the next state is decoded as something else. So, depending on the input value the next state changes and upon the clock that the present state become the next state. So, that is shown here like the present state is s0 and when the next clock comes if the input is enable is 0 then it goes to s2 enable is 1 it goes to another state called s1 and outputs here and outputs here are different so different action happen. So, it is like in a flowchart you are making a decision depending on some input you branch to some state and do something else totally different maybe you can imagine in the case of kind of CPU example say this produces this is the state for fetching the instruction and depending on the instruction type of instructions like say the move instruction you come here say the add kind of computation instruction you come here and do something and so on okay. So, various you can connect it with the kind of applications you know kind of scenarios we this can fit in okay. Now there is another very useful structure which is useful here the present state is s0 and there is an input called enable and it could be called anything and as long as that is input is 0 it remain in that state and when that input like however many clock comes it remains there and when that input becomes 1 it transit to another state. So, you can say it is we are waiting for something to happen okay. So, like you can imagine the controller initialize something and you are waiting for that some signal from the circuit or you use there is a data path which is doing some computation you enable that you know you kind of started that computation you are waiting for it to get over the state machine when it gets over it is continuing and doing something like that. So, very useful thing it wait for some signal wait for something to happen and it remains in that state. So, it means that the state was something some state and it is wait for some input to goes go high from the data path data path is doing something is waiting for the state machine is however many clock comes you know it is it can remain that state for a day if that input does not come. So, it just remain there in S0 when that signal comes it transit to S1 and do something else. So, that is what is shown here it is a conditional transition. So, many a times it is called wait and go like you wait for something then go to the next state. So, only these are the kind of three you know state transition possible there could be variation of this multiple transition on multiple more than one signal you can imagine there are two signals controlling then there could be up to four transition depending on maximum four transition and so on. So, let us look at the output now we have to handle in the case of output both Moore and Millet output. So, like this is the Moore output I have shown here in this state say there is a signal called read bar which is 1 and latch 0 ok. So, that is what is shown here and this is associated with this state. So, it essentially means that the S0 is decoded to produce read bar 1 and latch 0 and in this state the read bar is 0 it is transit like it is change from 1 to 0 and latch is made 1 and maybe in the next state and the latch is 0 then you get a pulse on the latch for 1 clock period duration. In the case of Millet output then you have this latch as a conditional output. So, here you see the FSM is in this state S0 it is waiting for this enable signal to happen and when enable signal and as long as it remains in this state the latch is kind of 0 because latch is 1 when enable is 1 that is a condition here. So, when enable comes it does 2 things transit next state upon the next clock and in this state itself when the latch becomes enable becomes 1 the latch becomes 1. So, that happens in this state before the state changes and this means in the next clock when enable has become 1 in the next clock the transition happens and you know that it has to be set up much before for the transition to happen because we have this if the transition has to happen then that enable has to come sometime before the setup time and the logic delay then only the transition can happen. So, the enable in this case has to come properly much before. So, when this controller is in this state and the enable comes before during that duration the latch will be 1 so that is the meaning of it. We will see the timing of the Millet output later but that is how the state machine looks like ok. So, let us take an example state diagram very simple state diagram and this is not something kind of arbitrary state diagram of a controller. This is the state diagram of a multiplier which we will take as a case study later. But I just want to kind of highlight how a real life state diagram looks like. So, it is very simple state diagram. So, this we have three states and you see S0 and this shows that at the power on you have to bring it to a starting state because we have to start in some known state. So, we will see how to bring a controller to a power on state and then it is waiting for a start signal. So, here this is the output there are four output called p reset kind of shift signal, load signal and select signal ok and upon the start. So, it shows that it is waiting for a start signal from outside upon the start. So, this is the kind of power on initialization everything is made kind of inactive upon the start signal it comes to a state called initialization state it initializes the data path ok. So, reset is made one some loading happens in the data path then it goes to a computing state where number of iteration happens ok. And it is waiting for that iteration to end we will see how that happens. So, it is looking for the computation to stop and that is called a max signal as long as the max signal is low the computation happens and this is the kind of shift signal is one for whatever reason we will see that later and it is selecting some path in the data path. And when the signal comes from the data path it goes back to the starting state waiting for the next start signal and so on. So, this is a kind of real life state diagram of a controller of a multiplier and you see that the inputs decide that state transition and there are states 3 states and for each state there are kind of output associated most of it is more output. But you see this select line is a milli output because select line is a function of some signal called r0 which is not shown here need not that it need not be the case that some of the input coming to the state machine need to produce the milli output you know it is not required it can be something else but which is related to the data path we are controlling naturally that has to happen. So, the moment you do this state diagram then we can write the next state logic and output logic that is the most important thing. So, like look here and before going that we have to assign some state kind of state assignment that need to be done. So, here if you do binary encoding for 3 states we need 2 flip flops okay. So, let us assume the states are like you have 2 flip flops Q1 and Q0 let us assume a sequential state assignment saying that this is 00, 01 and 10. So, how does the next state logic looks like you know it starts like that at the power on next state is present state is 00 and input signals are there when start signal is 0 the next state is 00 itself it remains there. When the start signal is 1 then the next state is nothing but 01. So, looking at the state diagram you can write the next state table. So, the moment you have the state diagram then you can write the next state table same thing is true of the output table the truth table of the output logic or output table like you see here in the state s0 the p reset is 0 shift is 0 load is 0 select is 0 but when it comes in the state s1 or 01 reset is 1 load is 1 rest are same okay. So, that is so, that can be easily written in a table and one thing I should mention that many a time some textbooks will show that like for kind of brevity or for a concise representation it will show only the signals that change okay. That means do not write everything you have 10 outputs do not write 10 outputs everywhere see here if you see reset and load only changes this remains so do not write it. But this as far as the figure is concerned it will be much neater but when you write develop a next state table or output table or write a code to do this you can miss that point do not write you will get into lot of trouble. So, I do not suggest that you do such a thing okay. There are clever ways to kind of circumvent that problem by initialising some default values and so on in a coding but it is not a very good idea. So, you should it is better you write explicitly what are the outputs okay. I am now only I am warning kind of various pitfalls people or the mistakes people make when you know when you are designing the state machine. So, let us look at the both tables next state table and the output table. So, that is what is captured here like the this is the present state q1 and q0 we have two inputs start and max only two inputs are there the start and max. So, that is what is shown here and we are decoding the next state that is a kind of function of the next state table. So initially the power on it is in 00 the present state is 00 when the start is 0 and max is down care we do not care about the max then the next state is 00 itself. And when start becomes 1 max down care 00 transit to 01. And if you see the next transition when you are in s101 there is no condition it transit to 10. So, when you are in 01 the respective of the condition the transition is made to 10 and again when the max is in you are in 10 max is low or inactive then it remains there waiting for the max to become 1. And when max is 1 it transit to 10 is transit to 11. So, you basically get two equations for D1 and D0 normally we take we form the equation in terms of the q1 q0 and the in board minimise it and all that not required this can be easily coded and the tool synthesis tool will do the optimisation and kind of create the necessary circuit to implement the next state logic. But mind you that this state diagram whatever the state and transition part and the next state table is equivalent you know we have written the table from the state diagram only. So, many a times in design we need not write this table we describe the table in terms of hardware description language looking at the state diagram. So, the moment you design the state diagram the controller design is over we describe this next state logic that is all in hardware description language then the design is done. So, let us look at now the output logic and as I said is not good to kind of you know some textbook will show you that you know you even write the output here various output and you say 400 what are the outputs. But then it is very crazy because this being a next state logic table the 00 is repeated twice. So, you are forced to write the output repeated twice and we have no way to know whether the output is a function of the present state only or input and there is confusion and sometimes people write the input condition on top as a kind of row label this is a column label and the resulting state and all that. In that case it cannot be combined at all but I suggest that you do not complicate use a simple method to represent it separately represented conveniently at least for you to study in nowadays in real life there is no need to write a next state table or an output table. So, this is the output table like present state it is a function of the present state present state is 00 then you know that everything is 0 all the outputs are 0, 01 this reset and load is 1 and 10 the shift signal is 1 and select is r0 is not shown here but maybe you can show the input as also in the table does not matter but then that is the way it is again this is exactly equivalent to the state diagram because it is specified for each state the output though kind of the output logic is kind of identical to the state diagram it is enough. We write the hardware description looking at the state diagram the moment you have drawn everything is done and captured you can describe in a hardware description language from the like we can describe the logic next state logic and output logic looking at the state diagram that is enough for the design. So, that is the it is about the state diagram and the next state table and output table. So, like before going further we have like we will start with a case study at least I will mention the scenario and do the design in the next class. So, just now we have seen we have done the timing analysis of the state machine basically the register to register path and register to output path possibly extended to another register path whole time elation. And we have seen that we have to go from the textual description to waveform by coming out with a sequence of steps and ultimately translate that sequence of step into the state of the state machine and various transition and various output it produces and to many a times as I said control algorithms are not easy to kind of you know design because there are various possibilities we need to work through it is not that straight forward you get the algorithm. Maybe there are like when you work with the CPU case you will find that there are common part like you might come out with the state diagram for various instructions then you find that there are instructions for which the number of states are equivalent. So, you can combine them together and all that. So, it needs a lot of kind of work on a piece of paper and the graphical tool is convenient. So, we have a graphical tool called state diagram which represent the state which represent the state transition depending on the input and which also shows various output. So, we have seen some kind of the state represented by all arrows represent the transition. We have seen unconditional transition where upon the clock a present state goes to the next state. And conditional transition where depending on input it makes some branching two or more branching and there are also wait and go structure which wait for a particular signal or a group of signal to change the state then goes to the next state. We have seen Millet and Moore outputs normally the outputs are shown connected to a state and the Millet output is written as a function of the input that input may not be part of the state transition that you should keep in mind. It could be some separate input coming from the data path and I also said that do not use shortcut when you describe the output do not write just the output which changes. So, that there is no confusion and we have seen an example state diagram and we have tried to work out the next state table and output table from the state diagram. What turns out is that the next state table we write all the information is in the state diagram output table we write all the information is in the state diagram. So, the moment when somebody draws a state diagram the control algorithm is fixed and the everything required for the state table next state logic and output logic is there. So, it is enough in our methodology we code this in a hardware description language the thing is done. So, I think kind of you get a picture of kind of what is the controller what is its structure what is how it is designed what are the tools we use graphical tool we use to design the controller and now we will illustrate it is not that unless we do some smart real life scenario this may not become very clear. So, I will take a simple example where the concentration is on the controller not the data path. So, because if you put a data path then we have to design the data path. So, I have taken some one example where there is not much of a data path but then that there is a controller which is a very it is not that I cook up something very simple it is a whatever I describe is a very useful thing in the next lecture the case study. So, our idea is that we go from the word description to all these procedure all the way up to the next state logic and output logic. So, you can relate the oldest step you know that in the present scenario that we are not doing everything by hand most of it is done by the tool but there is a part where the designers involvement is quite high. So, I will illustrate every step involved in the design whatever the designer does and even the tool does ok. So, that you get a clarity understanding that is what is the lecture is this course is about I want to bring the concepts very clear in your mind what the designer does what the tool does without much relation to particular tool. As we go along I will show all that thing in some kind of design tool definitely that will be illustrated but this case study this is a kind of simple case study to start with we will discuss in the next lecture. So, do not take it very lightly this kind of topics please go back look at it analyze it and learn it well it should be clear in the mind you know it is not that. So, you should work out in the mind and you should be able to visualize all these in the mind then because when you design complex thing it will be good if you can kind of design these things in the mind. So, I wind up the lecture here thank you and wish you all the best.