 Greetings, Risk Five Friends. So today is going to be shorter than usual. I'm not going to be actually doing any live work. So, you know, there is going to be just a bunch of show and tell, I guess. So you can see here, big schematic. So this is what I have been working on over the past few weeks. This is the sequencer base. So if you want to know what that is, just, you know, watch the previous videos. But I want to draw attention to some things here. Let's open up this small section. And we can see here, this is actually a comparator. And what I'm doing is I'm just checking the instruction for bad instructions. And there are two defined bad instructions. One of them is all zeros, I think. And one of them is all ones in the lower 16 bits. Or no, one of them is all ones. It says so right up here. So one of them is all ones. And the other one is all zeros in the low 16 bits. And those are defined as bad instructions. So now in TTL, there is a 74, 688, which is an 8-bit equality comparator. So you feed 8 bits into it, your 8-bit signal, and then your 8-bit, you know, it could be a constant, and it'll output whether they are equal or not. Unfortunately, we are using LVC. This is the low voltage CMOS, the 3.3-volt version. And there is no 3.3-volt version of the 8-bit equality comparator, pretty much because of market forces. So there is a 688, it's just a 5-volt version. In fact, let me show you that. Let's see. So here is the 8-bit magnitude slash identity comparator. We're looking specifically at the 688. The 687 is the magnitude comparator. And, well, we can see that it's an LS. And if you look through, you know, Digikey or Mouser, this is all you get. You don't get anything else. And if we look down to the electrical characteristics, yeah, it's basically just a bunch of XORs, we can see. Let's see if I can make this a little bigger. Right. Okay. So supply voltage, nominal 5 volts, right? Min 150 millivolts below that, max 250 millivolts above that. So this is a 5-volt part. It's not meant to operate at 3.3 volts. You can't do it. Look at the input high and low-level voltage. So we have 2 is the minimum threshold for a high, and 0.7 is the maximum threshold for a low. Now, if you feed a 3.3 volt logic signal into this chip, it will work because 3.3 volts come out, and that's greater than 2. So there you go. The input works. And if you have a 3.3 volt chip that is 5 volt tolerant on its inputs, then you could feed the outputs of this chip to that 3.3 volt chip. And again, things will work. So this is one possibility, is simply to use the 5-volt part. Let's take a look at the speed of this part, though. So if we go down here, it's okay. I mean, it's not bad. It's showing, what, 12, maybe 17 nanoseconds, which is okay. So that's certainly one possibility to consider. Let's also, again, take a look at the schematic. So this was my solution using only LVC parts. So we have this open collector slash open drain buffer. The 07 is a buffer, and the 06 is an inverter, and I talked about this last time. And basically, you tie all the outputs together. Now, because this is open collector, you do have to pull it up in case none of the outputs are, in case all of the outputs are open collector, then the output is high instead of high impedance. And then that gets fed to a gate over here. So there was a comment basically saying, yeah, that's not going to work. And they were pretty much correct. And let's see why. So let me pull up the data sheet for the 1G32. Okay, so here is the data sheet for the 1G32. And first of all, just for fun, let's take a look at the propagation delay on it. So propagation delay at 3.3 volts is typically 2.1 nanoseconds. So it's fast. But what I really want to show is the input capacitance. So it says 5 picofarads. So let's do some math. Okay, so what we have is our input. And we have this going to 3v3, and it's 10k. And it goes to the input of the chip, which is 5 picofarads. 5 picofarads. Let me use a white marker. Okay, so the input comes in over here. So essentially, this looks like this. That's what an open collector output basically is. Either the switch connects the output to ground or the switch is open. So if the switch is connected to ground, then the capacitor is pretty much immediately discharged, or as discharged as fast as current can be drawn into the chip. So that's pretty fast. So we expect to see something like this. However, when we open up the switch, well, the capacitor is going to charge through that resistor. And then we're probably going to see something like this. And the question is, well, when does it hit two volts? Because that's the threshold. So let's do some calculations. So there is the voltage and there is time. And let me just think. So the voltage is going to be equal to 3v3 times. And then what I usually do to figure this out is, I know that there is an e to the minus t over rc in here. And what I do is I say, okay, what happens when t equals zero? Well, when t equals zero, e to the minus zero is just one. So this is obviously wrong. So I might need to put a 3v3 minus that whole thing in there. Sorry, a one minus that in there. That way, when t equals zero, e to the minus zero is one, one minus one is zero. So the voltage is zero. And then as t goes to infinity, well, e to the minus infinity is just zero. So 3v3 times one minus zero is 3v3. So this is the correct formula. That's how I do it. Anyway, I don't really memorize the formula. I just sort of like, you know, remember what the factors are. And then I just figure it out from there. Okay, so let's, let's say r is 10 times 10 to the 3. So that's 10k. And c is five pika ferrets, which is five times 10 to the minus 12 ferrets. Okay, so we have v equals 3.3 times one minus e to the minus t over. Let's just multiply these out. It's 50 times 10 to the minus nine. Okay. And I can just say 3.3 one minus e to the minus t of to the minus. So this is t times 0.02 times 10 to the ninth, just inverting that. So 150th is 0.02, 10 to the minus nine inverted is 10 to the ninth. Okay, so we want to know when what time that's going to equal two volts. So we have two equals this. So I can divide by 3.3 equals one minus e to the t times 0.2, 0.02 times 10 to the ninth. Okay, so now I can take the e factor, put it on one side and take this factor and put it on the other side just to get rid of the minus sign. So e to the minus t 0.02 times 10 to the ninth equals one minus two over 3.3, whatever that is. Now I can take the natural log of both sides. So we end up with minus t 0.02 times 10 to the ninth equals the natural log of this. And then, of course, I'm just going to divide by negative 0.02 times 10 to the minus nine. I guess that was kind of stupid to do the inversion because now I just have to do it again. So t equals negative 50 times 10 to the minus nine times the natural logarithm of one minus two over 3.3. Okay, let me take out my trusty RPM calculator and work this out. So we get one minus two over 3.3, take the natural log, natural log, it's negative. So I take the negative of that, multiply by 50, and times 10 to the minus nine, well, that's just nanoseconds. So this is equal to about 47 nanoseconds. So there you go. When the switch opens up, it's going to take 47 nanoseconds for the voltage to be high enough for that gate to register as a one. So compared to a gate that switches in two nanoseconds, or even a gate that switches in 12 or 17 nanoseconds, that's pretty slow. So what I could do is I could make this 1k. And the 1k is going to go into where? The 1k is going to factor into here, which basically means that I'm just going to go 10 times as fast. So instead of 47 nanoseconds, now it'll reach the threshold in 4.7 nanoseconds, which is okay. There are some other complications like, well, you know, we've got all these outputs tied together. And when the switch opens, I don't think I think there's some like output capacitance that gets in the way. So I really, really, really don't want to do this. So, yeah, so that's the kind of the bad part of this. So what I'm going to have to do is go into the schematic and look at all the places that I did this and replace it with my chosen solution. Now I said that one of the solutions was just using the five volt part. And because a lot of the three three v three parts that I use are five volt tolerant already, I don't have to worry about doing voltage conversions. The five volt part will happily take three v three inputs, and the three v three parts will happily take five volt outputs. So so the other solution is something that was suggested, let me just close this. So this is the ATF 1502 ASV it is a 3.3 volt part, and it is a CPLD a complex programmable logic device. So let's talk about those for a moment. So let me get rid of all of this. In the beginning, there were pals, and these were programmable array logic devices. And what these were, essentially, the simplest ones were just what they call some of products. So the idea is that you would have inputs in, in, in, and you would be able to select either the positive or the negative of each of the inputs. So that's what that looked like. And then you would have and terms and the and terms looked like this. So you would get a bunch of and terms, I'll just draw, you know, for a group of four. And in between each of these intersections would be a fuse that you could that you could blow or connect. The outputs of these, so these, these are what are called the and terms. So I'm going to put a little and gate at the end of each of these. And the idea is that for all the fuses that were blown here, those signals would be ended together. So you could and, you know, the, the, the positive of one input, nothing from the second input, the inverse of the first of the third input, and so on. And the, the macro cell would be basically a group of those with an or gate at the end, just like that. And you could possibly invert it. So let's just put an inverter here. And I don't know, do this, and that would be your output. So in this way, you could do a lot of you could do a lot of different logical functions. And you were basically only limited by the number of and gates that fed into an or gate. And there were some pals, which had more than others. Then there were other pals, which had registers at the end. So, you know, there would be a register here, you know, maybe we'll call it a D flip flop. And there would be a clock line. And that would be your output, you know, or maybe it would be Q naught would be your output, you know, one of those. So, and that was pretty much the, the extent of it. Some pals even allowed you to fold back the, the Q outputs back into this array, you know, with, of course, the negative, so that you could sort of do little feedbacks. And then you could, you know, make little counters or, you know, whatever. So that was that then. And then the question is, well, okay, how did you program it? Well, you programmed it with, with high voltages. And they literally blew fuses in there. So they were one time programmable OTP, one time programmable. So there were also, for a brief period, peals. And these were programmable, electrically erasable array, logics. Okay, so the idea here is that the fuses were not permanently blown. So you could reset them electrically. There were also ultraviolet versions of pals that you could actually erase by just putting them into an e-promo racer with ultraviolet light. Eventually, there came the gal, which was the generic array logic. And the generic array logic survives today in the form of the ATF 16v8. No, I don't think they make those anymore. The 22v10, they definitely make. And I think that's probably all you could get. There may be a 20v8. What this, what the numbering system means is that you have 22ios. And you can have 10 of those being inputs, as many as 10. Same thing here. You have 20ios. Well, okay, obviously they're notios. Yeah, okay. So there are 20ios, not all of them are outputs. Maybe the eight is the number of outputs that you get. I think that's what it is. Yeah, right. That's what it is. So for the 22v10, there are 22 pins, 10 of which maximum can be outputs. They can all be inputs. And basically, it's the usual sum of products array with registers on the end that are optional, with optional clear, optional preset, I think. There's a clock, there's an output enable. So there's a bunch of options for each of these so-called macro cells. So the 22v10 has 10 macro cells. The 20v8 has eight macro cells. And that's basically that. So after the GAL was wildly successful, then there came ever more complex devices. So CPLDs are kind of next on the scale of complexity. These are the complex programmable, programmable logic devices. And for the most part, they're sort of like GALs, except they're kind of bigger. They have more features. And that's what the ATF 1502, 1504, and 1508 are. And that is the thing that I want to look at. What's next? The FPGA, the field programmable gate array. So this is like the C of macro cells that have very complex routes between them and all sorts of IO options. And it's like complex squared. So let's take a look at this CPLD. So let me show this thing again. Okay. So here's an example of a macro cell. So we can see that there are these five AND terms. And these are the same thing. You can see here, there's this little buffer symbol with a bubble. So you can select the positive or the negative of this. And there are basically 80 lines that go across. So you have 80 signals. That's 40 signals plus their inverts. And you can add them all together. And here are these fold backs as well. There's one fold back here. They don't call it a fold back, but they call it a feedback. This comes from an IO pin. So this is an input. This comes from, say, the output of this XOR gate or the output of this flip flop. And it can go back into the global bus. So basically, you can select any of those. You can add them together. And then your function is programmed using fuses. Your sum of products is programmed using fuses. And then there are the options in the macro cell. So here's an example. Here's a view of the PLCC version. And this is the TQFP version. They have different pinouts. They're actually rotated. So you can see the IOs around the edge. Okay. This is the macro cell itself, not the macro cell. This is the overall view of the chip. So you've got these buses. You've got a bunch of macro cells organized into blocks. For the ATF-1502, there are 16 macro cells in block A and 16 macro cells in block B. So that's 32 macro cells. So at a maximum, that would be 32 computed outputs as compared to the 10 that you would get in the 22v10. So this is obviously a bigger device. Okay. And they don't actually tell you how to program it because that's the secret squirrels loss. However, white cork has put together a github repository, which actually explored what the fuses did because what you can do is you could take Microchip's crappy bitstream generation program and you can create bitstreams out of it. Or you could take the bitstream and you can start flipping bits and then just sort of analyzing what happens to the chip. And in this way, white cork was able to determine what fuses did what. And I also made a bunch of diagrams to show what fuses do what. So now we have a way to program these chips using open source software. So things like nMyGen and Yosis and Python and that sort of thing without having to go through the crappy Windows only software which crashes all the time. There are some limitations though. You can get as far as defining the logic and then there's a gap and then there's how to convert that logic into fuses. That results in a file that you can then write to the chip using a standard JTAG connector. So there's that little gap that we have to jump. So let me show you how I'm going to do that. So now I can finally show you this thing. All right. So this thing right here is a diagram of the 181 ALU. This is the first chip that I wanted to tackle because it would be probably the most complex chip that I would want to convert into a CPLD. Oh and in terms of what my self-imposed rules allow me to put on these CPLDs. So you know that I've been using these one gate chips. So my self-imposed rules are if something is ROM-like then I can wait. If something is a very large lookup table with lots of inputs and lots of outputs and they aren't separable then I can convert that into a ROM. If something is a logic chip that should exist but doesn't because of market forces then I am allowed to to substitute that one for one for a CPLD. So here's an example right here. The 181 is an ALU chip. It's not available in 3v3 form. But if market forces were slightly different and people were still using the 181 well there would be a 74 LVC 181. There just doesn't happen to be one. So according to my rules I'm allowed to take one 181 chip converted into logic and program it into one CPLD. I'm not allowed to put any extra logic into the CPLD. I'm only allowed to implement the logic of this one chip. I'm not allowed to take say two 181s and stuff them into a single chip. So those are my self-imposed rules. So in effect I'm basically saying well if there were a 3v3 version of the 181 this chip would be it. So that's that. Anyway in the datasheet of the 181 they're very nice. They very nicely laid out the logic of these chips. Now if we look at this closely you can kind of see that there are various levels here. So here we go. So this is one level and you can recognize this as a sum of products. Yes there is an inverter on the end. But basically there are all the AND gates. Here some of the inputs are inverted and there are the OR gates. So in the CPLD this is basically one macro cell right here. So we have one, two, three, four, five, six, seven, eight. Eight of them. Now these XORs although there are XORs in the macro cells unfortunately it's not easy to just you know take the OR gate plug it directly into the XOR and then take another input and plug that into the XOR. It can be done but it's a lot easier if you have the space to just reserve one macro cell whose function is only an XOR. So that's one, two, three, four more macro cells. Okay so what's our total? 12. Okay now we can see that the next level is again a bunch of sum of products. So here's a product with really no sum so it's one sum right. So there's one, two, three, four, there's five and there's six and there's seven. So we're up to what is it 19 now I think? Then there are a bunch of more XORs so that's 20, 21, 22, 23. Here's another macro cell so that's 24 and here's the final macro cell so that's 25. All right well we have 32 macro cells in our chip and we've used 25 so it should work. I'm not using any registers so I don't have to bother about that complication. So what I did was I was able to determine that if I could program this in nMyGen and basically program each layer one by one there's a bunch of commands that you can use to generate sum of products and it looks something like this. Let's see if I can pull this up. So yeah okay so here's an example of a PLA file and a PLA file basically specifies your inputs, your outputs, and the sum of products. So each one of these columns down here, these things, each one of those columns is one of these outputs. So the first bit here is your n carryout, the second bit here is your a equals b, and the idea is that the n terms are all the ones or together and these are your inputs. The dashes or don't cares so in this particular case n carryout consists of this one input needs to be zero or this other input needs to be zero and you know if you look at this gate right over here well that's exactly what it is, this one input is zero, this other input is zero or them together that's your output. So I wrote a parser for this PLA right and again the PLA file only represents sum of products that's it. Let's see do I have another one? Okay so this is a special PLA file that I wrote and I added this special function called .xor which basically says this is not a sum of products this is an xor and basically what I did was I said okay well the xor is basically the one in this column and these are the two inputs that's all you get because that's all I ever needed. So now I have PLA files and I'll talk about converting n my gen into the PLA files in a moment so now you have a bunch of PLA files and we can look over here to see how we can actually layer these so you've got a bunch of inputs and then you have an and or a layer that's your sum of products then the next layer is is optionally a bunch of ands but basically the xor so you can get the outputs of the previous layer and also any inputs and then you just basically layer them until you reach the outputs and then you are done. So I wrote a program that takes in all of these PLA files and basically uses the Fuse database that White Quark has published in the GitHub which I will if I can remember have a link to below and basically converts it to an entire Fuse map that I can then burn onto the chip using a JTAG programmer. So now the question is well okay so how do you get from n my gen to the PLA file so let's open up the code again and go to I'm having a bunch of glare on the screen okay that's a little better ic.py okay so let's go to here so we can see see here that this is and or layer one so here are the inputs these are just the chips inputs or most of them and basically this is the logic of the first layer okay and then I have this method called toRTL it doesn't do any formal verification all it does is elaborate the module and convert it to RTL okay once it's in RTL format how do we get it into PLA format so let's see if I can show that I'll up a window here we go so let's go to MNTF um so basically what I do is um risk five reboot so what I do is I run okay so what have I got as the main for this file right now okay I've got and or a layer three that's fine we'll do and or layer three so what I do is I run ic.py in RTL mode um and what that does is it gives me this top level .il file so the first thing that you do the first thing that you do is you run it through um what do you do you run it through osis with this command line minus p synth minus o and then a bliff file which I think stands for block level information file or something like that and you give it top level top level .il so it goes ahead and it does something um again I'm not really sure what the bliff file has in it but if you look at it it has something to do with the logic okay so there's there's some stuff in there the next thing that you do is you run osis abc and what you do is you do read read bliff so you read the bliff file 181l3 dot bliff and then you call collapse what collapse does is it turns it into a sum of products and then you write PLA um I'm just going to write a dot PLA and then you can exit or you can quit okay so if we look at a dot PLA well that's the PLA file that we saw before so the other uh the XOR layers um I just you know wrote it myself because it's you can see that the format is pretty straightforward um there's also an output layer so if we look at 181 out dot PLA what I did was I said okay let's just define this this parameter called dot outputs that basically says all of these output blocks those are the output of the chip those are the outputs of the chip and that's it so I wrote a python program to basically read all these files in um and convert them to a fuse map um the way you convert it into a fuse map is that there's a utility that white quirk wrote that will take a template file which is essentially a blank file for an ATF 1502 chip it's a blank fuse file um and then you basically say you know set this fuse set that fuse and it's uh it's nice because uh it's symbolic so you can say you know set this fuse name or this macro cells feature to that setting um and basically my python program just outputs those settings those set commands um the result is a file that you can then program using jtag um and that's it now I haven't actually done that yet but uh that's that's the next stage um so so with that um what I decided to do is to take the 181 and convert it into a cpld and I also want to take the 688 and convert it into a cpld as well and then I can just pop that into the circuit instead of you know doing this this crazy stuff that I've been doing that probably won't work anyway um yeah and that's really all I wanted to talk about today so like I said a bit of a short video you know not much live programming or live schematics or anything like that but um this is a uh a decision that I've made and uh that's uh what's going to happen uh going forward now hopefully uh by next week I will have all the hardware that I need to actually program one of these cpld's and test it uh so we can see that it is actually doing uh either the alu functionality or the uh the uh comparison functionality and then we can use those in our schematic so I guess that's it for now um thanks for watching and I hope to see you all next week bye