 So, we continue our discussion on SOI MOSFET that is silicon on insulator MOSFET. We have already discussed how to realize the SOI wafers. We have also discussed what are the merits of SOI MOSFETs in as a discrete device or as a CMOS circuit. So, all the advantages we have discussed last time. Now, we will see how this device functions differently or how is it different from the classical MOSFET. So, this is the cross section of the SOI MOSFET. The top portion is actually the conventional structure except that you have the gate only in this portion junction only here. So, source channel drain and the gate oxide then the gate metal or doped silicon. Now, in the case of SOI MOSFET you have got the buried oxide or back oxide. We can call it as such back oxide and the substrate on which you have this oxide is grown the device is fabricated. I have shown this thing here the substrate it will be usually thick to hold the device there. So, you can see that I just to see the terminology is you can use it as a dual gate double gate front gate with the front gate oxide thickness T oxide f instead of T oxide you have the T oxide f back gate and the back oxide with the substrate acting at the gate region and back oxide is or T ox B. Here I have shown it differently we will do the analysis for different thickness of oxide, but ultimately you want to have double gate MOSFET where it is symmetrical that sort of thing will final decision will be having on that if possible to in this lecture or subsequently. Now, symmetrical double gate there is a DG double gate is DG MOSFETs G 1 G 2 are identical materials and T ox f is equal to T ox B. Now, there are another class of devices you call this is a double gate MOSFET it can be symmetrical or non-symmetrical the way I have put it it is not symmetrical. Now, undoped to this layer channel region can be doped or even you will see that we can even have it undoped. So, undoped ultra-thin body MOSFETs that is U T B MOSFETs will have T silicon that is the thickness of the silicon layer T silicon which is 1 to 10 nanometer that is the ultimate. Now, what we will see will be how to go about looking analyzing this how to understand the performance of this. You can have basically two types of SOI MOSFETs one is partially depleted SOI MOSFET other one is fully depleted SOI MOSFET. Lot of material on SOI MOSFET is available in a single book authored by Collinge silicon on insulator technology materials to VLSI. Cluer publication 1991 first edition, 1997 second edition lot of basic materials are there. What I discuss will cover some portion from there some portion from the papers which are which appeared. So, now let us see what is partially depleted and fully depleted do not be overwhelmed by this particular diagram. It is this portion see this is the same double gate what I have shown top gate front gate voltage V G F we can apply back gate is substrate V G B we can apply your front gate oxide. Then between the front gate oxide and back gate oxide you have got the silicon the whole thing is silicon. You can see the N plus layer is there source going from between the front gate oxide and back gate oxide similarly drain is there. Now what we are talking consider now is the partially depleted MOSFET means if you take the bulk MOSFET you have the only the front gate front gate oxide and the entire substrate the substrate is depleted. How much is the depletion layer width depends upon the doping level. So, at threshold the depletion layer width is maximum. Now we are considering a when will it be partially depleted or fully depleted. In the case of bulk MOSFET it is always partially depleted only one channel. For example, if I cover this portion below this line that is actually the conventional MOSFET where when I applied sufficient voltage this channel will invert there is there is inversion below the inversion layer there is a depletion layer. And the depletion layer width depends upon the surface potential. When the front channel let us forget about back channel when the front channel is inverted the surface potential is twice Y F and that depends upon the doping concentration. So, phi F is K T into logarithm of N A by N I. So, higher the doping more will be phi F. To give an example when the doping is 10 to power 16 phi F is 0.35 volts and that will give maximum depletion layer corresponding to that is given by this relationship. We have already discussed entities that I have calculated and put it is about 0.3 microns. Why I brought this number is supposing the thickness of this soil layer is 1 micron. When I apply gate voltage to the front gate when the front channel is inverted depletion layer width will be 0.3 microns. So, if this is 1 micron thickness entire layer below that will not be depleted. That means channel this whole thing is channel T silicon which is shifted down here. T silicon is that thickness T silicon is only partially depleted when it is inverted. So, below this layer there is no depletion layer, but now I use this back gate also to deplete from the back side and invert the back channel. So, what you have shown is this portion is 60 maximum depleted due to front gate. This portion is 60 maximum depleted by the application of back gate. That means at a T maximum you will have an inversion layer here and inversion layer on the top, but now you can see there is no difference between the bulk MOSFET and this. You have got one MOSFET on the top, you have got another MOSFET on the back. It is like putting two MOSFETs in parallel. There is no coupling between this region and this region. They are isolated. That is partially depleted. So, in this example if the T silicon is total from this layer is 1 micron, the top depletion layer will be 0.3, bottom depletion layer will be 0.3 and you will have 0.4 micron thickness undepleted. So, this is a partially depleted case. So, basic device equations for a partially depleted that is PD, SOM MOSFETs are same as that of bulk devices. There is no difference. So, we do not have to discuss any more. So, this is not used very often except that you can still use it for radiation hardware devices. It may not be, you can have two channels and the device is isolated from substrate fully. That sort of thing is used, but this is not a very popular device today for ICs. Two inverted channels can exist in parallel, but remember these numbers, 10 to the power of 16, 5 to the power of 0.35, depleted depletion layer with maximum 0.3 microns. So, T silicon is 1 micron which is greater than twice the XT maximum. So, it is a double gate operation. So, in that case when the double gate operation is there, if T silicon is more than twice the depletion layer width, it is partially depleted. If it is single gate that is there is no back gate, then T silicon should be greater than XT maximum, then that is partially depleted. The idea is clear. Fully depleted device, it has removed all these, no material is there, but there is a depleted layer to show that I put this diagram like this here. So, you can see here front gate and back gate. So, if I take same 1 micron thickness, of the SOI layer and if I use instead of 10 to the power of 15, 10 to the power of 14 doping per centimeter clove, P type doping, then phi f corresponding to that is 0.458. I am sorry that is twice phi f. See let us remember phi f here was 0.35 and doping is lower, phi f will be smaller. So, what I have here is twice phi f. You have to correct it. It is not phi f, twice phi f. Phi f is this divided by 2. So, twice phi f is 0.458. So, corresponding to twice phi f that depleted layer width is 2.465 because go back to that one. Twice phi f is lower, but n a is lower by 100 times. Twice phi f in 10 to the power of 16 cases is 0.7 volts. 10 to the power of 14 cases is 0.45 volts. Not much different, but this doping is reduced by factor of 100. So, depletion layer width will be more by factor of about 10. So, you can see that the extreme maximum here is 2.46 micrometer. If there is a thick as silicon layer, silicon depletion layer will be 2.46 as compared to 0.3 micron is 10 to the power of 16 cases. So, now what we say is if the thickness of the channel is 1 micron, the entire layer will be depleted. It will go beyond that. Even if you have this thickness of channel is 2.46 micrometer, when it is inverted, the whole thing will be depleted. So, the thickness is less than 2.46 micron. It is definitely inverted. Both front and back channels can be inverted. What happens in between? We will see some of the analysis. So, that means the case is different from that of bulk MOSFET. You have got the entire layer depleted. You have got the front channel inverted, back channel inverted. In fact, you will see that if you change the front channel potential, it will change both front channels into the potential and back channel potential. In other words, you will see that there is coupling between the front gate and the back gate, because there is no charge here. Oxide depleted layer oxide. So, whole thing is coupled. If I change the whole thing between the two, the field between the two will change. So, that is the meaning of coupling. We will understand more about that later on. Now, let us go back to the 10 to power 15 case. Can I make a fully depleted SOI MOSFET in 10 to power 15 doping? HT maximum is 0.3 micron. Suppose, here I make this thickness of the SOI layer 0.1 micron. It is a fully depleted case. So, if I go to thinner and thinner layer, I can use slightly higher doping. Now, this is the idea of fully depleted and partially depleted. This operation of this is different from the bulk MOSFET, whereas partially depleted is same as the bulk MOSFET. So, we need not go into discussion of that. We will get down to discussion on the fully depleted SOI MOSFET. Let us take a look at that. This is a diagram, which tells you the energy band diagram. All of you are familiar about energy band diagram. This is the bulk MOSFET. Bulk MOSFET put upside that way, gate, oxide, substrate. So, all that is put like that. So, gate is there, oxide, shaded region is oxide. This is the depleted region. You can see the depleted region, band gap, energy band diagram bends upwards because the field is in that direction. So, you have got below the depletion layer, there is no band bending. There is no band bending. There is no voltage drop. The entire voltage drop is across this depletion layer. So, this is the band diagram of the bulk MOSFET. And if I draw the intrinsic level, that will come from here like that. Intrinsic level will be below the permeable that will be inverted. Now, let us take the partially depleted SOI MOSFET. So, this is the MOSFET now. I put it like that. Front gate, front gate oxide, silicon, back gate oxide, back gate. So, you have got partially depleted. This is oxide. This is the depletion layer. So, please remember wherever depletion layer which is there or wherever depletion layer is present, the band bending takes place plus to minus. Now, this is the region which is not depleted. To go back, we are coming from here to here. Depleted, no depletion. Depleted from backside. Depleted, no depletion. Depleted because of applied voltage plus here. So, field is in that direction here. Here, the field is in this direction. The band diagram is like this. Now, let us say supposing this portion is removed. That means, I have made the thickness equal to sum of this and this. This is removed. So, you put them together. No depletion. I am sorry, no undepleted portion. Fully depleted. So, this goes up like this. This goes up like this. And the electric field here will be 0. See, if you go here, l g band diagram is flat. Electric field is 0. From here out it is 0. Merge them together. Up to this point, the electric field is in that direction. Belong to the front gate. And from this side onwards, from this back, right side to the left hand side, electric field is towards the left side. So, energy band diagram bends up. Where they meet? Where the two depletion are meet? Here, field is in that direction. Here, the field is in that direction. There, the 0 field is there. And where is the 0 field is there? There is a potential minimum. Comes down. Minimum increases that way. More about this we will see as we go further on this discussion. So, this is the energy band diagram of power. Fully depleted SOF MOSFET. This will be inverted if this potential is twice SOF. This will be inverted actually if that potential is twice SOF. Notice also, you are applying that voltage with respect to this source region. Here, after the analysis becomes slightly different, slightly different marginally, but you will have to be careful in looking at the entire situation. So, this is again the diagram of the SOF MOSFET. Now, these have shown this back oxide, T oxide B thicker compared to a T oxide F, not symmetrical. Symmetrical case, they will be equal. And this is the T silicon, T S, we call it in the notation. And this is the T oxide F source range. We are now talking of fully depleted MOSFET, no more partially depleted. So, you can have in this case several type of operations. One, you want to have MOSFET operation, there must be at least one channel inverted, so that electrons in the N channel device electrons are created and you can transport it here like this. So, one case is front channel inverted and back channel can be accumulated. You can have the entire layer depleted, but still you can have, how do you accumulate the back channel? Apply negative voltage to the gate. So, if you take a MOSCAP p-tap substrate, apply plus voltage to the gate, you will deplete. It keep on increasing plus voltage, it will be inverting. Suppose, you apply negative voltage to the gate with respect to the substrate or the source, plus charge will accumulate, it is accumulation. So, I can have accumulation layer here on the back channel by applying a large minus voltage to the gate, back gate. But at the same time, I can invert this front gate by applying plus voltage to the front gate. You can see the flexibility that you get. That is one operation. This is only more for academic interest understanding purpose. In some cases, they use it in some special applications. Otherwise, it is very rarely used, but you may come across such situations when you make use of it for an integrated circuit sometimes. Second case is front channel is inverted. Apply a plus voltage large enough, so that you can invert. How much is the voltage that you must apply to the front gate to invert depends upon what is the condition on the back channel. That also we will see. See the bulk mass set, your threshold voltage is decided once the doping is fixed and the oxide thickness is fixed. Now, here another parameter, you can control the threshold voltage by using a back gate. You can do that also in the bulk mass set. Back gate bias can change, but that will only increase the threshold voltage, reverse bias if you put. If you cannot apply plus voltage to go to the back gate, because then there will be follow bias across the junction. So, you can only increase the threshold voltage. You can control the threshold voltage some extent marginally. Here, there is an oxide. You can apply plus minus without hurting this junction. So, if you apply minus here, inversion. If I apply plus here, depletion. So, front channel can be inverted with back channel depleted. Second case, third case is I apply sufficient plus voltage to the front gate, sufficient plus voltage to the back gate, so that both channels are inverted. So, front channel inverted, back channel inverted. Now, you can see when you have both channels inverted, you can draw a line at the center. You can say half of the top portion of the silicon is and the depletion layer there belongs to front gate. It is not shared between the two, both are inverted and half of the layer below this middle line here, that is belonging to the back gate. So, whatever depletion layer charge is there, it belonging to front gate there or if T silicon, T silicon, total charge per centimeter square is Q N A into T S. So, Q N A T S by 2 will belong to the top gate, other charge will belong to per centimeter square will belong to the back gate. There is another class of devices, which is more soft dedicated version or another version of this third version, that is volume inversion. Ultrathin body, U T B is ultrathin body, double gate S Y MOSFET. So, today we talk of ultimately ultrathin body and in this analysis, unlike in the bulk make MOSFET, you will talk of T ox C oxide. C ox is capacitance per centimeter square for gate oxide. Here, you will have talk of front gate oxides C ox F, which is epsilon oxide into epsilon 0 of course, divided by T ox F, that is per centimeter square. And you can also talk of C T silicon, what is T silicon? If the entire silicon layer is depleted, the capacitance corresponding to that layer, silicon layer, that is C silicon is epsilon silicon into epsilon 0 divided by T silicon. Instead of oxide, you have got that silicon permittivity, silicon thickness. You can talk of that, that is when it is fully depleted, when it is fully depleted, you can look into it as a capacitor. When you go to sub threshold slope, you will see that that capacitance complete temperature, that is why I just brought in here. C ox B. Now, when you go into the analysis of this structure, what we will do with B? We will assume that this P plus, P layer is P plus. That is the stability, so that whatever voltage I apply is available here. To simplify, it will modify it only marginally with a small drop in the substrate, if the doping is present there. So, when you go to double it, it is in fact, the situation will be, that will be held up, this will also be held up. So, we consider that case to avoid more complication. In other words, you can say this is a metal here, this is a metal there, there is no drop here in the silicon. Now, let us take a look at how to, what we are interested in is, what are the operational modes and what are threshold voltages. Once you know the threshold voltage, you can use the MOSFET equation, same equation you can use to describe the MOSFET current, transconductance. So, the entire analysis is hovering around the threshold voltage. You can do the same equation, you see ox A W L P G minus V threshold whole square or W Q into V into V into V into V into V, that is the ultimate equation, velocity into charge into W and Q depends on what is the threshold voltages and what is the gate voltages. So, now, just before we go into that, you can see that this is bit more complicated structure than the other one. Notice, when you apply gate voltage in the bulk MOSFET, what happens and how it will be? The bulk MOSFET, I am going to be slow here because slightly different from the concept there. Gate, black, oxide, depletion layer width, when a plus voltage and of course, inversion is there. Now, here how did you recall, how did we find out the threshold voltage? Is that at threshold voltage V G equal to V T N and V G gets shared between the oxide and the silicon and in silicon, it is shared between the, it is part of a depletion layer. So, at threshold voltage V silicon is twice fair, the drop. So, depletion layer corresponding to that is Q depletion by, I am sorry, oxide drop. To make it very clear, gate voltage is shared between the oxide and silicon and at threshold voltage, what is the silicon drop? Phi phi f, that is very clear. And once, phi phi f is the drop in silicon, you know how much is the depletion layer width from this formula. So, it is phi phi f, so depletion layer is this much. Once you know what is the depletion layer width, you can find out what is the, what is the voltage drop across the oxides, that is this one. Charge in the depletion layer width is Q N A into X T maximum divided by that, divided by C oxide is the voltage. So, what we did was, V silicon is twice fair, corresponding to that X T maximum is given by this formula, corresponding to that, you know Q D is that much per centimeter square. Q D by C oxide is the voltage drop X of oxide. Take a capacitor, charge on the other side of the capacitor is Q D minus Q D. Q D by C oxide is the voltage of X of oxide. This is how we did the calculations. So, how did you arrive at that? I am doing that, because you may have multiple layers beyond this point. If you have multiple layers beyond that point, you may not be able to easily compute this. Here, you know once is drop across silicon is twice fair, you know depletion layer width, you know charge. Charge by C oxide is the voltage of a cross oxide. Now, look at the other way. What is the charge related to, how is the charge related to the field and the surface? If you apply Gauss law to this surface, top of the silicon surface, you apply Gauss law. It is part of the infinite surface. So, you apply Gauss law to that portion per centimeter square, part of that per centimeter square, charge is Q N A X T maximum. Charge divided by epsilon s is field Gauss law. The field lines permeating on the surface is charge beyond the surface divided by epsilon s. Epsilon r epsilon 0, that I have put in epsilon s. So, you took that once centimeter square of the sphere, then you say the electric field is that much. So, what we are telling is, the Q D by epsilon s is electric field in silicon. Now, from the continuity of flux, if you take, I do not know whether you have studied electromagnetic field, you must have studied or basic electrostatics. If I have studied, here look at this. I have oxide here, I have silicon here. Electric field here and here will be different. What is continuous is a flux, del dot d into d of s is constant or the flux is epsilon s into epsilon. So, here epsilon s is, epsilon s is the field in silicon is E s and epsilon s is the permutivity. So, epsilon s into E of s should be equal to epsilon oxide into E oxide. That is the continuity of flux. This is a D, D is epsilon into E. D in silicon is D in oxide. Sorry, D in silicon is D in oxide. So, now you can see, I have drawn the electric field diagram here. E oxide is higher than in the silicon. If I know E oxide, I know voltage of across oxide. See, I am just trying to get this relationship slightly differently, because you may not have that replacement derivative precisely, but you can find out. If you can find out the free peak field on the surface, you can find out the voltage of across oxide, because if I know the peak field E of s in silicon, I know the oxide drop, oxide field from this relationship continuity of flux. Now, if I know the oxide drop field, I know what is the voltage of across oxide is. It is exactly a derivative actually. I am just recalling that. So, E oxide into T oxide will be the oxide drop. E oxide is from this relationship epsilon s E of s divided by E oxide is epsilon oxide is that. This is a flux in silicon divided by permittivity in the oxide gives me the flux in the oxide, electric flux, electric field. Flux is product of the two. If I divide by this, I get electric field in oxide. That into T oxide gives me a voltage drop. So, what is this quantity E of s into epsilon s here? E of s is Q d by epsilon s charge beyond that surface. Whatever charge is there, divide epsilon s is the peak field. So, E of s into epsilon s was the charge here. That is the charge. So, same relationship you got differently. Why I derived that is, if you want to find the voltage pressure voltage, all that you have to do is, what is the voltage at a pressure across oxide when the surface potential is twice y f. So, potential near the surface is twice y f. You can find the voltage drop across oxide by knowing the field near the surface of silicon. That is because epsilon s into E of s actually is the charge beyond that point. Whatever is the number of layers divided by C oxide will give the oxide. I think it is, when you go through this, once more you will actually see. So, by doing this, I have shown that what you write here is the same as this. It is writing Q d. I wrote it as, I showed that it is equal to, Q d is equal to whatever charge beyond that point. It does not be depletion layer. Epsilon s, that is, permittivity of the material layer, silicon into the silicon field at the surface. That is what we get now here. Threshold voltage is twice y f plus this. So, if you go to the same aspect, all that you have to do is, if I want to find out threshold voltage of this type of structure, all that I have to do is, at threshold voltage of front gate, I know that the potential here is twice y f. So, I say potential twice y f. That is the condition for immersion. Why is twice y f? And if I can find out the field on the surface multiplied by permittivity divided by C oxide, I get the oxide drop. That is all what we are doing. It is as simple as that. We are trying to find out where assuming twice y f is the potential there. So, gate voltage is twice y f with respect to ground. So, potential here with respect to ground is twice y f. Beyond that, only the gate to oxide drop is there. That is just epsilon s into E of s divided by C oxide f. If I forget to say, I have assumed that it is at oxide. Now, let us take a look at it a bit more. It is a bit slow on this. So, this is the case of bulk MOSFET on the left hand side. Take a look at those figures now. This diagram I have drawn already in the previous page. This is oxide. There is a gate. This is silicon. This is no-tone. So, putting all like this, I put it like that. Gate, oxide, silicon, bulk. So, in silicon, because it is informally doped, electric field will always be linear. We have seen it number of times. So, this is the extreme maximum. At inversion, we are considering threshold voltage. So, we are considering a situation where there is inversion. That means, we are considering a situation where the surface potential, that is potential of the surface of the silicon is twice phi f. I think in the previous series of lectures, you would have called that twice phi b. If it is called, sometime people call twice phi b, I call it twice phi f. Both are same. So, you have the potential as phi f s. Electric field is linear and integral of that will give a parabolic term. So, voltage drop in silicon will be decaying like this parabolicly. That is going back to basics. And the potential is continuous. In the silicon, in the oxide, there is voltage drop. Electric field is constant, but there are no charges. If the electric field is constant, the potential is integral of that, linear. So, you can see that voltage rises in a parabolic manner in silicon, bulk MOSFET, then it is linear. Electric field rises linearly and it is constant. There is no charge. In between, there is no charge. Here, it is linear because as you go from here to here, the charge keeps on increasing because depletion layer. The charge from here to here is, if you start 0 from here, I am sorry, you charge 0 from here, this end. As you go, the charge is going on increasing and voltage is going down to 0. So, let me, without going into that, linear becomes parabolic and constant becomes linear there. And you see here, the oxide is higher than the silicon here because of the difference in the permittivity. Lower permittivity is the factor of 3. So, this oxide is 3 times this quantity. Now, let me now go to a better example. A bit more involved with situation, SOI MOSFET with the back channel accumulated. Front gate oxide, back gate oxide. These colored portions are oxide. This is the T-silicon. What you are telling is, we are talking of fully depleted case. That means, by the time it has inverted, the entire silicon layer is depleted. But if I start with the back gate bias VGB negative, see this diagram, this full line here shows the potential. When I apply a voltage across this VGB, back gate, just go back to this. I will show you. See here, when you apply VGB, you may be wondering with respect to what you are applying there. You are applying with respect to this one point or some point somewhere in the silicon, somewhere outside. There is a neutral point. With respect to that, you are applying. In the case of MOSFET, also you are applying a voltage with respect to the gate to the source. Source is connected to the substrate. Here also, the similar thing situation you can have. So, when I apply voltage here, negative with respect to that, this will be accumulated. Back gate is made negative with respect to ground. That means, this channel will be having plus charges. P becomes more P plus. It is accumulated. Now, the potential here corresponding to that will be how much? In an accumulation layer, see in a depleted layer, because of a depleted layer and band bending, you get charges sufficiently. You get a region over which charges spread. And the potential can be 0.1 volts, 0.2 volts, 0.3 volts or even 0.5 volts depletion layer drop. For example, when you take 10 to power 16 doping, you have got twice 5 is 0.7 volts. That means, voltage drop is 0.7 volts. Now, when you have accumulation layer there, you can accumulate the charges with very small voltage surface potential. So, the potential of this region with respect to the substrate will be very small, plus here, minus here, plus there. In other words, you will have a charge sheet with very little drop in silicon. So, the assumption here again would be that it is a charge sheet with no drop across that charge sheet. Like what you do in the case of inversion, you take the inversion layer, you do not transfer a drop across that, because charge is large. So, here you can say that plus charges are there, which is actually decided how much you have voltage applied and how much is the back gate thickness. So, if you take the back gate here, you will have a field in the direction, plus here, minus here. But the voltage here will be 0, because if you have a large plus charge there, that can come with very small voltage across, voltage in silicon, because after all the charge is exponentially related to whatever background charge is there. Whole concentration is 10 to the power 16 into e to the power of 5 by B T. So, let us say 5 is, even if it is 2 millivolts, e to the power of 5 by B T will raise this particular carrier concentration from 10 to the power of 16 to double that value very easily. 25 millivolts if you take, e to the power of 25 millivolts by 25 millivolts, 2.27. So, if doping it 10 to the power of 16, 10 to the power of 16 into e to the power of 1, 2.27 times 10 to the power of 15. So, carrier concentration is very large there. So, at that voltage that surface potential there is just 2 millivolts, 25 millivolts. So, what we are telling is by applying 90 voltage, the entire voltage will drop across this particular region and the potential of the surface will be raised with respect to the source by very small quantity, 25 millivolts, 30 millivolts of that order. So, we are neglecting that and seeing the potential is 0. We can take into account, you will see that even the analysis will still hold good. So, I am neglecting that voltage surface potential, taking it as 0. That is what I put here, psi S B is 0. So, when you do the entire analysis, you will see that if you want to consider back channel accumulated, you can put psi S B equal to 0. Front channel inverted, you will put psi S F, psi S F is equal to twice by M. This is understanding that with which we are doing the analysis. See more simplification, but holds good quite a bit. So, if I draw the electric field here, I fix the voltage as V G B, there will be electric field like this. Then we charge here plus charge here, minus charge here. This plus charge can be very large because doping is not there and this will be negative charge. Now, when you started with that bias fixed, we are not varying that voltage, we are not varying the field. When I apply voltage to the front gate, what happens in the initially? I am applying it with respect to substrate, that is with respect to source. So, applied voltage exactly in this case, I am sorry, exactly like this, it will start appearing, you know, if it is not depleted fully and the voltage is very low, some voltage appears across the oxide, some voltage across the silicon. So, you will have initially, there will be depletion layer starting from 0 here. Entire layer is not depleted initially, there is 0 potential here. Depletion layer will start widening and at one point, the depletion layer will come and merge here. That is the dotted line. The dotted line is the situation when the depletion layer from front side has, from the front side has widened and ultimately merged with this point. Where was the negative charge come from at the time? From the depleted portion. When I apply plus voltage to the gate, there is no charge here. Negative charge come from this substrate as the depletion layer widens because of more and more plus charges at the front gate, more and more negative charges from the substrate, more and more widening of the depletion layer. At a particular point, you can call it as the punch through voltage, where the depletion layer is completely merged with this point. That is the depletion distribution there. Similar to this, but this field will be much smaller than that because this bit was large, 1 micron, let us see and that is not depleted. This is, if it is 10 to power 16, this let us say 0.2 micron. It has depleted fully, but if it is point, if it is 10 to power 16 doping and if this width is 0.1 micron, surface potential is not by 5. When this has depleted here, just go back to that graph and show you. Here, here itself we can see. If it is 10 to power 16, surface potential will become twice higher if the depletion layer width has become 0.3 microns. Now, if I cut it from here and keep it only 0.1 micron, it whole thing would be lowered like this. So, that is you have got the edge of the depletion layer here, potential is much lower than that. All that you have to do is pull this side down, so that field is lower. So, when the depletion layer is not 0.3 micron, the voltage of a cross silicon is not twice higher, it is less than that. So, that is the situation here. It is not twice higher and oxide drop is actually corresponding to this peak field. You have got the oxide drop, which is lower than that. You have to follow very carefully, because this is bit slightly different from what we usually discuss. Now, at this point, whatever plus charge was available was coming from this negative charge here, depletion layer. Beyond that, if I increase the voltage, plus charge I put here, the minus charge will come from, where can it come from? It can come from the other end. So, what happens is, the field lines from here rise parallelly. I wish I had another diagram here. See, at this point, electric field is something maximum here. Here, it is 0. Now, if I increase the electric field at this point, that is 100 lines increase from here to here. That is it. All the 100 lines do not find the negative charge here. It will have to go to the other end of the gate, where there is negative supply is there. So, the extra 100 lines, all of them will cross this. Over simplification the electric field has increased from here to here by some delta E. The delta E is 100 lines. All the 100 lines, delta E will cross this. That means, 100 lines which are extra crossing here will cross this also. That means, the electric field will increase from here to here by delta E. So, what we are telling is, this distribution is not going to change, where there are no charges to terminate. See, electric field distribution, if I see electric field will go up here, if there are charges here, but there are no charges here. So, whatever extra charge is coming here will cross here. So, the entire field line will go up here, it will like this parallel. That is the meaning of drawing this line mean. There are no charges in between. All the charges will come from here. So, what will be the voltage distribution? Voltage here is not changing. Why? Is your held voltage constant by the back gate? That is remaining same thing. But this field is remaining same thing as before. It is not changing. But what has happened is, the plus charges here have reduced because the negative charges, let us say there are 1000 lines here originally, out of which now here it is only 1000 charges, if there are field lines are constant. Now, when these extra 100 field lines come here, this has not changed. That is because the field lines which are coming, 100 lines coming here, remove those plus charges because they are coming from here now. So, you have got that extra 100 lines coming from here. There is no need of that plus 1000 charges. There will be only 900 charges. I am giving the numerical number because 1000 charges here, 900 charges here, 100 charges coming extra from there. Charge you tells is maintained. So, this field is not changing. This voltage drop is not changing, but field lines have moved up here. So, the distribution now will be this potential is 0 here. Why? There are plus charges here with very small potential here. That is this till the accumulation here is maintained. So, long as there are plus charges here, accumulated charges are there, where are the plus charges coming from? They are accumulated. So, long as there are plus charges are present, the potential is 0. If I go on increasing that, if the plus charges disappear, then it will start depleting, but there are plus charges at 0. So, from here to here is what is the potential here? We are considering situation where it is inverted twice y of. So, now we know the potential in the silicon, which is less than this 0.3 microns. Now, it is 0.1 micron. The potential drop across silicon is more is twice y of, but the length over which the potential drops is smaller. So, evidently we will see that the field here will be higher. So, that aspect you can see from here, corresponding this field here will be higher, field here will be higher. So, this is a serve MOSFET in the back channel accumulated. We will discuss about the voltage calculation in the next presentation, but this is a crucial thing to understand. We can before you go to the next lecture, we can go through this once more and you will see appreciate that lecture, next lecture after seeing this only, again going through this. So, is the accumulation condition, but here the field will be higher, surface potential is twice y of. Now, let us see the other condition. I will finish these two before we wind up for today. Back channel grounded, see in this case, back channel accumulated by applying voltage. This is slightly simpler. I should take this first. In a complicated thing, finish first, go to simpler things afterwards. Here, I have grounded this, connected back channel to ground. No voltage applied. So, as I start applying from voltage from the back gate, Dipliesion layer keeps on moving. Forget about the solid line, observe the dotted line. That is the situation when the Dipliesion layer has completely depleted this channel. Initially, Dipliesion layer will be narrow. It will keep on widening and come up to this point. Just I will go to one slide. It will be clearer to you here, for example. I have grounded this point, let us say. I keep on increasing this voltage. Then, you will have the Dipliesion layer, which will be narrow initially. Higher voltage is widened. This is the electric field. Widen the electric field like that. That is the situation. Here, I have plotted the dotted line where the Dipliesion layer has just reached this point. No rolls from the back gate. You have grounded that. So, you can calculate what is the applied voltage is. At this point, what is the electric field here? Q N A into T silicon is the charge divided by epsilon silicon is the electric field here. From that, you can find out this one. That is, in this case, you can straight away see Q N A T of S is the charge. You have C oxide is the voltage of across oxide. Now, once it is depleted just here, beyond that, I increase this gate voltage. So, remember this is grounded. So, applied voltage now shares between this oxide, this silicon and this. Once it is just depleted fully, if this were silicon, what would happen? The Dipliesion layer would have moved further down. But now, again the same number. I have increased the voltage so much that the surface potential with respect to ground becomes twice twice. This is 0. There is a potential drop here. There is a potential drop here. There is a potential drop. Just when it is punched through, there is drop across oxide and silicon. When I increase to beyond that point, at inversion, there will be drop here, drop here, drop here. And across the front oxide, it is linear drop because there is no charge. Across this is parabolic because charge is constant across this linear drop. But this is 0. So, there is a rise of potential and the potential is psi S B and this psi S F. So, if you look into the electric field then, psi S B minus 0, that is the eox B. And front oxide is gate voltage that is applied is threshold voltage minus twice that is the oxide. How much voltage I have to find? How much is the electric field here? I can find out or voltage drop I can find out if I find out the surface field. So, if you want to calculate the threshold voltage of this device, all that I have to find out is how much is psi S F? How much is the electric field here when this potential becomes psi S F? That calculation we will see next time. So, what will you say about the field here compared to the previous case? Previous case, the drop across the silicon was twice psi F because this is 0, this twice psi F. In this case, drop across silicon, same silicon thickness, 0.2 micron is twice psi F minus psi S B. So, the field here is smaller compared to this. Now, let us once again go back to this. Compare the situation here. Twice psi F dropped across 0.3 microns. That was the replacement area width. Now, this thickness is smaller, but the voltage drop across that is much smaller. Twice psi F minus psi S B. This can be as close as to that. So, the field here will be smaller. See, why I am pointing out this field is, we had said that in the bulk MOSFET, the mobility is affected by doping. The mobility is affected by the field in the vertical direction. So, vertical direction in this case is like this, from the gate down to the channel. So, you can see that in this case because of the difference in the voltage drop across the vertical direction is less, the field in the vertical direction will be less than the case of bulk MOSFET. So, we can see this. Already, there is a pointer telling you that if I use a server MOSFET, the vertical electric field can be reduced. We have to go back later on C, where we can reduce the doping concentration. Also, we have to see. So, this is the situation. Now, let us take the other case, where back channel also is inverted. When the back channel is inverted, what is the potential there? Means, I applied sufficient voltage at the back gate. So, that is twice way up. I applied sufficient voltage at the front gate, that is twice way up. So, electric field lines will be terminating here to 0. Part of this belonging to top channel, part of this belonging to the back gate. So, electric field lines will come in this direction, left to right and on the right hand side, electric field lines will be coming from right to left. So, it is actually extension of this. I have already biased with the gate bias for the differential layer with this here, let us say. So, you have the, just when it is whole thing is depleted, you will have this situation. I will think I will discuss this in the next lecture. What we have seen here is, if both channels are inverted, both potential will be twice way up. So, what is the drop across the channel? That is, difference in the potential is 0. So, drop is low here in this case. Field is low. So, what we are trying to point out here is, in the case of a soy MOSPET, you can have a situation where the both channels are inverted and the vertical electric field will be smaller. If the electric field is small here, electric field is small in oxide also. You can have that type of situation. Actual threshold table will discuss in the next lecture.