 Hello and welcome to the series of video lectures on the subject digital techniques for secondary IT students. I am Dr. Rishal Gajbar and in this video lecture we are going to implement half-adductor circuit by using verilog hdl language. At the end of this session you will be able to implement half-adductor circuit module by using verilog hdl. You will also be able to write test bench in verilog to verify the correctness of the written module. The software that we are going to use for the simulation purpose is model sim student edition. You can download this software by using this link which is provided here. It's a free of cost software so you can download this install on your computer and you can simulate the verilog programs very easily. So this will be the workflow for our session. We will first discuss the verilog module for a circuit which is half-adductor in this case. Then we will discuss the test bench which is required to simulate the verilog module which we have written and finally we will verify the simulation results in model sim software. So half-adductor is a combinational circuit that performs addition of two bits, addition of two binary bits. This circuit needs two binary inputs which are represented by using the names A and B in this case and two binary outputs sum and carry which are represented in this case by using capital S and capital C respectively. The schematic diagram here shows the half-adductor circuit and in this case you can see there are two inputs A and B and there are two outputs capital S and capital C which stand for sum and carry. This is the truth table for half-adductor circuit and in this case you can see there are two inputs A, B and two outputs S and C and in this truth table you can see the values for sum and carry for all possible input combinations and one can find from this truth table the logical expressions for the sum as well as for carry. And if one find out the logical expression you will get sum is equal to A x or operation with B whereas this carry is equals to A and operation with B. The same thing is represented here in this diagram. So S is equal to A x or operation with B whereas the C is equals to A and operation with input B. So let us discuss the verilog module for half-adductor circuit. In this case this is the module definition for half-adductor circuit. So in this module definition wherever you will see the red word that is nothing but a keyword. So all the red words are here represented by using the red color. So the module definition in verilog always start with the module keyword. So the module followed by the name of the module which is half underscore adder in this case and inside the bracket you provide the list of inputs and outputs. So it is written as A, B, S, C. Here A and B are the inputs and S and C are the outputs. In the next line we are going to explicitly define what are the inputs and what are the outputs. So basically here A, B, S and C are the identifiers. So we here explicitly represent which identifier belong to input and which identifier are the output. So here we have written input space A, B and semicolon. Also you do not forget to give the semicolon at the end of the first line. So in the next line we have written assign keyword and we have written capital S is equals to A, carrot symbol followed by B and semicolon. What this statement is doing in this case? It is performing the XOR operation between the inputs A and B and the result is assigned to the S which is some in this case. So the carrot symbol in Varylog is known as a XOR operation. So in the next line similarly we have written assign capital C is equals to A and percent symbol B and then semicolon. So what is happening in this case? Here the and operation between inputs A and B is performed and the result is assigned to capital C. So thus we have implemented the Varylog module and the Varylog module will always end with the end module keyword. So do not forget to give that also. So this is how you can write the Varylog module for half at a circuit. So let us now discuss the test bench for half at a circuit. So before explaining the test bench let me give the perspective of why we should write the test benches. It is always better to write the test benches for every module that you write in Varylog. Why? There are two reasons. The first is by using test benches you can verify the correctness of your module very easily. Secondly it also avoids the manual input for your module. So otherwise what it will require if you do not write the test benches then for every input you have to explicitly give the inputs. So that manual provision of input will be avoided if you write down the test bench. So everything in Varylog is written in terms of module. So your test bench will also be a module. So it will start with the module keyword followed by the name of the module which is test underscore half at a in this case semicolon. And here the inputs will be defined as a rake data type. And why these are defined as a rake data type because you want to provide the all possible input combinations and whenever you are providing some input combination those input combination should persist unless and until the user provides some new inputs. So that is why it is defined as a rake data type. The outputs here are defined using the wire data type and these are written as wire as a keyword followed by the list of the output names which for your module. So which are essence in this case. Next the most important part is to instantiate the module which you have written. So the module name in our case was half underscore adder. So it is like creating an object of some class. So here the module is instantiated as follows we write down the name of the module. So half underscore adder followed by the object name which is h1 in this case and in bracket you provide the list of input and outputs followed by semicolon. So it is written as a comma b comma s comma c semicolon. Next we write down the initial block. So initial block is written by using the initial keyword here and initial block has the property that whatever statement that are inside those will be executed only once. Now here what is happening there are multiple inputs. So inside the initial block because there are four input combination that we need to provide here. So since there are multiple inputs that we need to provide. So it is a convention that you should provide it within the begin and end block. So that is why it is written something like this. So initial followed by begin and end and inside that you provide all possible input combinations. And here the input combinations are provided. So first input combination is provided as a is equal to 1 represent the number of bits dash b means it is a binary and 0 it is its value. So it is a 1 bit binary number 0. So the first input combination is 0 0. Then we provide the delay it is always better to give the delay between two input combinations. So the delay here it is provided by using hash 20. So there will be a delay of 20 units and the next input combination is 0 1. The next is 1 0 and 1 1. And we end this module definition with the end module keyword. So pause the video for 1 minute and write down the answer of the given question. I hope you have written the answer. The answer here is twofold. First to test the correctness of verilog model we write the test benches and secondly we want to avoid the manual entry of input values. Now let us see the simulation results in models in software. So I have already written the program. So this is the model definition for half adder circuit and this is the test bench written for the half adder circuit. And I have named this program as a test underscore half adder dot v. Dot v is the extension that we use for saving our files. The next thing we have to do is to compile this program. So for compilation go to this symbol compile select appropriate file. So test underscore half adder dot v compile and just check whether your compile is successful or not and as you can see here there are no errors and warnings. So our compilation is successful. The next thing is to go to the library and there inside this work you will find your module. So just go to the appropriate module which is test underscore half adder in this case. So I will select that test underscore half adder. Just right click on that and select the simulate option. So a test window a simulation window will appear on your screen. Then the next step is to add the waveforms. So for that purpose go to the add to wave option select the to wave option and select the all items in region. You will see a simulation window here and here these are the inputs and outputs which will be represented as a waveform. So the you can see the first name as test underscore half adder which is your module name for your test bench followed by slash a is your input and so on. So you can see a, b, s and c. The next step is to run. For running this program just select this symbol and click here. So you can zoom this also just select this one. Now here one can see that for the inputs a and b as 0, 0. The sum is 0 as well as carry is 0. For the next input combination for that is 0, 1 you can see the sum is 1 whereas the carry is 0. In the next input combination the input a is 1 whereas the input b is 0 and in this case you get sum is equal to 1 and carry is equal to 0 whereas for the last combination you can see a is 1, a is 1, b is also 1 in this case you can see and in this case you can see the sum is 0 and the carry is equal to 1. These are the references. Thank you very much.