 Hello, and welcome to this presentation that covers the features of the STM32 Extended Interrupts and Events Controller. The EXTI controller provides up to 40 independent lines, split into two categories, configurable lines and direct lines. The applications can benefit through smarter use of low power modes, taking advantage of the capability to wake up via external communication or requests. The EXTI controller provides interrupt and event generation, as well as the capability to wake up the processor from sleep and stop modes. Configurable lines allow the user to select which active edge generates interrupts or events, with a dedicated status flag for each line. Requests on configurable lines can also be generated by software. Configurable lines are linked with external interrupts from general purpose input outputs, programmable voltage detector, real time clock, and low power timer. These lines can wake up the processor from sleep and stop modes. Internal lines provide the possibility to wake up from sleep or stop modes on internal peripheral events, with status flags provided by related peripherals. They are linked mainly with peripherals working in sleep or stop modes. As mentioned on the previous slide, configurable lines can act as a wake up source from sleep and stop modes. They provide the capability to wake up from a GPIO rising or falling edge, programmable voltage detector, real time clock, or low power timer. This slide describes the EXTI hardware workflow. To initialize a GPIO to generate an interrupt to wake up the processor from sleep mode, for example, four main blocks need to be configured. First of all, the GPIOs need to be configured in input mode. As a second step in the system configuration controller, the GPIO pin needs to be connected as an input to the EXTI controller line. The connection of the GPIO pin to the EXTI line is selected through the EXTI system multiplexer. The third step consists of enabling the adequate edge detector for the EXTI line. The EXTI controller is capable of generating an interrupt on a rising edge, falling edge, or both edges on an EXTI line transition. The last step involves enabling the interrupt line in the CPU nested vector interrupt controller, or NVIC, to generate an interrupt as soon as the EXTI controller raises its interrupt event.