 session 17th of ARM based development. In this course in the session we will be covering ARM term instruction ah more on ARM term mode and then in the next session we will be talking about the term instruction in detail . So, what we have covered so far is about all the ARM instructions we have covered everything about ARM ah instructions so far and we are all ready to start writing ARM term ARM assembly code to solve various problems ok and that familiarize with the different instructions how and the how they function and then how to use them to solve ah realized problems ok. So, you you are equipped now to write assembly language already ok with so much of examples of every instruction that we have covered in this session . So, ah let us now see what is the term mode and then how ah they help in the embedded systems ok why did the ARM introduce that a new state in the ARM problem . So, today's discussion will be covering this topic and we will go into the details of term instruction in the next session ok. Let us see the background why term state is required and then what is it actually trying to do and how is it helping embedded developers to use the term mode state of the ARM processor ok . So, I have already drawn this picture. So, I do not want to waste your time on this. So, ah what ARM what we will see a corresponds to you know the whole thing and then term refers to this part of your hand correct . So, they have named it to indirectly mean that the whole ARM processor is capable of this mass and term mode is a small part of it ok ah this is a symbolical representation ok. Do not think that you know if this ARM is 80 percent only 20 percent of that could be accomplished in term mode you do not have to interpret exactly as the picture shows ok. This is only a symbolical meaning saying that how term mode is a subset of a ARM ok and all of you all aware that without some you know we cannot do a whole lot of things right. So, this is named appropriately. So, let us see how this design philosophy has evolved and how does it help us ok. So, basically term instruction set is a 16 bit instruction. If you remember ARM was a 32 bit instruction ok. What do I mean by that every instruction is 4 byte wide correct 4 byte wide and all the instructions were always starting on the 4 byte boundary and then the ARM processor was a you know in accessing the 4 byte at a time interpreting the instruction which are 32 bit wide whereas, in term mode it is a 16 bit wide instructions ok. So, one instruction is just a 16 byte sorry 16 bit wide that means, only 2 bytes ok. So, naturally the termed instructions are organized in the memory ok on 2 byte boundaries please remember what is 2 byte boundary and 4 byte boundaries you must be aware now. If our you know starting into this 1000 100 here then this will be 102 the next instruction will start at 102 and then the next to that will be 104 in decimal ok. You suppose if it is in decimal then 106. So, it will start like this ok it will all be occupying 2 bytes ok. So, in 1 clock ok that is n clock right. So, earlier in term mode we saw that it was accessing 4 bytes instructions. So, when you see the pipeline it was filling the pipeline which are 32 bit wide correct. Now, the same pipeline exists ok inside the ARM processor nothing changes only thing is what thewith the memory what ARM is interfacing and then how it is reading the instruction it change. So, it starts searching 16 bits ok only 2 bytes as a instruction ok 16 bits. So, it is it will be moving the 16 bit instructions into the pipeline ok. Now, what happens after the decode stage I will explain, but the fridge as far as the fridge stage is concerned it is accessing 16 bits at a time from the memory which are 2 byte wide and those are the instructions. So, it has to interpret the instruction within 2 bytes. So, that means,assembler should have known that ok it is generating a 16 bit instruction or 32 bit instruction accordingly it should be encode the contents into the instruction ok. So, when we say that term mode code term with the ARM is executing in term state and then from starting from 100 suppose already at the 100 ARM instructions instead of ARM instructions termed instructions are filled with ok who has filled it it could it is that ARM stool chain with the programmers input saying that from 100 address 100 termed instructions are to be filled. So, every instruction will be a 16 bit wide instructions which are filled into the memory and then the ARM processor starts fetching 2 bytes at a time from there ok. So, that is what I call as a 16 bit instructions and addresses the issue of code density. So, what is the reason for this thumb thumb mode instead of whatever you accomplish with the 32 bit wide instruction ok most of the things we are accomplishing it using only 16 bit instructions. So, effectively we will be saving here on code density that means, amount of code that you have to write and then amount of code size that particular thumb code occupies in the memory will be smaller compared to ARM code ok understood. So, this is a thumb mode. So, what I am saying is thumb mode code is only 16 bit wide. So, if most of the instructions of ARM are you know implemented with a 16 bit of course, some limitations will be there, but with a 16 bit encoding then we will be saving on the amount of memory that is needed to save that code in the memory. So, that is why code density is the advantage one of the advantages. It may be used as a compressed form of a subset of ARM instructions ok understand there ok. I will explain you how we are compressing ithow the tool is compressing it and how the ARM processor expands it we will see. So, thumb instructions map into ARM instructions. So, what I mean by that is though thumb instructions are 16 bit wide and they are compressed and stored in the memory. After they come into the processor in the fetch mode it comes as a 16 bit ok instruction. It goes through a decode stage where it is decompressed and then a that equivalent 32 bit instruction is generated ok. Every 16 bit instruction mode there is a equivalent 32 bit instruction which is generated or decompressed internally in the processor ok. So, that is in which stage it is in decode stage then onwards the processor from this ok execute stage whatever the processor is doing internally the register file everything may not know except that the thumb bit in the CPS will be set ok. I will show you where when the thumb mode is there how it is different inside the processor. So, CPSR there is a particular bit which will be set other than that the instruction is like a similar to ARM instruction ok. It exec you know it accesses all the 32 bit instruction or registers and then they do a similar operation that you know original ARM mode was doing. So, that will be performed, but with someassociated limitations which we will talk about it. So, what I am saying is the 16 bit instructions in the memory gets decompressed ok into the 32 bit equivalent ARM instruction and then it is executed internally ok. So, what is the advantage of this? So, in the thumb mode only a new entity here gets activated which is a decompressor other than that they execute more you know the logic of this as well as the inside internal registers there is no change it is they are all equal same as what you would have seen in the ARM mode. So, effectively with a smaller modification it is minor changes into the decoder object we are achieving some efficiency in terms of core density ok in the thumb mode very good. So, thumb programmers model maps on to ARM's programmers model what is programmers model you must be knowing now it is all registers how many registers that programmers views in you know in the mode particular mode and then what are the access restrictions what can be accessed as a 32 bit or 16 bit or byte or all those things ok it is a programmers model whether even the NDNS is part of this. So, they are all same ok they remain the same only except that the instructions are seen as a 16 bit wide and internally they are converted to equivalent 32 bit ARM instructions and then they execute it internally in the processor ok very good. So, implementation of thumb use dynamic decompression what I mean by dynamic mean as soon as as and when the instruction gets fetched from the memory it is decompressed it is ok it is not a static decompression or anything it is as soon as it is fetched from the memory it knows that it is in the currently in the thumb state. So, it knows that it is fetching only 16 bit wide instruction. So, it gets decompressed into a equivalent 32 bit ARM instruction. So, thumb is not a complete architecture please remember thumb mode if I say a processor supports thumb mode that does not mean that it only can execute 16 bit instruction that is what I am saying it cannot exist alone ok. If it can execute a 13 16 bit instruction in thumb state that means, it actually has all that is required for a 32 bit mode of ARM ok. So, it actually on reset it starts with a 32 bit mode and then changes over to 16 bit. So, 16 bit mode is a subset of the ARM mode and thumb mode cannot exist on its own it has to be along with the ARM instruction set and the ARM ok internally ARM processor architecture is same. So, it is a add on thumb state is an add on to the ARM instruction ARM processor ok very good. So, it is not anticipated that processor would execute thumb instruction without supporting the ARM instruction set it is not anticipated. So, if the thumb is supported ARM instruction set is default supported, but the other way is not true ok ARM instruction set may be there, but thumb may not be there ok. So, it may execute only 36 bit instruction, but it may not have a support of ARM or the thumb mode ok very good. Let us go to the philosophy of this. Therefore, the thumb and section set need to only support common application function. What I mean by common mean? The most important things which are used ok frequently or most ah ah commonly used functions are supported in the thumb mode because thumb mode is a subset. So, you the suppose ARM instruction is so much the thumb mode will be some something. So, there should be choice which one to be left out and which need to be supported in thumb mode. So, that is decided based on the common application which are used. Allowing request the full ARM instruction set where necessary, request in the sense it comes back to ARM mode wherever necessary for instance all exceptions automatically enter ARM set. So, so as once I said thumb mode is a subset ok inside a ARM mode. So, processor can decide to support something some sub curve inside functions in the thumb mode and then whenever it needs to take ah you know ah support of the ARM mode instruction it come jumps to the ARM mode and does something and then goes back to thumb mode for some common functions ok. So, one example is exception handling. So, all the exceptions handling are supported only in ARM mode I explained in the last session. So, inside the thumb mode there is no exception support, but one question would be this does it does it mean that inside the thumb mode there would not be any exception no. Thumb any anywhere when the processor is executing there is a possibility of any external interrupt coming correct IRQ or FIQ may come somebody can press reset correct when it is fetching the instruction a fetch prefetch about could happen when it is accessing some data a data about could happen and then say you know system mode supervisor the mode all the modes are there in the thumb mode also please remember when it is in thumb mode all the other exception modes are always there based on the whether it is enabled or not in the CPSR ok, but when those exceptions do happen the exception handling is done in ARM mode ok. So, it comes out of the thumb mode executes the exception handler and goes back to thumb mode that is what I mean by thumb mode not supporting the exception handling ok, but exceptions are always could happen in any mode ok even while fetching a thumb instruction that can be a memory call even while a thumb instruction is writing a some data into the memory that can be a data abort ok and while it is a processor is executing in thumb mode that could be an IRQ or there could be an FIQ ok those interrupts can come it you know interrupts are not going to wait for which mode it is and then you know interrupt the processor it may give interrupt and then if you have this F and I bit are there in the ARM processor the CPSR if they are clear that means, they are enabled then these interrupt will be recognized and then processor comes out of the thumb mode and then goes to the interrupt worker table and they execute the handler ok that is what I say exceptions are automatically handled in ARM mode from which fully supported by ARM development tools. So, what I mean by that ARM assembler or a compiler recognizes you are you have to inform them ok inform the tools that are a going forward this code I want to put generated in thumb mode that then it will generate 16 bit instruction ok and then then you can let on say that I want the ARM instructions to be generated here. So, mode will change over to ARM mode you have to make sure that you know when you come into this code ARM code mode is modified ok and then it starts executing the ARM code. So, the development tools all of them support both the modes and applications can mix both ARM and thumb mode subroutines together ok. Wherever there is a performance ok a to optimize the performance versus code density ok. So, if code density is important you go for a thumb mode if performance is important then you go for ARM mode. So, you can choose which one you want to execute in ARM mode which one you want to execute in thumb mode and then tools will support it and then you will generate the code accordingly and then processor changes the mode and then such as those instructions accordingly. So, use of thumb instruction set can improve code density ok. You can relate how code density improves based on the thumb mode because thumb mode has 16 bit wide instruction I told you that you are trying to compress the ARM instruction into a 16 bit instruction. So, effectively only 16 bit bit you know code instruction is getting fetched from the memory. So, only 16 bit data or whatever numbers will be used right to fetch the instruction. So, the signals drawn driven on the 16 bit ok the power delivered or power consumed would be comparatively lesser compared to a driving a 32 bit wide instruction bus right. So, there is only single bus there is a data bus you know either data will come into the bus or instruction will come. So, in a typical ARM mode 32 bit of instructions will be fetched whereas, in thumb mode only 16 bit instructions are fetched. So, it has to drive only a 16 bit bus. So, power efficiency happens because of that ok. Now, code density happens because it occupies less space in that memory how does it save the cost? If you have a 16 bit memory you can of course, the memory cost will be less and then the interface also kept to be a only 16 bit the bus will be there interfacing with the ARM ok. So, that is possible in that case the cost of the set whole setup will be less because you are you know PCB bit and the bus the power required everything comes down and then cost of memory also cheaper and bus which is also less. So, because of that cost will also be less. How does it enhance the performance? Because I told you most of the functions are compressed into 16 bit instruction, but they are integrated as a 32 bit instruction. So, there is no not much of you know performance wise internally once they are decompressed they are behaving like a another 32 bit instruction. So, the performance is also relatively better by using the thumb instruction ok. So, power saving cost saving, code density and then performance all at once thumb mode supports ok ok. Now, let me tell tell you how the thumb state is entered by the processor. So, if you recall there is one bit in the processor CPSR register which is meant for thumb mode. So, if this is set ok then it is in thumb mode otherwise if it is 0 it is in ARM mode ok that is the only difference. So, based on this mode change you can in a very very quick you know quickly it can just change from mode one mode we have one state to the other state ok. We can call it as state rather than mode. So, we call ARM state and thumb state ok. So, maybe I am using mode also interchangeably maybe let me try to avoid that because mode is always associated with the processor mode we thought system mode, supervisor mode, user mode right IRQ mode FIQ mode these are all called modes. Whereas, you know to differentiate between a mode and the state they call this as a thumb state not a thumb mode ok. So, it is not part of the mode. So, let me rephrase. So, always we talk about thumb state or ARM state ok good. So, ARM processor we support the thumb instruction set can also execute the standard 32-bit ARM instruction. So, I told you that. So, the big 5 of you know the T bit correspond to that thumb state. So, T is set then the processor interpret the instructions in a 16 bit and itexecutes in the thumb state otherwise it is the ARM state. So, how do you make over whether a particular processor core supports thumb state or not? If in the name you have a T if you see a T that means it supports a thumb state ok. So, that is a so, we are talking we are learning about ARM 7T EMI. So, I explained about this later earlier. So, T corresponds to the thumb state support provided by this core ok very good ok. Now, let us see how a processor in ARM state enters a thumb state ok. I told you that ARM core start up after reset executing ARM instructions. Please remember on on reset on reset what is the value of T bit when I say that it starts in ARM state that means, T bit will be 0 ok on reset it is 0. So, it starts with the ARM core that means, what the vector table has the entry to map to you know to point to the reset port right. We have to write ARM instructions here because it is going to fetch a 32 bit of instructions because the processor starts off with the ARM state ok. So, please remember that I will start from the sorry friendsthere was a little bit of technical interactionin the recording. So, let me start from this where I I do not know where I actually leftin this slide. So, let us start from this. So, ARM core starts ok in a on reset after the reset it starts an ARM instruction mode ok and then later on by executing a branch with exchange branch and exchange instruction it switches to ARM state ok. So, I am explaining a typical scenario where that exchange are moving from ARM state to thumb state happen how does it happen ok. Assume that this is the instruction ok and assume the currently the PC is executing the ARM core is executing this instruction it is in the execute state. So, PC will be pointing that O not A ok because plus state will be the typical offset ok this is O not 4 and why is it incrementing by 4 this is the ARM instruction. So, this is 32 bit by instruction. So, from the ARM state it is trying to change over to thumb state. Now, using this instruction branch and exchange with R 1 and I am assuming that R 1 is having a content 1001 please remember in a typical scenario any address for a ARM state should have the last 2 bits as 0 because it is a 4 byte boundary. So, these 2 do not actually have any value correct last 2 bits of any address in a 32 bit address correct because it is a 4 byte boundary. So, it will fetch 4 bytes at a time. So, the instructions addresses can jump from 100 to 104 then 108 correct it jumps by 4 bits 4 bytes. So, but still there is a bit set here ok. So, when the processor execute this instruction what does it do ARM processor when it encounters a bf x it sees that means, it is supposed to exchange exchange with what the PC you know PC with the value in R 1. So, it will load whatever is the content of PC R 1 into PC, but PC has to be saved because after the branch it is supposed to come back to the next instruction which is 4 byte next to that. So, whatever is the previous value of PC which are supposed to be 108 is it will modify it with by my separate in by 4. So, that 104 is copied into the R 14 ok. So, the link register ok link register it will be it will put that address into a link register and then go to wherever R 1 is pointing it ok this address right which is in R 1 ok. So, it is supposed to move to 1000 is it supposed to move to 1000 or 1000 1 see one has a indication to say that if the LSB is set the new address if where you are moving the processor is moving to they are all encoded in a 16 bit format that means, if they are all in some mode those instructions are format you know encoded as 16 bit instruction ok. We are informing the processor ok by executing this instruction with R 1 having this content if this instruction is informing the processor saying that hey when you go to the new address which is there in R 1 ok please interpret the instructions as 16 bit. So, how how will it do that how can it do that it will do it will do it automatically if it can change the t bit to 1 right if t bit is 1 that then it will automatically go into some mode and then whatever addresses it fetches it will fetch as a 16 bit weight instructions. So, basically this 1 is to indicate that this when you change over to the new address ok you you have to change the t bit also to 1 ok that is we are telling the processor to do it ok. Automatically CPSR t bit will be modified by making only the t bit change it will not change anything else and then copy the low air shift 31 bit of address ok 31 bit of address because please remember ARM is a some state is a 16 bit instruction that means, only the LSB 0 or 1 it does not matter right 2 bytes anyway it is 2 byte boundary. So, only the bit 0 in the address is do not care the rest of the 31 bit needs to be considered as an address in the term state ok whereas, in ARM state the lower 30 bit will be considered as the address and then the LS bit 0 and 1 will be considered as a do not care. So, because it is moving from ARM state to the some state it has to only consider the top 31 bits not 30 bit or 32 bit top 31 bits will be considered as address and then the LS bit will be considered as a 0. So, when it is loading the value into PC it will copy the rest of the bit except the first bit and then the first bit is set. So, it will make this t bit as 1 that is it then it will go on to this 100000 and then start executing this as a cum instruction. So, that is what happens ok when you change over to some state this is how ARM processor moves to some state ok I hope this is clear to you. So, this is the outcome of the instruction ok when this is the content of R 1. So, note that since the instruction causes a branch it flushes the instruction pipeline please remember when there is a branch the new set of instructions are fixed. So, earlier BX is here in the execute state R 1 some ARM instruction would have been here. So, in the different stages now because it is a branch it will flush these two and then refill it with the thumb instructions which are 16 bit wide. So, because t bit wide ok the thumb instruction which is coming into decode stage will be decompressed and then the as the execution starts. So, previous instruction which were fetch which happened to be ARM instructions they are all you know ignored they are flushed out of the pipeline. So, other instruction which is changed from ARM to common mode ok include exception returns why exception returns ok let me explain. I told you inside ARM the thumb state is there whenever exception happens it comes to ARM mode. So, automatically assume that IRQ are there ok as soon as IRQ interrupt is suppose FIQ is not know active or it is no signal is on that IRQ is there. So, IRQ has to be serviced ok no other abort or anything is pending. So, IRQ is has to be serviced. So, processor jumps to automatically jumps to ARM state. That means, it makes the t bit equal to 0 and then it jumps to ARM state executes the ARM the IRQ handler, but you have to remember when this when it is doing this change it also saves the current CPSR into a relevant mode SPSR ok. In this case IRQ SPSR is there in the SPSR it saves the current status of the CPSR. Now, in that state t bit would have been what set because it was earlier executing the thumb then section. So, it would have been equal to 1, but it has to recognize IRQ and it comes jumps to IRQ handler by reading the vector table and then coming to handler, but automatically it also saves the status and then only changes this please remember the CPSR is modified after saving the previous content. So, the previous content with the PS1 has been saved into SPSR of the IRQ mode ok. Now, when it comes back from the exception back into the original instruction ok it could be a thumb instruction or it could be ARM instruction assume it is both are in user mode. So, if it happens to be a user mode thumb instruction it will it will come to know whether it is coming back to thumb mode or ARM mode by as soon as it copies the SPSR into CPSR. If you remember there was an instruction I told that move S with PC as a destination and then the return address is copied there then automatically SPSR is moving to CPSR right this moment also happens. So, as soon as the SPSR content which you had a t bit as 1 moves into CPSR the processor enters the thumb state. So, from the new wherever it has to restart from it will start fetching it 16 bit instruction because it has already moved to thumb state. This is what I am saying that it returns from exception if it was earlier before going into the exception it was in thumb mode when it returns also it will come back to thumb mode please you should remember this it is little involved, but you should you have to visualize what happens during the exception how the CPSR getting saved into SPSR preserves the original state of the thumb state or the processor. So, by restoring the SPSR into CPSR it comes back to the previous state it could be ARM state or thumb state, but it comes back to that state. So, so there is a possibility of ARM to thumb mode coming back by while coming back from the exception because if it was a thumb mode where the exception happened while the processor was in thumb state then it comes back to thumb state automatically when the SPSR gets you know return into CPSR ok. Let us see how thumb state exists happens ok. So, I in the previous example I showed you how it enters thumb state there should be a two possibilities while entering the thumb state one is you know by executing the BX instruction with the some value in R 1 or R 2 any register with the LSB of this register set to 1 then it moves from ARM to thumb state ok this is entry into thumb state and the one more possibility of entering into thumb state is returning from exception that also explained return from exception that also comes back to thumb state because exception needs to be handled in ARM state it comes to ARM state on exception and then we are going back it goes to thumb state. So, entry into thumb state can happen either through proper instruction or through exception return now I am going to explain you how can it exit from thumb state now it is going out of thumb state to ARM state. So, one thing is very clear if an exception happens of course, it will exit from thumb state and then it goes to ARM state is not it. So, that is the because of exception happening but can the and you know that exception is a unprogrammed event. So, how can the programmer decide to move out of the thumb state that is called programmer deciding to exit of thumb state that can also be done by executing a BX instruction ok. So, in the BX instruction suppose thumb state also supports the BX instruction ok this is 16 bit wide ok it is executing a BX instruction with the same assume that some register R 1 ok R 1 happens to have the bit 0 let us be at the 0 ok suppose then what it will do it will know that ok now this happens to be 0 that means, it has to come back to ARM mode. So, it will when it executes the BX instruction it will come back to ARM mode from thumb state sorry I am saying more thumb state ok sorry thumb state. So, I should not mention more for ARM and thumb. So, thumb state to ARM state happens by doing a BX which is happens to be a thumb state instruction, but R 1 will again be may have made 0 or the LSB then it will come back or implicit return to an ARM instruction stream whenever exception happened I told you exception also can bring this state from thumb state to ARM state. I hope this is very clear to you because this is the you know material how does the processor enter ARM state from thumb state and then how it goes back to thumb state. So, this exchange of state you should be clear about ok. Unfortunately the instruction simulator that we are using does not support thumb state. So, please you cannot practice them writing this instructions in the in this lab, but since I told you that instructions are all same. So, you do not have to write you know another set of instructions to try out all the thumb state instruction. Only thing what we should be aware of is how does the processor switch from one state to the other state. Once as soon as you are clear once you are very clear about this then you learn you know quite a lot about the ARM you know that and then thumb state ok there is nothing much to know only this how you can move from one state to the other state is what is more important ok. So, let me show you one example ok a typical code this is a pseudo instruction if you remember address loading ok. We are trying to load a a address into R 0 ok which happens to be a PC address that means, what a code a pointing to a code ok. Assume assembly code is written like this ok you can mix a ARM code and a thumb code in the same file no issues only thing is from the instruction ok because you look up the instruction it looks same ok B X R 0 and R 5 they look the same ok. So, the processor the assembler when it is generating the code since both instructions are supported in both the state ARM state as well as thumb state ok the instructions are supported in both state. So, you should know by some mean whether it is supposed to generate a 16 bit instruction or a 32 bit instruction for a particular mnemonics you have mentioned. So, that is given by mentioning the ARM 16. So, prior to this somewhere ARM 32 code 32 would have been written ok. So, once you have code 32 this is thecommand to the assembler to say that whatever instructions you encounter after this particular the you know command interpret them as a 32 bit instruction ok. So, this B X R 0 will be interpreted as a 32 bit instruction. So, it will generate a 32 bit instruction, but what is it what are we doing here? Intro thumb thumb is a let me you know remove all the thing because intro into thumb is a. So,hi friends. So, what happens this is the you know instruction that I am explaining youlet me get the pin ok. Now, let me refresh it again start from here. So, what happens is once we have that LSB as 1 here because that label is added with 1 and then that is loaded into R 0. So, RSB the bit 0 of R R 0 is 1 then automatically the processor enters a thumb state and the processorassembler also would have you know read this course course 16 and then it was interpreted as 16 bit instructions here. See both should match what the assembler generates and then how the instruction flow assumes the instructions or whether it is in thumb state or arm state both should match otherwise suppose you have a 32 here and then you try to jump here it will cause a problem because the instruction would have been encoded as either 16 bit based on what we mentioned here. So, once we match these properly you know while writing the course then there would not be any issue because it is course 16 is there. So, 16 bit instructions are here and then the control also jumping to this location. So, and then we have set this LSB bit as 1. So, it goes to 16 bit mode and then execute the rest of the course as a 16 bit instruction in a thumb state. So, in this case the bit would have been set ok. Now as a programmer you are interested in jumping back to arm state because you you want to execute may be some very you know very critical code which has to be a 32 bit right. So, that may it can run faster. So, you you have written it such a way that you are informing the assembler saying that a following this code is generated 32 bit code then processor will interpret all this assembly mnemonic sets a 32 bit instruction. And then when you say R 2 5 is loaded with this address and then you will just say B X R 5 without that plus 1 ok, without that plus 1 what happens the bit 0 would have been 0. So, thumb state the that bit would have been cleared again now it will go back to arm arm state. So, please remember the moving from one state to other state is very veryyou know trivial in the sense it is not doing a whole lot of job like what thumb typical exceptions do ok. Please remember moving from one arm to now user mode tosome IRQ mode it involves a lot of work ok it will involves lot of work that means, it has to go to the other state they will save the CPSR SPSR values as well asyou know change the mode of the processor and then start saving the registers if IRQ handler is doing all those things will be there. Whereas, in the state change the registers the original registers whatever values are there they are all retained as it is ok. I will tell you whether all the registers are visible in each state if only part of the register set is visible, but still the contents of those registers remain the same. So, you can pass on some informationwhich you have done in the one state suppose R 2 register is you know with loaded with a new value something and then you want to use it in another state it is exactly you know perfectly possible there because all the things are this you know it processor remains in the same mode when it is changing from one state to the other state mode change it does not happen only state change happen. So, and that also only the 1 bit in T bit is changed the rest of the things are same mode mode mode between the CPSR is same other whether inter flag and IRQ FIQ are enabled or not even the CPSR contents everything remains the conditional flag everything remain the same. So, you can seamlessly move from one state to the other state because if that happens to be complex then there is no advantage of having two two states and then trying to save something. So, ARM designers have taken care of that. So, it is a excellent you know thinking that when you move from one state to the other state it only changes the 1 bit in the CPSR and then rest of the state information is preserved and the mode remains the same. So, it is a seamless movement from one state to the other state ok. So, I hope this is very clear to you how we move from ARM to some state and then come to ARM state ok very good let us take it on. Now, I will give you the so far I have not told you what are the registers are visible are they all registers visible or the all band registers are visible in some state we have not talked about that. So, let us see please see some so many band registers which you saw in ARM state correct they are all not there in some state ok why because in the some state anyway we know that exceptions are not handled in some state correct exceptions can happen, but they are not handled. So, there is no need to be the some state processor enough in me does not have to know the existence of this bank register. Any way when exception happens when it enters the exception mode it will enter the ARM mode and those relevant bank registers will be visible to you. So, in the some state they are not visible ok even in the user mode register not all registers are accessible by all instruction ok. They are there physically please the bank register also physically there in the processor it is not that somebody has come from takes away, but they are not visible at all they they is a some state does not even know the existence of other modes. But here so it is only the this registers are visible ok core registers and the top the this registers are used only by specific instruction ok and then the rest of this registers which happen to be a generic purpose also you could use R 13 or R 14 or R 15 ok in a typical ARM mode they are all tied to a particular function here ok. Why is it so? Because they want the in the term mode the certain state there is only 16 bit place for encoding any information. So, so most of the things need to be hard wired or assumed to be you know a particular function. So, that it need not be configured in the instruction. So, to simplify the instruction encoding some assumptions are being made ok. So, it always assume that R 13 is a stack pointer ok in ARM state you can have anything as you know any other registers also as a stack pointer whereas, that is not true with the thumb state ok and then also though all the low registers are visible in thumb state not all the high registers are visible in the all the instructions. So, it may be some part of the instructions in the thumb state may access them, but not all of them ok. Similarly, CPSR it is you know whole thing is visible, but accessibility wise it cannot change the mode of the mode mode bits of the thumb on a CPSR. In the thumb state you cannot modify the mode because if you modify the mode you are supposed to be aware of the mode bank registers which is not there in the thumb state. So, it will remain the same mode as what it was earlier ok. You cannot modify the mode of a processor in the thumb state ok. Let us see what are the other things. Thumb and state as a subset I told you already it has a restricted view of ARM registers only low registers we call it as a low R 0 to R 7 and these are all hardware it is meant for special purposes and thenmostly the stack pointer is you know is very important because it always assume that R 13 is the default register to be used for in the thumb state if there are stack related operations to be performed ok. I will explain you what I mean by that ok. In the previous example so far in ARM state we have seen that any register could be played you can use it as a stack pointer ok that if you remember that full and decrement or empty and increment all those things right. So, here there is a restriction remaining high registers have a only restricted access ok. A few instruction allow high registers to be accessed not all of them and CPSR condition code flags are set by arithmetic and logical equally operations ok. One more thing I need to tell you here the CPSR condition flags correct CZNB as a reference ok. In the ARM state we will say move S add S right only when we mention S this state register the condition flags are modified right otherwise they are not modified by the ARM in the ARM state when you execute this instruction. Whereas in thumb state there is no option of mentioning S at all you will only say add ok. Anyway move does not support you know disturb the state arithmetic and logical operations ok add or and anything you do whether you mention S or not they will default affect this condition flags ok in the thumb state. I will tell you why ok that may be think it over why they have removed that S option in the thumb state ok. Let us have one small quiz here take two minutes break you do not need more than that please read it over read it out and then decide the answer then they can continue ok. Welcome back if you say all the options are looking reasonable I am sorry they are not actually the correct option is C ok. I will tell you why other options are not making sense there is no need for more registers in thumb mode it is not that there is no need ok. As a programmer we want as many registers as possible right we cannot say that there is no need in our thumb mode thumb state ok I should have mentioned it at thumb state ok sorry you write it at thumb state ok there is no more ok. So, thumb state we want all the registers, but the problem is with a 16 bit encoding possible only 16 bit encoding we cannot have all the registers encoded ok why because if you allow more registers to be encoded your number of bits required to encode them will also increase see when you have r 0 to r 7 how many bits are required to encode them encode them 3 bits correct 0 0 0 to 1 1 1 ok. Whereas, if you say even if you want to include r 8 also into it you need a 4 bit of 4 bit wide encoding and in the instruction you will need to decide in the 16 bit instruction encoding we as a processor designer we have to decide whether we are going to have 3 bit for operands register operands or 4 bit for register operands. If you use more bits for the operands then naturally the amount of bits left for operations will come down. So, they have to know as a designer they need to optimize on number of bits required. So, basically what they have done is reduced the number of registers. So, that the number of bits required to encode them in the register in the instruction comes down. So, they can compress the instruction bit. So, high register to increase the power there is no relevant to relevant to high registers and low register increasing power ok it does not make sense. Allowing access to all the registers in the processor will slow down the execution of thumb state that is also not true. And this is also not true because we always want as a programmer we want more register, but because of the restriction that 16 bits only are allocated for the thumb instructions. So, the the processor designers have gone in for a only reduced visibility of instruction set ok very good. Now, let us just quickly look at the similarities the thumb instructions are 16 bits long ok you know that and they map into ARM instructions. So, they integrate many properties of ARM instruction set they exactly map 1 to 1 mapping is there. They are also the same like load store data processing data transfer and control file instructions ok all of themthe same set of instructions ok there is no change let me and then it also supports all the different word word words ok. And then please remember the 32 bit memory is visible in the 16 bit thumb state also. So, the memory what is there is still a 32 bit memory ok. So, you do not assume that ok once it enters the thumb state is only as a half of the memory is visible now even in thumb state the whole unsatmented you know 32 bit is visible. However, in order to achieve 16 bit instruction then number of characteristics features of ARM instructions are have not been supported in thumb state ok some some of these characteristics features are not there that is all. But, but the holistically they work on 32 bit registers they work on the same memory ok 32 bit memory all that is same ok internally because the I told you that internally registers are all 32 bit. So, whatever address is generates are also 32 bit. So, you know you know the whole 32 bit memory is visible even in the thumb state ok that you should know know. And then what are the differences most thumb instructions are executed unconditionally except branch instruction what I mean by unconditionally if you remember the instruction format the first 4 bits are conditional code correct. So, you can say add EQ right and then sub NE all that you were we were able to do it in ARM state, but they are not possible in thumb state ok. The default the all these instructions are you can mention only add and sub. If you write like this maybe assembler may give a warning or it may just not or you know it will not allow you ok because always this is executed that means what this conditional flag is this not a conditional flag it is on condition in which this particular instruction needs to be executed this taken as always that means 1 1 1 0 if we call this pattern. So, this particular bit pattern is not there in the 16 bit this instruction bit at all ok. So, conditional codes are not there. So, conditionally you cannot execute the instruction, but instruction can affect the conditional flag, but you cannot execute the instruction conditionally please remember only a few instruction may be executed like that. Similarly, the data passing instruction use two others format what is two address format in a typical ARM state we will say that r d comma r m comma r n correct. So, you can write you can mention three registers whereas in thumb state you can mention only two registers r 1 comma r 2. So, what does it mean that means only r d comma r m that means it will assume 1 to the r d itself is r m ok they both are same ok r n is there and the r m. So, only two register format is allowed in the thumb state ok there is in being again there is the limited space for encoding the input machine. So, and the ARM in compared to ARM instruction format the 16 bit cum instruction format is little bit not very regular that means the bit pattern will be you know we we are not going to look into the patterns how it is encoded, but they are not in a very for regular as a condition flag will be here and then you have seen that right a specific location is reserved for you know r d then something for r m and something for r and all those you know fixed locations were mentioned you know fixed because there are a you had the ARM designer had a 32 bit of instruction width to place them whereas, in the 16 bit instruction encoding they have to accommodate what is possible within that limitation ok. So, a dense encoding is there are no state of register access instruction there is no MSR or MRS instruction which accesses the CPSR they are not there in the thumb state ok you cannot access the state of that is why I am saying you cannot modify the code you cannot modify the thumb state in the thumb mode ok and then you cannot modify the conditional factor also directly you can execute an instruction and then get modified, but you cannot write into them because unless you have this MRS and MSR you you cannot access any of the contents of the CPSR in the instruction many addressing modes are not supported in thumb state ok. So, these are the differences and no bank register of course, and privilege modes in thumb state. Now, the biggest register difference involves in the SD register ok stack pointer ok I mentioned it that means, actually push and pop are the two instruction which are supported in thumb state and they default use the R 13 as the base register ok and they internally convert into ARM instructions with the door and store LDM or STM or LDR STR, but when you say push or pop they assume it as R 13 ok I will when we talk about the instruction I will explain more in the next section, but remember that there is a default stack operations are assumed as assume assumes R 13 as the stack base pointer ok stack pointer and there are there is no swap registers in the thumb state again sorry about this it should have been thumb state ok very good . So, no support for coprocessor instruction I have not talked about the thumb state, but let us you knowcoprocessor instruction I will talk about that later and then barrel shifter operations are separate instruction what I mean by that if you recall the ARM state hasyou know you can have one of the operands you can say you know L H sorryyou can say arithmetic shift left A itself ok. So, we can mention as a part of the an instruction itself we can mention the barrel shift operations right whereas, in thumb state they are all separately given as the instruction. So, you cannot along with the instruction you cannot mention thebarrel shifter operation why again the limitation because of the instruction weight. So, but support for barrel shift operation is there, but you have to mention it as a separate instruction ok and then all data plus instruction set conditional path that is one more in you know you cannot mention S flag because again it is one bit will be wasted if S bit needs to be mentioned. So, they have removed the S bit option that means, what every instruction logical or arithmetic operation will affect the conditional path ok the C S that can be. So, these are the basic differences now let us see how it is implemented inside the processor a thumb instruction set can be incorporated in the 3 stage pipeline ok with a minor change ok. Whereas, in a 5 stage pipeline ARM 9 there is little bit trickier, but we are not going to cover that ARM 9 anyway here in our course and then biggest addition is the thumb instruction decompression ok I mentioned it earlier, but I will see I will tell you how it is implemented this law is translate thumb instruction into equivalent instruction ok. Since ARM does not a little ARM does a little little work in phase 1 of decode cycle let us remember fetch cycle decode cycle in that phase 1 is there okthere is a signal clock and then if you have 2 phase signal if you have seen there is one moreyou knowsecond phase. In the first phase the decode logic that ARM instruction does very minimal work because it is only resolving the registers and all that and actual access of the register accesses are happened in the execute stage only. So, what is what am I trying to say earlier is the decode stage can easily accommodate the decompression logic that means, I told you that a thumb instruction gets expanded to ARM instruction in the decode logic that means, it is decompressed. So, this job of decompression this not not delaying the decode logic so much because you know that when the decode is happening parallely some memory access or some internal register operation or arithmetic will be happening and they will be taking more time. So, decode logic may not be a bottleneck in deciding the m clock for the particular processor implementation that is what I am trying to say. So, thumb pattern operation exactly the same way as ARM pipeline please remember if they work as a same way ok. So, I told you this decompression happens here ok. So, thumb to decompression perform the static translation that means, what it has a you know 16 bit ok. What I mean by this is the translation is not going to modify ok it will as soon as the instruction come ok 16 bit instruction the every pattern of 16 bit instruction the thumb state instruction has a fixed pattern on ARM state ok they convert it into 32 bit ARM state format ok. They there is a direct one to one mapping ok that is what I call as a static translation ok. So, that translation happens and this involves performing a look up to translate . So, what I agree with 0 extending 3 bit registers are expanded to 4 bit registers because you know when it is converted into a 32 bit instruction any register mentioned in the 16 bit instruction may be you have mentioned as R 1 you would have mentioned it as a 0 0 1 3 bit whereas, it comes here as a 4 bit value. So, it can be 0 extended because that is the reason anyway only the lower bityou know lower set of register are 0 to R 7 are used in the most of the instruction here. So, they can be 0 extended in without any problem ok it will still map to the same register which was referred in the thumb state instruction ok. I hope this is clear to you. So, this is what is being done by the implement you know thumb decompressor. So, this is the internal operation. So, you know you know you know based on whether it is a a thumb state or arm state a 32 bit or instruction 32 bit or 16 bit instruction come here and then the pipeline interprets it as thumb state or instructionarm state based on the 3 bit and then this is 16 bit ok this is another 16 bits ok. So, you may wonder how it isanyway instructions are accessed from the memory as 16 bit only right 16 bit instruction they are coming as a 16 bit why is a low or high is given it could be because the memory and arm processor how they are interprets it is totally it is a very flexible. You remember that there is a separate data bus and it could be a 16 bit bit 32 bit wide data bus can be there. So, the memory can be you know connected to the processor in different so many different ways. So, based on that either the memory may give the you know instruction based on the whether low half word lower half word or higher half word those instruction may land into any of this buzzer. So, it is internally handledby how it is connected on the memory and the processor. So, you might get a instruction 16 bit instruction always in a lower half word or it could come the higher half word and lower half word. So, based on the type of the state it may choose one of them ok or it may choose this this decompression itself will be will not be there in the normal typical arm state this is how what is the width of this will be 32 ok. So, this will not be functional when arm if it is in some state suppose the t bit is 0 and arm instruction the attribute with the instruction comes and then it goes through this and then it goes there ok decoder it enters the decode stage ok this is the pipe in a fetch stage this is the decode stage ok. So, let me if suppose you have missed out something let me explain this little bit more ok. So, this is the internal ok or the organization of the inside the processor ok. So, this is instruction fetch mode stage and the whole thing is a decode stage this is the decompression part of the decode logic and this is normal decoding of instruction and then identifying the register operands and all that. Now, when this instruction come in based on the t bit it may be getting a 16 bit wide instruction or 32 bit instruction from the memory ok and then they will enter the marks based on the whether how memory is providing the instruction 16 bit instruction whether in the high this 2 or 16 bit ok and this will be a 32 bit wide ok this is 32 bit why this is a typical data data are getting read either using LDM or STM or LDR or STR then those instructions anyway will fetch 32 bit data I told you that memory is a 32 bit memory you know segmented memory and segmented memory. So, 32 bit data only will be read by the processor either it is in some state or arm state suppose instructions only there is a difference. So, if it is some state what happens the 16 bit instruction come through either this bus or you know higher part of the data bus or lower part of the data bus the instruction enters and then it gets decompressed this logic is activated and then what you get out what you get is a 32 bit instruction ok either it is taken from here or taken from there based on the arm state. Now from here onwards it behaves the same way like whether it is a arm state or a thumb state ok from this onwards the behavior of the processor internally will be same. So, every 16 bit instructions have a a unique 32 bit instruction map to arm state and then onwards it acts as a arm instruction ok please remember that. So, an example suppose you have written a in a thumb state your instruction written an instruction like this what it means see there is no conditional code EQ or ME is not there. So, it is always executed ok it is always executed and there is no F here it is default assumed to be F. So, that means, it will affect the conditional flag. So, F is there. So, it is always assumed that S is present and then I also said one thing 2 operand instead of 3 operand in thumb state it is a 2 operand that means, what one of the operands is same as R D. So, R D is there in 2 places and immediate operand is exactly the 8 bit is coming here S is added because always S bit is there and then it is executed always that is why when it is expanded a 32 bit instruction is generated like this this is the code for conditional flag or always. So, this instruction is always executed ok S bit where is it it is here wait a minute I think if I remember correctly it is here ok. So, S bit it is set. So, if this instruction as such is going to impact the conditional flag and this is to say that it is a immediate operand because immediate operand is there ok and then R D is same register is put here and then you see here it is extended with a 0 ok and here also extended with a 0 ok. What is this? It could be an add operation. So, it is actually you know 0 100 is the data processing of instruction. So, it is mentioned here with the immediate operand ok. So, add instruction is given ok and the R D is written this way and then immediate operand one more operand is additional third operand is a immediate operand. So, you can see that any instruction in the thumb state maps to a equivalent arm instruction ok that is what you should remember fine this is how it is done and then if you recall a originally in the thumb state 12 bits are reserved for immediate constant. Now, since we are only reserving 8 bit in the thumb state the remaining will be filled with the 0 ok. So, that is all this is how it is expanded. So, typical thumb system how they are used it should be clear that all thumb systems input some ARM code for handling initialization and extra expression handling ok ARM is there always. It is likely however that most thumb applications will make more than this minimal use of ARM code. So, more of ARM code may be there that is what I am saying ok and then a 32 bit memory or 16 bit memory could be used. So, we can use a fast 32 bit memory for ARM code and then use a 16 bit memory for thumb code ok. See again this is independent you know it is left to the designer system designer. So, typical which is the best way of designing it is put all the thumb ARM code in a 32 bit memory and then put all the 60 or thumb state code in the 16 bit ARM and then it is also can be a offset of shift ARM. So, that it can be little bit slower also ok. So, this is how a typical example of thumb system may look like ok. So, what are the benefits some numbers thumb code requires 70 percent of the space of the ARM code ok why it needs more or less it needs only 70 percent of the space of the ARM code ok. Suppose you are doing a some job ok in ARM state ok and then you are converting the whole thing whole set of instruction into a you know thumb code ok thumb code. That means, you are executing everything in the ARM state. Now, the effective code say suppose this was occupying 16 bytes of 100 bytes of um code code space it would only take 70 bytes of thumb instruction, but please remember the instruction number of instructions here will be more than that number of instructions here why because this every instruction takes 32 bits here. Every instruction here takes only 16 bit so, but still it occupies 70 percent of the space. So, the number of instruction number of instructions here will be more ok greater than number of instruction here in ARM state ok. Whereas, space wise space code space wise this is less than this space ok ok maybe I will you know this is I will write it like this. So, the space wise this is less ok whereas, number of instruction wise this will be more in ARM state ok. So, how much space the thumb code uses 40 percent more instruction that is what I am saying number of instruction wise this will be more ok you know than original ARM instruction that space wise it will be less. So, 32 bit memory the ARM code is 40 percent faster ok if suppose you are using a 32 bit memory ARM will be running faster there, because you are accessing 32 bit at a time, but if you are using 16 bit memory the thumb code will be faster if a 45 percent of faster than the ARM code ok. So, because you know you are accessing it as a same bit and this is in sync with the way you the processor wants the code to be provided to it. So, you know 16 bit more beneficial in the ARM state thumb state compared to a 32 bit memory in a ARM state thumb code uses 30 percent less external memory power ok it accesses it uses less power power, because it generate it only powers the half of the bus in the data bus ok the data portion of the bus for such in the instruction. So, performance is all important then what you do you can use 32 bit memory and ARM code if cost and power are more important 16 bit memory with the thumb code ok. So, this is the overall comparison of how core space compared to instruction and you know which is better which memory to be used in which state is what is given this is the summary of all of them ok. I hope you understood the reasoning behind all of them . So, we have come to end of this session we will touch on the instruction you know of thumb state in the next lecture ok. So, today we talk saw the background design philosophy and how it is implemented inside the processor the thumb state of the processor ok. I hope you understood everything here nice to talk to you and then we will again meet in the next section have a nice day. Thanks for your attention. Bye bye.