 So, welcome to this lecture on VHDL and the course digital system design with PLDs and FPGAs. In the last lecture we have seen some issues with the finite state machine. Basically we have seen how to optimize state diagram, basically the algorithm then we have looked at the output races and what is the solution to that problem. Then something about the selection of flip-flops and you know kind of advantages in choosing a particular type of application, actually we have more, some more issues to be handled in the case of the finite state machine but I think to discuss that it is better we look at how to do the VHDL coding of finite state machine. That will bring clarity to that those portion not that lot of coding is involved but whatever little that can be shown there will you know bring clarity and you know put things together. So for a at least one lecture or two we will concentrate on the VHDL coding. So before that we will have a quick look at the last lecture's slide. So let us go to the slide basically this is what we have seen when you have a state diagram there could be equivalent states and there are multiple equivalent states you can retain one and remove all the other because others are redundant. And the equivalent states produces the same output under the same input condition for milli kind of output for more it is only just the state matters. And it also transit the equivalent state transit to the same next state for the same condition that means number of transition and number of the conditions on those transition should match then they are equivalent and you can retain one that was the idea. And we have discussed how to detect this in a next state table. So if you look at the next state table say you detect the rows which are identical except the present state those are candidates for kind of equivalent state then with this you can go to the next state table these states next state table and find the kind of the rows with identical rows except those present state. Then an intersection of those states which should give you the equivalent state and one can be retained and we have discussed some kind of decent algorithm. So look for the same next state and find them out then look at the input condition that will give a subset of that. Then you go to the next state table look for all these kind of states whether the outputs are same and you choose those states in the case of milli you have to check the input condition also then you are with the equivalent states then you can retain one. We have looked at this scenario when there are multiple flip flop change the state and if there is variation in the propagation delay there could be transitory states and if that produces output and there could be glitches in the output for brief duration at the beginning during transition and that can affect if it is used depends how these condo signals are used. If this is used in a synchronous way to enable some muxes and all that no harm because the clocking will happen on the next state but if you use it asynchronously to clock something to basically to clock something then you are in trouble because say this is a right signal to a memory then the location can get corrupted depending on the pulse width okay. Even if the data bus is triceated some whatever the values whatever those floating values will get kind of returning to the location so one need to be careful. And to avoid it if you can avoid somehow the multiple bits changing this scenario can be avoided so that means you have to go for gray coding but that is not possible in all cases then we go for output registering the idea is to put a register at the output of the logic output logic. So these transitory kind of glitches will not be caught in the next clock head but the valid outputs will come will be registered here everything appears one clock period late but that is okay. So that is how the output registering is you know is done and we have kind of simplified because this logic can be clubbed here then this flip-flop can be clubbed there and you get a picture like that which is this comprises of next state logic and output logic. This comprises of output registers and state flip-flops so you can see that out of this logic the next state come the output comes and here the state flip-flop will give the present state and the output flip-flop will give the registered output. The advantage of this view is that we know that a single process can do the you know in a single process we can code a register with the preceding logic. So this can be very easily you know coded using a single process in VHDL that is one advantage of that and we have the last thing we have looked at was the selection of flip-flop if you use D or T or JK what are the transition table and we said JK you have the twice the number of output coming off of the next state logic but then because of the down care maybe the area can be lesser than D and T and the FPGAs and CPLDs have many a times this choice of between the D and T flip-flop same flip-flop can be used as D or T. So that was the last lecture so let us look at today's part we are looking at how to do the VHDL coding of a finite state machine. So this is the block diagram of the finite state machine you have next state logic looking at the input and the present state decoding the next state which the flip-flops will upon the clock will transfer the next state to the present state. Output logic will decode the present state formula output along with the input to produce the output. Now you know that this is flip-flop you know how to set up flip-flops you know how to do the VHDL coding of that it is very simple and this next state logic is a combinational circuit and we have discussed how to write using when else or with select or case when if then all that. So there is nothing great about it but also you know this is also logic so you can use any constructs in principle there is nothing new about it but there are since there are various like we will see how many ways different ways you can attack this problem that should be kept in mind. So naturally so if you take these inputs there could be multiple external inputs then the clock reset all that will be ports or signal while coding because in the state machine is controlling the data path. So many times the clock and reset can be external all the inputs sometime can need not be ports it can be signals because you we have a data path along with the state machine. So many times come out of the data path and when you code it together this can be signals output can be signal because which goes to the data path to control something but at least for our kind of classroom study sometime we make some FSM simple FSM with some assumption of input and output in that case will be ports but definitely the present state and the next state are internal and so they will be signal ok. Now at the beginning itself I will say this there are different ways of coding it and we are going to soon see what all possible ways you can code the FSM ok. Say one thing I can say you can write a process for this a process for this a process for this it is ok I mean or you can write concurrent statement for this output logic. But the important thing is that you know that if the tool the synthesis tool has to detect that this is an FSM finite state machine. So if you do the coding say this is a combinational circuit this has flip flop and this is a combinational circuit the tool may not know that all the three comprises a state machine ok. So that will be like you will get the desired result because you are coding it correctly but all together put it together the tool should know it is a state machine then only it can do the state machine specific optimisation like we talked about the state diagram optimisation unless that is known the tool may not be able to do the various kind of optimisation attack various issues and so on. So it is very important that when you work with the tool refer to the tool manual and find which is a coding style which is specified by the synthesis tool and stick with it and do not try to code it in any other way. So that is very important to kind of understand and nowadays many a times people read less and less manuals. But even sometime it is trivial I suggest that when you use a tool however simple the tool is even if you buy a new cell phone it is worthwhile to read the manual spending some time so that lot of time can be saved otherwise the initial things will be fast then you get stuck you can waste lot of time. So that is my advice so let us go into this coding part. So let us see how many different ways you can code it so as I said you could write a process for next-side logic, one process for flip-flop, one process for output logic ok. We will see how that process can be written but at least we are kind of enumerating all possible way of you know writing this FSM in VHDL ok. Now sometime what happens is that the number of outputs are less ok. So number of states are more maybe say you have 8 states and only 2 outputs ok. Now if you write a process for 8 states and 2 outputs what you have to do is that when you write a process you can use only case or if. You will say case present state is when as 0 you will say what are the output there are only 2 outputs then you say when as 1, when as 2 and so on ok up to S7 but this can be avoided if the outputs are coded in concurrent statement then we can say suppose O1 and O2 are the outputs then you can say with present state select ok O1 gets 1 when you know S0 or S5 or S6 something like that L0 ok. So in 1 statement 2 statement 2 concurrent statement the output can be written. So if you see that the number of outputs are much less compared to the number of states then it is better to write the concurrent statement for this output logic. So that is another way of you know looking at it there is a third way of that you know that the registers with the preceding logic can be written in a single process ok. So we can do that we can write one process for this flip-flop and the next state logic and you can write a one process for output and that always again bring this issue up if the number of outputs are less same one process for next state logic and flip-flop. Then you can write concurrent statement for output ok. So these are the kind of four different ways you can code by looking at this picture you know we can kind of look at different scenario with these logic combined ok we will come to that and we have to also look at the reset the reset can be asynchronous or synchronous if the flip-flop has asynchronous reset then we will use that. So asynchronous reset in the flip-flop process so if we have we are using asynchronous reset wherever the flip-flop is there we will write include the asynchronous reset if or you can include a synchronous reset in along with the next state logic with that we have discussed earlier how to introduce reset and we just talked about the circuit that. So naturally we will have to say that as a priority we have to say if reset is one the next state is starting state and so on ok. So these are the possible you know different possible ways of doing the VHDL code. Now we have seen a two block view of the FSM wherein we said anyway this output logic and the next state logic receive the same kind of inputs that is the present state and the input. So why not combine this and show the output as if from here and call this logic which comprises of next state logic and output logic. So let us kind of look at that so if you do that then we have a logic section which is comprising of next state logic and the flip-flop. So you can write one process for this next state logic and output logic and one process for flip-flop ok. And here you could even separate the output logic with the concurrent as concurrent statement you can do that but the fact that we are looking at such a block diagram which shows that maybe this is the appropriate thing with respect to this diagram ok. So these are the kind of two scenarios we have looked at as far as the coding is concerned. So let us look at this kind of scenario so where the next state logic is process flip-flop is process, output logic is process or concurrent statement or these two together in a process. So we will see how that can be coded. Suppose you want to write next state logic as a process then we know that we have two kinds of input one is the present state ok which is multiple bits ok. Then number of inputs lot of inputs ok. So we write a process within the sensitivity list is the present state and various inputs may be I1, I2, like that so that is a process. And now we have two inputs to handle one is the present state and next is a input and when you look at the state diagram for a particular state all the inputs are not valid you know like you are in a particular state then you say if a particular input is 1 go to the next and so on. So and this has to happen for all the state so very normal intuitive thing to do as far as the coding is concerned is a case present state is and you say when s0 ok. Now for that state s0 you say if start is low then remain there or if start is 1 else if start is 1 then go to the next state. So this is 1 because you have to say for all the states so case is a better thing but for a particular state only certain inputs are valid. So we use if nested if under the case for each choices we use a need for to specify the transition ok. Now when it comes to this particular block very simple we say if reset is 1 present state is the starting state may be s0 else if clock given clock is equal to 1 we say present state get the next state that is all ok. So that is what is shown here if reset then starting state else if clock given clock is equal to 1 the present state get next state and output logic if you are using only the more kind of output then we can say case present state is when s0 you say suppose there are 3 outputs you say what are the output values when s1 what are the output values and so on ok. So that is what is shown here and if the output logic is in concurrent state when we say because that depends on the present state we can say with present state you say when s0 and what are the outputs. And if it is a milli kind of output you can say if under that particular state you can say if kind of input is 1 then the output is 1 and so on. And then we can combine these two together that can be coded like if reset is then you know what is the beginning then you say else if clock given clock is equal to 1 because we are putting these two together. And under this because this will now come at the D input of the flip flop. So this logic will come within this clock even clock is equal to 1 we have discussed that and you say case present state is when then all the if you have to write. So this is a little bit kind of complex coding but it is very convenient because looking at the state diagram we are able to write in one shot otherwise you have to look at the state diagram to write this process. Again go back from the beginning you have to look at the state diagram to write this but if you are combining it from top to bottom you can write it together. So it is less error prone and we checking or debugging is very easy if you put it together okay. So now this is the scenario where we are combining both together. So we said it is case when on present state you say case present state is when as 0 when as 1 for each of the state you say if on a particular input then you transit to next state. And the flip flop is simple we have discussed that and when synchronous reset is used there is a chance of implied latch I will maybe I will not discuss this now when we go to the coding we will look at it. Now what we are going to do is that we are going to take an example very simple example maybe when we discuss the case study we will see a reasonably complex state machine to control the data path. Now my indent is to you know show the styles of coding for that I have to kind of use less space so I am kind of bringing a very simple example as a state machine basically to illustrate the coding all the I do not want to show only part of the code I want to show everything. So I have chosen a very simple example it is a sequence detector basically in communication when a transmitter transmitting something to the receiver it can be synchronous or asynchronous many a times the clock is send along with the data in communication and with some encoding you know there are different type of the clock encoding can be used maybe you have heard about Manchester encoding differential Manchester encoding and all that ok. So that allows to embed the clock in the data it is retrieved and resynchronized with the PLL. So we are kind of and the receiver should know when the transmission starts so many a times at the beginning of the transmission or a beginning of a frame depending on whether it is synchronous transmission or asynchronous transmission there will be a pattern and which is a quite a long pattern ok it is not a very simple pattern and the receiver is looking continuously every bit it has to look for that pattern ok. When the pattern comes it is kind of you know sure that the transmission is starting and the synchronization happens like that. So we are taking a very simple example transmitter and we are assuming the clock is available that is a scenario though it is a separate clock line is not sent from the transmitter to receiver. So we are kind of coming out with a state machine to detect a pattern 101 sent by the transmitter that means this detector is continuously looking at this data in DN and that is synchronized with the clock. So every positive edge the data is sent and this is continuously looking at it and whenever it receives a 101 it make the detector high ok. Now we are not you know designing the receiver we are just detecting or designing the detector sequence detector and we are trying to implement that detector as a finite state machine which need not be the case in a real sequence detector which is used in communication so mind you but then it is a nice exercise so to work with it basically sequence detection. So I give some mental exercise as well as it clarify our idea of the state machine the coding and all that so that is the basic idea. But mind you this is an overlapping detector ok that means suppose the transmitter is sending something like say 101 then like if it is a known overlapping detector say 101 it is detected then says it sends 00 not detected again 101 is sent again it is detected. Suppose the transmitter is sending 101 again 101 it is a known overlapping detector that means every 3 bit boundary this pattern is searched ok. So but when we say overlapping detector it means that the receiver looks for the particular sequence every bit boundary not the boundary is not limited by the length of the sequence every bit the sequence is checked. So it may happen that the transmitter is sending a pattern 10101 5 bits so the first bit first 3 bits 101 the detector will detect as the particular sequence then from the third bit third bit is 101 so third bit is 1 fourth bit is 0 fifth bit is 1 again that overlapping the 1 2 3 is a sequence 3 4 5 is also the 101 sequence that is detected. So you know I mean this is exercise maybe a mathematical exercise than a circuit design but then it is good to discuss that so let us look at how this can be done. So let us turn to the block diagram the block diagram of the state machine is simple a clock input a data input and a 1 output which is detected whenever it will see 101 it is this goes high and as I said if there is a 01 here then this third bit fourth bit fifth bit will constitute a sequence again that will also be detected we have to design that in a such a way. And very important thing to remember that the clock and the data is synchronized so we cannot afford to miss any clock ok. So in the FSM we have discussed we have assumed that the clock is bit kind of flexible and the clock can be very high frequency clock and we have you know we can wait for some input to in a state for something to happen and all that here we cannot miss any clock you know we cannot eternally wait every state a data comes that should be kept in mind. So let us try to detect this 101 so let us draw a state diagram for it so basically we have to look for say at this beginning if we come to a state like at the reset we come to state a let us call it say and the output has to be because we have one output definitely it is 0 the output is 0 detect is 0 ok. Now we are looking for 101 so if the input is 0 we have nothing to do remain there you know because we have come to starting state the sequence have not started it is 0 coming so remain there. So if it is d in is bar dash or d in is 0 then remain there detect is there but if d in is 1 we have received the first bit ok 1 and we come to state b we have received the first bit detect is 0 but here the game start if it is 0 we got the next bit because here we have received the first bit if d in is 0 d in dash we can go to the next state. But if it is d in is 1 we do not have to go back because we have already got 1 and if further ones are coming it is a starting bit of the sequence and we can remain here you know as long as 1 is coming remain there so that is what is shown here because any time the sequence can start. So if further ones are coming remain there detect is 0 if it is d in is 0 d in dash go to next state that means that we got 1 and 0. Now if the 1 comes we go to state d and we can say detect is 1 ok and but if it is 0 d in at this state we have got 1 and 0 if 0 comes everything is destroyed we have to go back ok. So that is the detect is 0 so if the 0 comes you go back reset nothing can be done look for new sequence but if it is 1 then we have got the sequence ok 1 0 1 and the detect is 1 ok we say detect is 1 now the game start ok if it is 0 no luck you go back ok sorry if it is 0 mind you we have got 1 0 1 ok now 0 you do not need to go back you should not go back because this 1 could be start of a new sequence new sequence. So if it is 1 0 you go back so you have you are in the new sequence 1 0 and 1 comes you come back here. So if it is 0 you go back here if it is still 1 it could be start of a new sequence so you go back here ok so that is it so if d in a 0 this is a new sequence and 1 0 if it is 0 you go back if it is 1 you get it back again if it is 1 still it could be the starting state. So that is the state diagram once again because we have to write the code so remember this at the beginning come to state a detect is 0 0 remain there 1 go to next state 1 remain there and detect is 0 0 you come here because you have got 1 and 0 and detect is 0 if it is 0 go back if it is 1 come to d detect is 1 if it is 1 go back to the state b because it is a new sequence could be starting if it is 0 this is a second bit of probable second bit of a new sequence so 1 0 and that is done. So we have 4 states so a b c d 1 input d in and 1 output ok. So let us look at the VHDL coding of this and let us look at this is a more kind of output ok. So let us look at this we will write like this next state logic as a process flip flop as a process output logic we will write concurrent because there is only one output there is no point in writing a process because there are 4 states we have to say case present state is when a when b and all that that can be avoided if you write as a concurrent statement. So let us look at it this is the library close IEEE library the package this is the entity as I said since we are writing this kind of standalone all our input d in clock reset or input standard logic detect is output standard logic and the entity name is sq detect 1 and we say architecture some name of that. Now comes the thing we have to kind of remember with most tool support see we have 4 states with binary encoding we will end up with 2 flip flops ok. So the present state and the next states are 2 bits because there are 2 flip flops so this we have to define a standard logic 1 down to 0 ok both of this but this is kind of cumbersome what happens is that if we come and make some changes suppose we find that this state diagram we have drawn as some problem and we have inserted one state in between then it becomes 5 state and whatever was 2 bits has become 3 bits and you have to do a lot of changes it is a big problem. So most tools allow you to define the present state and next state as an enumerated type ok so that you can easily change the state diagram. So how that is done is that you define a new type ok you say type state type and this is a name you know it can be anything it may not be called state type some type you know some name is then you say the state names a,b,c,d so these are the 4 values this state type can take and we know that internally it takes 0, 1, 2, 3 and there are 4 states so it will be encoded in 2 bits and internally it may be assigned 0, 0, 0, 1, 1, 0 and 1, 1 then we define the present state and the next state by this kind of enumerated data type we say signal present state and next state is state type ok. This is one advantage the tools give as very convenient and internally it is converted into the standard logic vector and so this is what you please check with the tool you are using whether it support that. Now let us write the next state logic so let us write the next state logic looking at the state diagram here next state logic a label process the input to the next state logic is present state we call it you see here the pr state the pr state, all the inputs you know we have to write all the inputs but we have only one input so we write that d in it is a begin ok. Now for various state we have to write the code so we say case present state is ok. Now we have 4 states a, b, c, d so we say when a in the first state now we specify the transitions ok say if d in is 1 then we got 1 is next state is b else next state is a that means if d in is 0 remain there you know that is what is shown here d in is 0 remain there d in is 1 go to b ok and mind you do not ever write if d in is 1 next state is b end if ok. If you write like that there will be a implied large you know people will think that anyway you are in a so you just say if d in is 1 next state is b and end if you say when a is there there will be a feedback do not ever do that just state the complete if else you know you have to complete it otherwise there will be implied large ok. And when b in b we say as d in is 0 then go to next state otherwise stay there so if d in is 0 next state is c else remain there when c we know that if 1 0 1 if d in is 1 then next state is d else next state is a going back all the way if it is 1 go to d else go back there. And in the d if it is 1 go back to b else go back to c so that is what is shown here if d in is 0 then next state is c 1 0 else next state is b ok. And if when others because we have to enumerate all the condition as far as simulator is concerned next state is a ok does not matter we are only kind of taking the theoretical possibility for simulator so n case n process. So that is how we code the next state logic in a process using case and nested if and as far as the flip-flop is concerned it is simple flip-flop the process clock and reset in the sensitivity list begin asynchronous reset if reset is 1 then the present state is a because we have to make the present state the starting state you know so upon the reset this will become a then everything happens properly and it will transit so at the power on it comes to a so that is what is written here like if reset is 1 then present state is a else if clock 1 clock is equal to 1 then present state get next state end if because there is a memory and n process that is it ok. And the concurrent statement you know that detect is 1 when the present state is d so that is what is written as a concurrent statement detects gets 1 when present state equal to d l 0 and n sequence detector 1. So this is completed we have the entity architecture we have written a process for the next state logic with case on present state for each state we write the transition using the if for state transition. And we write the flip-flop in a process with asynchronous reset and the output in a using a concurrent statement being more it is very easy ok. So that is it and now we look at this kind of scenario where the next state logic and output logic are combined together. So it is simple like we say here case present state is and you say when a at the beginning we say what is the output detected 0 without if and we say if condition and you repeat it and that is idea. So that is what we are going to see case on present state and you state what are the outputs for each choice and in each choice we write if on input for all the transition ok and as usual if reset is in the flip-flop process ok. And as we have written and when synchronous reset is used there will be an implied latch I will tell you I will show you soon how that happens ok. So that is this is the sequence detector VHDL code where in the next state logic and output logic is combined in a single process and flip-flop is a process. So as before we have the library and the package we have the entity with the DN clock reset as input and detectors output. In the architecture declaration region before the begin we have the enumerated data type type state type is ABCD signal present state next state is state type and these all are kind of standard. So you can cut and paste copy paste from the previous thing only thing is that if you have a new state machine with more state you add that and this is a useful template to keep and this is where we are writing giving a label process where we are combining both the output logic and the next state logic. The sensitivity list as the same as before present state and DN the fact that the output logic is combined does not change this because the output logic also get the same kind of inputs. So present state and DN and when we say case present state is and we take the first state when a and we say detect get 0 then that is we have specified the output for particular state more output. And now we specify the transition if DN is 1 then next state is b else next state is a and if and so on okay. So we do the same for b the c and the d okay. So that is it only thing is that when you say when others you have to say detect is 0. If you do not say there is an implied latch so wherever you say when you have to specify the output if there are multiple output in your case everything has to be told here like if you have a detect and enable as output everywhere it has to be specified not only the place where it changes that you should keep in mind. Now the flip flop is as before same the clock reset begin upon the reset the present state is a else if clock even clock is equal to 1 present state is next state. So that is why I said this all can be written as a template you just copy paste. This is same for all you know irrespective of the enumerated types maybe it is a state diagram with 5 state 8 state this is not going to change it is all same because we have declared this as a state type which is enumerated. So we need not worry about the size of the number of bits which is used to encode the state that gets automatically you know covered and so let us now earlier you know we have looked at a Moore machine for detecting 101. So let us do a Milley machine just for the as I said just as a practice and you can already see what can happen in the Moore machine we have said come to b 0 come to c 1 come to d and say detectives 1. So you can imagine what can happen we say 1 0 now upon the 1 instead of going to d we say in this state if the d in is 1 the detectives 1 ok that is a game but we should know where to go like with that transition that is what we are going to see in that Milley machine. So let us look at this same thing it is a sequence detector same block diagram the sequence is 101 it is an overlapping detector it is a Milley machine. So at the power on reset you come to state a detector is a 0 as long as d in is 0 remain there if d in is 1 come to next state b is 0. Again we know that if d in is 1 remain there d in is 0 come to next state c d in is 1 remain there because it could be start of a new sequence and 0 transit to the next state. Now here we are going to say detectives is 1 if the d in is 1 and we have got 1 0 and if detectives 1 if the d in is 1. So we can say detectives d in it detectives is 0 if d in is 0 but upon that 1 we have to transit. So you got 1 0 and 1 back here because that 1 could be a beginning of a new sequence. So 1 0 1 again 0 1 it can go like that but if it is 0 you go back here ok. So that is what is shown here detectives d in d in happens go back here d in bar it goes back there. So this shows even in a like we have discussed what is the difference between Moore and Milley kind of output you see here there were 4 states now the 1 state is less for a 1 output and we also know that the detect comes earlier it used to go to the d state and the detect used to come. So whatever we had discussed before is true here also. So let us look at this kind of coding and we are going to code the next state logic and output logic together in one process. So that is in one process so we write a label a process present state and d in and when we say case present state is when a we say when a detect is 0. If d in is 1 next state is b then next state is b else that means it is 0 and the next state is a end if and I said as I said do not ever say if d in is 1 then next state is b end if because implied latches are come to b we say detect is 0 because detect is 0 if d in is 0 go to c if d in is 0 next state is c else next state is b you know remain there d in. Now like when c we say detect is d in detect is 1 if d in is 1 detect is 0 when d in is 0. And now the transition is if d in is 1 go to b d in is 1 then next state is b else next state is a and if when others we say next state is a sorry I have to say some value for detect otherwise it will be implied latch. Remember that I have to specify detect some value it does not matter but I definitely have to say detect is 0 or something like that so otherwise there will be implied latch I have to say that. So, that is the millet machine with the output logic and the next state logic combined. But if you are writing the output separate then you can say like this detect is 1 when present state is z and d in is 1 else 0. So, that is what we want here say we say out detect is 1 if the present state is z and the d in is 1 that is what it is written here okay. Now assume that we do not have like in the previous diagram the asynchronous reset we are combining the synchronous reset okay. Now when you code that it looks very simple for coding we say if reset is 1 next state is the starting state else if clock even else you can say case present state is okay. But there is a danger in there that is what I am going to show okay. So, here what can happen is that you say a process where the present state and d in is a input and now a new input comes reset and you say if reset is 1 then assume that this detect is not there and you say next state is a okay. Else you say case present state is that we know that in that case you are going to specify the next state as well as detect okay. So, in here for each state we are going to specify the next state and detect and if you do not specify the detect here there will be a implied latch on detect. So, we say detect is do not care okay you can say anything it does not matter detect is 0 it really does not matter. But then to avoid that feedback that latch we say detect is 1 okay. So, this you have to be careful when you write two things when you combine the next state logic and output logic and you include the reset in this particular use synchronous reset you can end up in this state and write all the outputs here if there are four outputs you are going to specify all that here in this reset section you write for output and say do not care okay that is that you have to remember otherwise you know there is another way of doing it you just say the reset separate you do not say you write the case for the next state logic and output logic do not mix it with the reset you say if reset is 1 then next state is a just say end if not a very good I am not very kind of comfortable with this style you know that this is much better than this one. But I suggest you use a previous one. Now when you write a code like that we have no control many a times what is a state encoding okay like many a times a tool will assign 00, 01, and 10 to it though we have not discussed the state assignment what are the advantages of state assignment which we are going to see in the next lecture we may have to give a different assignment. So that can be kind of specified by some state encoding attribute so you can have a sequential coding we have seen the gray coding you know if you do sequential coding you might end up with output racing so you can use a gray coding and there is something called one hot one where one state is encoded in a one flip-flop we will see that where it is useful but one hot zero is like one hot one but you start with all zeros okay in a one hot one if there are four state then there are four flip-flops so you have 001, 0010, 0100, 100, but in a one hot zero you start with all zeros so that is a difference. But that can be manipulated by a state encoding using some attribute in VHDL coding so this is the kind of syntax for it you say attribute state encoding of whatever type name you have used. See here we have used the state type you know when we said at the beginning we said the state type okay so we have to say here attribute state encoding of state type then type is you can say sequential gray 101, 1, 0 and things like that. So I am showing one example where attribute state encoding of state type is gray there is another way you can say attribute enum encoding of type name state type say is type is give string give the assignment straight away. So you can say take the assignment as 001, 1110 okay here you have to choose between this four but here you can kind of you know tell the custom encoding okay. Now you have to check the tool the vendor specification whether they support this every tool vendor may not support this attribute may they may call it by a different name. So you have to you know check the documentation of the tool suppose that is not possible okay like the tool does not give you an option of changing it then you can explicitly instead of using the enumerated encoding you can instead of saying type state type is ABCD you can literally hard coded you say signal present state and next state is standard logic vector 3 down to 0 and you define constants you say constant A is standard logic vector 3 down to 0 equal to 001 constant B constant C constant D and so on then you can use ABCD only. So even if the states are changing you have to the architecture declaration region you can come and change it in one place and do the change in the coding and mind you we have seen that the moment you have the state diagram the coding is exactly 1 to 1 okay. So it is possible that you can automatically generate the code from the diagram not a graphical diagram. So the tools let you draw the state machine. So the moment you put a bubble and give a name they know that there is a state called a second bubble and B they know that there is a B and if you draw and put an arrow they know that there is a transition. So as and when you draw these things are tracked and ultimately a 1 to 1 code is generated. So there are graphical FSM editors are available in the tool and that can be used but at the beginning when you start I suggest you code it not a great effort you learn it well maybe then once your practice then you can use a FSM editor from the tool window. So I just want to kind of close that part of the VHDL here so that we can continue with the state machine in the next lecture. So essentially we have looked at the various coding style we can adopt for doing the VHDL coding of the finite state machine we have seen all possible ways okay like using process and next side logic and output logic combine, next side logic and flip flop combine, output logic using concurrent statement. We have taken an example a simple example of a sequence detector of an overlapping sequence detector which is detecting 101. We have seen a Moore type detector Millet type you know output we have seen the various coding style. We have seen there is an issue when you synchronous reset and combining the output logic and the next side logic and how to sort it out. And we have briefly looked at how to change the state assignment using attributes once again it is tool specific vendor specific you have to check the documentation. Ultimately the vendors give an FSM editor which generates the code from what you draw though it looks like a magic it is very straightforward a good computer students can take it as an kind of project and easily do that. And so that is what we have seen in the next lecture we will continue with the issues of the finite state machine various other issues and this lecture will be useful there. So I suggest you go back maybe practice some state machine maybe you can try a different sequence the best thing is that different sequence write the code simulate and learn well. So I wish you all the best and thank you.