 Hello everyone, this is Vishwanath Chavan, assistant professor, department of computer science and engineering, Walchan Institute of Technology, SolarPur. Now I am here to explain 8087 numeric data processor. At the end of this session, students will be able to describe the block diagram of 8087 architecture and they will be able to explain the pin diagram of 8087 architecture. 8087 numeric data processor is having some other names like math co-processor or it can be called as numeric processor extension or it may be called as floating point unit. It was the first co-processor which is designed by Intel. These are paired with 8087 resulting in easier and faster calculation. Once the instructions are identified by 8086 processor then it allocated to 8087 co-processor for further execution. So it has different data types. We will see what are those. It supports for binary integers, packed decimal numbers, real numbers and temporary real format. Let us see the different features of 8087. It supports for different data types like integer, floating and real types and which are ranging from 2 to 10 bytes. The processing speed is so high that it can calculate multiplication of 2 different sizes like 64 bit width, real numbers in 27 microsecond and can also calculate square root in 35 microsecond. It follows a high-tribal floating point standard. Let us see the architecture of 8087. So mainly it has two parts. One is control unit and another is numeric extension unit. Let us see the different function unit of respective. So control unit is having data buffer, control word, status addressing and bus tracking, exception pointers and these are the connections which is connected to external word. And to numeric extension unit. So this unit has different function units like component module, microcode control unit, operand queue, tag word. So there is a register stack which is 8 bit, programmable, shifter, arithmetic module, temporary register and this is how connected to all these components. Now let us see more detail about these two units how it works. So 8087 architecture is divided into two groups. One is control unit and other is numeric extension unit. The control unit handles all the communication between processor and memory such as it receives and decodes instructions, reads, writes memory operand and maintains parallel queue etc. So all the co-processor instructions are ESC instructions because it is identified that it is concerned with 8087. So that is they start with F. The co-processor only executes the ESC instructions while other instructions are executed by the microprocessor. The numeric extension unit handles all the numeric processor instructions like arithmetic, logical, data transfer instructions etc. It has 8 register stack which holds the operands for instructions and their results. So think about this question and try to answer. The question is 8087 architecture is divided into how many parts and what are those? Pause this video and write the answer. I hope you answered. Let us see the answer for this. The answer is 8087 architecture is divided into two groups. One is control group and another is numeric extension unit. Let us see the PIN diagram of 8087. So total it has 40 pins. PIN number 1 ground, PIN number 40 VCC and address and data lines AD0 to up to AD19. No connections, clock, ground, reset, ready, busy, QS1, QS0, S0, bar, S1 bar, S2 bar, no connection, RQ bar slash GT0, INT, RQ bar slash GT1 bar, BHE bar, S7, then S6, S5, S4, S3 like this. So we will see more detail about all these pins. The following list provides the description of respective pins. AD0 to AD15. These are time multiplexed address and data lines. A strands address, D strands data. So which carry addresses during the first clock cycle and data from the second clock cycle onwards. Next, A16 to A19, meanwhile S3 to S6. So these lines are time multiplexed address slash straightest lines. It functions in a similar way to the corresponding pins of 8086. The S6, S4 and S3 are permanently high while the S5 is permanently low. It has BHE bus high enable slash S7. During the first clock cycle, the BHE slash S7 is used to enable the data on the higher byte of the 8086 data bus. And after that it works as status line S7. QS0 and QS1. These are the Q status input signals which provides the status of instruction queue, their conditions as shown in the following table. So QS0 and QS1. If both bits are 00, then the status is no operation. If it is 01, then first byte of upcode from the queue. If it is 10, then it is empty queue. If it is 01 and subsequently byte from queue is identified. So there is a int pin which is interrupt. It is an interrupt signal which changes to have when unmasked exceptions have been received during execution. When busy, it is an output signal. When it is high, it indicates a busy state to the CPU. Next one ready. It is an input signal used to inform the co-processor whether the bus is ready to receive the data or not. Next reset. It is an input signal used to reject the internal activities of the co-processor and prepare it for further execution whenever required by the CPU. Clock. The clock input provides the basic timings for the processor operation. Next VCC. It is a power supply signal which requires plus 5 volt power supply for the operation of the circuit. Next S0, S1, S2. These are the status signals that provide the status of the operation which is used by the bus controller 8087 to generate memory and IO control signals. These signals are active during the fourth clock cycle. Let us see the table which talks about status input signal S0, S1, S2. So the first two are unused. Next 101 which indicates memory read. 110 which indicates memory write. 111 which indicates it is passive. RQ slash GT1 and RQ slash GT0. These are the request and grant signals used by the 8087 processor to gain control of the bus from the host processor. 8086 for operation transfer. These are the references. Thank you.