 Hello and welcome to this presentation which describes the DMA transfer's hardware and software views. To start a DMA transfer, a request is required. This request can be caused by a hardware event. From a peripheral indicating that data are ready to be transferred. From a peripheral indicating that an update of its control registers is required. From a peripheral indicating that a read of its status registers is required. A software request can also start a DMA transfer. This is typically caused by the CPU writing to a control register of the DMA controller in order to transfer data from a memory mapped address range to another memory mapped address range. The DMA controller implements a programmable arbitration logic that enables the user to adjust channel bandwidth and latency requirements according to the following rules. The priority of the request is programmable from 0 to 3. Requests having the same priority are handled with a round-robin arbitration scheme. Time-sensitive requests should be assigned the priority 3, which is handled with a fixed higher priority scheme over the priorities 0 to 2. The residual bandwidth is shared by requests of priority 0 to 2 by implementing a weighted round-robin allocation for these non-time-sensitive channels. The different weights are monotonically resulting from the program channel priorities, the Q0 having the lowest weight. This slide and the next two clarify the relationship between the software settings and the hardware transactions for the low-power DMA. A program transfer at the lowest level is called an LPDMA single. An LPDMA single data width is 1, 2, or 4 bytes, as defined by the two LSBs of the SDW log 2 and DDW log 2 fields of the LPDMA CXTR1 register. Programming the binary value 1, 1 in these fields causes the user's setting error flag to be set. Note that the width is programmed independently for source and destination transfers. The addressing mode after each data of a LPDMA single is defined by the S-ink and D-ink bits of the LPDMA CXTR1 register, either a fixed addressing or an incremented addressing with contiguous data. The start and next addresses of an LPDMA source and destination single must be aligned with the respective data width. The user can configure the data handling between a data transferred from the source to the destination. The table lists all possible data handling from the source to the destination. If the destination data width is equal to the source data width, the source data is copied as is and transferred to the destination. Otherwise, it depends on the padding and alignment mode control bits. If the destination data width is larger than the source data width, the source data can be either right aligned and padded with zeros or sign extended up to the destination data width. If the destination data width is smaller than the source data width, the source data can be either right aligned and left truncated down to the destination data width or left aligned and right truncated down to the destination data width. There is no data manipulation between two distinct data transferred from the source before the destination transfer is generated. In this table, the time ordering of the data stream is conventionally taken with the first byte of data transferred being the lowest index B0. This timing diagram highlights the relationship between the software configuration of a channel and the transactions that are generated on the AHB Masterport. Two consecutive linked list items or LLIs are represented. First, LLI number N and then LLI number N plus 1. An LLI transfer can include a data transfer and a link transfer. The LPDMA supports a single transfer operation mode, the direct mode. A data transfer is a single data read immediately followed by a single data write because the LPDMA does not support FIFOs. Each single read followed by a write data transfer requires an arbitration cycle before being transferred over the AHB Masterport. The data transfer is a block transfer. In other words, a series of read followed by single transfers writes. The link transfer is composed of single data reads, each of them requiring an arbitration cycle and a transfer over the AHB Masterport. The link transfer updates channel control registers from values read from a structure in memory. This slide and the next six clarify the relationship between the software settings and the hardware transactions for the general purpose DMA. The GPDMA supports a single transfer operation mode, the FIFO mode. A program transfer at the lowest level is a GPDMA burst. A GPDMA burst is a burst of data received from the source or a burst of data sent to the destination. Since the GPDMA has two AHB Masterports, source and destination bursts can be executed simultaneously. The requested source burst transfer to the FIFO can be scheduled as soon as possible over the allocated port, depending on when the FIFO is ready to get a new burst from the source. The requested destination burst transfer from the FIFO can be scheduled as soon as possible over the allocated port, depending on when the FIFO is ready to push a new burst to the destination. Based on the channel priority, these ready FIFO based source and destination transfers are internally arbitrated versus the other requested and active channels. This table lists the main characteristics of a GPDMA burst. A source and destination burst is programmed with a burst length defined by the fields SBL1 and DBL1 respectively and a data width defined by the fields SDWLOG2 and DDWLOG2 respectively in the GPDMA CXTR1 register. Programming SDWLOG2 or DDWLOG2 with the binary value 11 leads to a user-setting error. The addressing mode after each data, named BEAT, of a GPDMA burst is defined by S-ink and D-ink for source and destination respectively, either a fixed addressing or an incremented addressing with contiguous data. The start and next addresses of a GPDMA source and destination burst must be aligned with the respective data width. When the source or destination address increment mode is selected, the address is automatically updated at the end of a burst with the burst size and byte units, which is equal to the burst length plus 1 multiplied by the data width. When the burst length is 1, the burst can be called a single. The programmed source and destination GPDMA burst is implemented with an AHB burst as is, unless one of the following conditions is met. When half of the FIFO size of the channel is lower than the programmed source or destination burst size, the programmed source or destination GPDMA burst is implemented with a series of singles or bursts of a smaller size, each transfer being of a size that is less than or equal to half the FIFO size. If the source block size is not a multiple of the source burst size, but is a multiple of the data width of the source burst, the GPDMA modifies and shortens bursts into singles or bursts of shorter length in order to transfer exactly the source block size. If the source or destination burst transfer crosses the 1 kilobyte address boundary on an AHB transfer, the GPDMA modifies and shortens the program burst into singles or bursts of shorter length to be compliant with the AHB protocol. If the source or destination burst length exceeds 16 on an AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of shorter length to be compliant with the AHB protocol. In all cases, the GPDMA ensures source and destination data and address integrity without any user constraint. This table lists the possible data handling from the source to the destination when the source data width is a byte. The source and destination data width of the programmed burst is byte, half word or word as per the SDW log 2 and DDW log 2 fields. The user can configure the data handling between data transferred from the source to the destination. The data handling that can be performed is byte-based source reordering, data width conversion by packing, unpacking, padding or truncation. If the destination data width is different to the source data width, depending on the padding and alignment mode control field, byte-based destination reordering. If the destination data width is larger than the source data width, the source data is either right aligned and padded with zeros or sign extended up to the destination data width or is FIFO-Q'd and packed up to the destination data width. If the destination data width is smaller than the source data width, the source data is either right aligned and left truncated down to the destination data width or is FIFO-Q'd and unpacked and streamed down to the destination data width. If dbx equals 1, and if the destination data width is not a byte, the two bytes are exchanged within the aligned post-PAM half words. For instance, the byte 7, byte 6 half word becomes the byte 6, byte 7 half word. If dhx equals 1, and if the destination data width is neither a byte nor a half word, the two aligned half words are exchanged within the aligned post-PAM words. For instance, the byte 7, byte 6, byte 5 and byte 4 words becomes the byte 6, byte 7, byte 4 and byte 5 word. This table lists the possible data handling from the source to the destination when the source data width is a 16-bit half word. This table lists the possible data handling from the source to the destination when the source data width is a 32-bit word. If sbx is equal to 1, and if the source data width is a word, the two bytes of the unaligned half word at the middle of each source data word are exchanged. For instance, byte 7, 6, 5, 4 becomes byte 7564. If the destination data width is larger than the source data width, the post-sbx source data is either right-aligned and padded with zeros, or sign extended up to the destination data width, or is a FIFO queued and packed up to the destination data width. If the destination data width is lower than the source data width, the post-sbx data is either right-aligned and left truncated down to the destination data width, or is FIFO queued and unpacked and streamed down to the destination data width. This timing diagram highlights the relationship between the software configuration of a channel and the transactions that are generated on the AHB Masterport. An ongoing GPDMA transfer can be a data transfer, which includes source and destination burst transfers, or a link transfer for the internal update of the linked list register file from the next linked list item. Two consecutive linked list items, or LLIs, are represented. First, LLI number N, and then LLI number N plus 1. The data transfer is composed of a series of burst data reads followed by burst data writes because the GPDMA supports FIFO. The GPDMA may modify and shorten bursts into singles or bursts of lower length, as explained in the previous slides. Each burst or single data transfer requires an arbitration cycle and a transfer over the AHB Masterport. The link transfer is composed of single data reads, each of them requiring an arbitration cycle and a transfer over the AHB Masterport. In addition to this presentation, you can refer to the other presentations on the GPDMA and LPDMA, DMA Overview, Autonomous DMA and Low Power Mode, DMA 2D Addressing, DMA Circular Buffering and Double Buffering, DMA Register File, DMA Error Reporting, DMA Linked List, DMA Input Output LLI Control.