 Hello, and welcome to this presentation of the STM32 Low Power Universal Asynchronous Receiver Transmitter Interface. It covers the main features of this interface, which is widely used for serial communications. The Low Power Universal Synchronous Asynchronous Receiver, or LPUART, provides full UART communications at 9600 BOD when the LPUART is clocked using a low-speed external 32.768 kilohertz oscillator, or LSE. Higher BOD rates can be reached when it is clocked by clock sources different from the LSE clock. Applications can benefit from the easy and inexpensive connection between devices, requiring only a few pins. In addition, the LPUART peripheral is functional in low power modes. The LPUART is a fully programmable serial interface with configurable features, such as data length, parity that is automatically generated and checked, number of stop bits, data order, signal polarity for transmission and reception, and BOD rate generator. It supports RS-232 and RS-485 hardware flow control options. The LPUART supports dual clock domains, allowing for wake-up from stop modes and BOD rate programming independent of the peripheral clock. The multiprocessor mode allows the USART to remain idle when not addressed. In addition to full-duplex communication, it also supports single-wire half-duplex mode. Here is the LPUART block diagram. The LPUART clock FCK can be selected from among the system clock, APB clock, high-speed internal 16 MHz RC oscillator, or the HSI-16, or the low-speed external 32.768 kHz crystal oscillator, or LSE. TX and RX are used for data transmission and reception. NCTS and NRTS are used for RS-232 hardware flow control. The driver-enable or DE signal, which is available on the same IO as NTRS, is used in RS-485 mode. The LPUART has a flexible clocking scheme. Its clock source can be selected in the RCC, and can be either the PCLK, which is the default clock source, or the HSI-16, LSE, or system clock. The registers are accessed through the APB buds, and the module is clocked with FCK, which is independent from the APB clock. The maximum baud rate that can be reached is 9600 baud when the clock source is LSE, and 26 megabaud when the clock source is at 80 MHz. The frame format consists of a set of data bits, in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start bit, S, where the line is driven low for one bit period. This signals the start of a frame and is used for synchronization. The data length can be 9, 8, or 7 bits with the parity bit counted. Finally, one or two stop bits, where the line is driven high, indicate the end of the frame. The previous slide described a standard frame. This slide shows an example of an 8-bit data frame configured with one stop bit. An idle character is interpreted as an entire frame of ones. The number of ones will include the number of stop bits as well. A break character is interpreted as receiving all zeros for a frame period. At the end of the break frame, two stop bits are inserted. The LP UART supports full duplex communication, where the TX and RX lines are respectively connected with the other interfaces, RX and TX lines. The LP UART can also be configured for a single wire half-duplex protocol, where the TX and RX lines are internally connected. In this communication mode, only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus, it acts as a standard I.O. in idle or reception states. For this usage, the I.O. must be configured with the TX pin in alternate function open drain mode with an external pull-up resistor. In the RS-232 standard, it is possible to control the serial data flow between two devices by using the NCTS input and the NRTS output. These two lines allow the receiver and the transmitter to alert each other of their state. This slide shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half-duplex communication. Both signals are active low. For serial half-duplex communication protocols like RS-485, the master needs to generate a direction signal to control the transceiver or physical layer. This signal informs the physical layer if it must act in send or receive mode. In RS-485 mode, a control line driver enable is used to activate the external transceiver control. DE shares the pin with NRTS. To simplify communication between multiple processors, the LPU-ART supports a special multiprocessor mode. In multiprocessor communication, it is desirable that only the intended message recipient should actively receive the message. The non-addressed devices may be put in mute mode using two methods, idle line or address mark. The LPU-ART can enter or exit from mute mode using one of two methods, idle line detection or address mark detection. The LPU-ART is able to wake up the MCU from stop mode when the LPU-ART clock source is the HSI-16 or LSE. The sources of wake up can be the standard RxNE interrupt or a specific event triggered by a start bit detection, an address match or whenever any data is received. Several LPU-ART events can provide an interrupt. The transmit data register empty flag is set when the transmit data register is empty and ready to be written. The transmit complete flag is set when the data transmission is complete and both data register and shift register are empty. The CTS flag is set when the NCTS input toggles. The received data register not empty flag is set when the received data register contains data ready to be read. The idle line flag is set when an idle line is detected. The character match flag is set when the received data corresponds to the programmed address. The wake up from stop mode flag is set when the wake up event, start bit or address match or any received data is verified. Several error flags can also be generated by the LPU-ART as shown in the table. The overrun, parity and framing error flags are each set when the corresponding error occurs. The noise error flag is set when a noise is detected on the received frame start bit. DMA requests can be triggered when received buffer not empty or transmit buffer empty flags are set. The LPU-ART peripheral is active in run, low power run, sleep and low power sleep modes. The LPU-ART interrupts cause the device to exit sleep or low power sleep modes. The LPU-ART is able to wake up the MCU from stop 0, stop 1 and stop 2 modes when the LPU-ART clock is set to HSI 16 or LSE. The MCU wake up from stop 0, stop 1 and stop 2 modes can be done using either a standard Rx and E interrupt or a WUF event. In standby and shutdown the peripheral is in power down and it must be reinitialized after exiting these modes. The STM32-L4 devices embed a single LPU-ART instance. Compared to the USART, the LPU-ART doesn't support synchronous, smart card, IRDA and LIN modes. It does not support the receiver timeout, modbus communication and the auto-bod rate detection features as well. This is a list of peripherals related to the LPU-ART. These refer to these peripheral trainings for more information if needed. General purpose input output, reset and clock controller, power controller, interrupts controller and direct memory access controller.