 Hello everyone. Well, it's a really full room. I think I see advantage of being after the chi-cad talk in between the new CAD tools. My name is Casper, and I'm going to talk about designing printer circuit boards using code. So hardware description languages and programming languages. So just a little bit about me. I'm a freelance electronic design engineer, and I love writing code, and I love open source, and especially electronics. These are just some of my projects, like my paid projects, which are not open source, unfortunately, but it is a Braille display and a VR chair controller. So you'll notice I said I like to code, and that I like hardware, but I didn't say I like designing hardware all that much. And it's very frustrating. I get very frustrated with designing electronics, and this is normally a summary of how electronics designs are done when I've given this presentation in the past, but I think after the chi-cad talk, I think we're all on the same page. So you normally have a schematic tool and a PCB layout tool, and you define your connections in your schematic tool, and then you root the connections in your PCB layout tool on a kind of physical model of your board. So if you're designing digital hardware, something to be run on FPGAs, you actually use schematic entry as well. But well, you can use schematic entry, but hardware description languages were invented in the 80s, and that's largely how people design digital hardware. The reason for this is because schematic entry for this kind of thing becomes really confusing. You can try and get this URL of this puzzle here and try and solve it. I haven't had time to do it myself yet, but it's not mine. It's someone, and it's available at that URL. So we use code to describe logic circuits, because it's much easier to manage the complexity. And so these are known as hardware description language, or HDLs, and that's for digital circuits. So schematic entry for PCB designs can be quite confusing as well, especially if we have high-pin-count components such as FPGA. And these days, the schematics use a lot of labels, and they kind of jump around all over the place. And it's often quite hard to follow the kind of the root all these signals are taking. So people have tried to extend HDLs for analog and mixed signal design, and Verilog A was designed in 1993, and it was merged into Verilog AMS in 2000. There's also analog and mixed signal extensions for VHDL, and some more experimental ones where I couldn't actually find implementations of. But these are also spiced, which I forgot last time I gave this to. But all of these are really about simulating, the actual behavior of your electronic circuits. And I suppose I'm interested in just replacing the schematic entry and making that easier. So all these details of what the actual behavior of the components are is too much detail, and it's going to be a lot more work than just defining the actual net list or schematics. So the question really is, what's so attractive about this? What about using code for designing circuits? And you're hoping for faster iteration cycles. And you're hoping to use programming constructs and tools for a better design process. And hopefully you could get modularity and reusability. So the first language that I came across that tries to solve this is PhDL, or the PCB Hardware Description Language. And this is what it looks like. It's quite a clean syntax for describing circuits, but it's its own language, so that does come with disadvantages. You don't have a general purpose language. And it's not as expressive as a general purpose language. It's from 2011. Like I said, it's a new language. The compiler is Java-based, and it has an IDE, actually, which will help you and guide you in your design process. And it can output EGLE and OCAD net list natively currently. And there's some conversion programs for others. But I haven't investigated it fully. So the next one I came across is Skiddle. And this was created in 2016. And it's a library and language in Python, really. So this is Python. What might confuse you a bit, if you're used to Python, is that there's some operator overloading going on there. And the plus equals has been overloaded to make connections. And there's kind of this implicit circuit in the background that's being built up. And then, if you use the generate net list command, it will produce a chigad net list. So Skiddle also has some provisions for reusing bits of subcircuits. And this is done through functions, really. So you'll notice that in the function, the arguments are the inputs and outputs of the circuit. So when you reuse a circuit, you apply the functions to your inputs and outputs. Another one that's quite fairly similar in some ways is PyCircuit, which was created a little bit later. And it's also embedded in Python. And it also outputs a chigad file, so it outputs chigad PCB files rather than net lists. So it'll have, this means it makes it a bit easier to have the footprints embedded into your output. So you don't need to worry about where your libraries are, which you would need to do, which you would need to, if you work from a net list. It also has the default way to do things in this modular way, with functions. And again, inputs and outputs are what you're parameterizing over when you have reusable bits. PyCircuit also does layout. So you can try and do layout with it. And it has some experimental support for hooking into SNT solvers to try and solve layout as a constraint problem, which is quite interesting. Still, it's experimental. So I've contributed a bit to these projects in discussing with the project creators. And I've started to make a playground for my ideas for what I would like in a circuit description language, really. And I decided to do it in JavaScript because we already have two in Python now. And this is what I've started working on. I call it replicad. And the goals are really to, much like the others, it's to make it easier to do schematic entry and make it easier to reason about circuits and also to confirm Atwood's law, which is that everything that can be written in JavaScript will be written in JavaScript. And I really want to get down to this issue of if it gets really hard to debug your circuit programs, really. So that's my goal with creating this to try and use setting analysis and electrical rules checks and really make it hard for you to introduce errors. Yeah, I have some other ideas there, such that if you look at this, the variable names are used as the schematic references. So the way I do this, the way I've played around with doing this is to use JavaScript language transforms, which then when you say my resistor is R1, and you just give the value of the resistor, and then in your schematic or in your output, really R1 will be that resistor. So I'm using kind of these language macros or processing to get that done. And there's an explicit circuit object. So with both Skiddle and Pi circuit, there's this implicit circuit object which is being modified. And here you have to say, I'm instantiating a circuit, and then I will add connections to it. And that's how when you add connections, you also then implicitly add the components to the circuit. Because why, why, yeah. And what I'm hoping to do is to do function arguments. So functions parameterize over not over connections, but over the values in your circuit. So this is a resistor divider, and you can instantiate new resistor divider with different values of different resistors. And then you return your circuit, and you can reuse that in another circuit. So some of these issues we've already touched on, but the pros really would be that you define everything once, and you reuse it, and you reuse programming constructs to make design easier. Some of the issues, it's hard to visualize what's going on. It is in the end a visual task, and you want to see where the connections are going. It can still be very tedious, and debugging could be a nightmare, and I've touched a bit on what I plan to do in replica for that. But on the subject of visualization, because with the schematics, I like reading schematics, but making them can be a pain. And I like reading good schematics. So really we want some kind of visual output from our programming, from our circuit language. So I added this graphless output to Skittle, and I kind of made it look a bit like a schematic, though I knew it would never look like a schematic. And that's kind of how far I got with it. It seemed like it would be OK for simpler circuits, but as things scale up, it could get problematic. PISA could already had some graphless visualizations as well. And the reason this looks like this is that there was a prototype for an interactive editor where you could click on different nodes. So all of these bits are really nice and clickable. And then it will highlight on your layout side what everything is. So fairly recently, I came across an Atlas SVG, and that draws SVG schematics from Joses, Jason's netlist. And they look amazingly good. So we tried to make an analog skin for netlist SVG. And these were some of the initial results we got from that, which is there's some oddities. You wouldn't necessarily draw it like this, but I think it looks very promising to me. And this is the most recent example of that, which was because David Coven has hooked up netlist SVG to PyCircuit now, and this is one of the outputs from that. So the other thing that I've been working on is, well, thinking about is we already have quite a specific language as electronic engineers. We already have a lot of words, and we'd like to really reuse that language when we're in our circuit description language. So the project, I came up with this, which is called Electrogrammar. And I probably don't have time for the demo. But pretty much it takes quite the descriptions that you normally use in your bill of materials or in your schematics, and it gives you a past output for that. So that means that it gives you a very quick way of defining components. And it's kind of, right now, this first version was JavaScript only, and it does capacitors, resistors, and LEDs, surface mount versions. It's a lax parser, so you can put things in any order. It understands what you mean, and it ignores invalid input. So it's useful for search applications, really, where you might say capacitor for my PCB design, one microfarad, and it will understand capacitor one microfarad and take that, and ignore the rest. So we're currently working on Electrogrammar version 2, which we'll be using Antelophore, so we will have parsers for JavaScript, Python, Java, C, C++, Go, and we could probably do C sharp. I don't know. Antelah has a lot of language outputs, and we've been expanding, well, David Craven has been expanding. David's doing a lot of work. He's been expanding it to diodes and transistors, and SMD and through-hole parts. Because even for transistors, we often have very structured names for them, so it's suitable. And we will do, well, it looks better, actually. Oh, here we go. Yeah, and we were doing a strict parser so that there'd be a version where you really have to put things. You have to say one microfarad and then 10% tolerance on one microfarad. And they really have to be in order. So should you use any of this? Well, it's all a bit alpha and experimental. So I think if you're interested in the subject, definitely look at these projects and try and contribute and try to get them into a better state. So this was all about schematics, really. And the title of the talk is short. And we're mostly talking about schematic net list entry. And of course, you can do other things with programming languages. And KyCAD ModTree is a Python DSL for KyCAD for prints, and that's being used in the standard library for KyCAD to generate things. There's QDA, which is a JavaScript utility for making complete libraries. And that's now also being integrated into PyCircuit. So layout, I already mentioned PyCircuit can do layout. And of course, you can do scripting within KyCAD. And you use your programming constructs that way to help you make tasks easier. So kind of back to this. We've addressed some of these, but just on the third point, the modularity and reusability. There's obviously other ways. You don't necessarily have to use programming languages to make reusable bits of circuit components. And you can also, diffs would be another great thing that would be great to do in, that you don't necessarily need code for diffs. You can do visual diffs. But kind of on the subject of reuse, this is my other project, which is Kidspace.org, which has reusable bits of completely defined projects that you could possibly reuse. And it would be interesting to expand this to have support for using this as a kind of NPM or a module repository to pull in bits of circuits into your circuit. That's me, actually. So I could maybe do the demo. I'm 18, it says 18 minutes. I'll try and do the demo while you think of questions. Yeah, so this is the demo of Electrogramma. That's not Electrogramma's fault. It's frozen. OK, I think I'll take questions. The typical test that a 49er would do with the ERC, I didn't see anything. You just said go directly from the description language to the net list or a VKAD board file. But it's kind of common for people to do things like make sure they don't have outputs tied together or how a plane's tied together before they do that in a typical traumatic area. Is that something to provide? I'm aware that. So the question is whether ERC checks are provided in any of these circuit description languages. And I'm aware that definitely for Skiddle and PyCircuit, they have built-in ERC functions. And it's something, for replica, it's not done yet. Obviously, I'm just starting out with it. But it's something I really want to focus on kind of seeing where static analysis ends and where the ERC checks begin, really. The closest thing, the question was whether there was a kind of integrated solution for visualizing the PCB and the schematic and the PCB and the code in one kind of package. And I know Dave Curven again from PyCircuit is working on a viewer. I will be as well. For replicat, we'll probably collaborate on this somehow. There's nothing ready yet. Put it on the use of that to try to do simulation layout of the schematic on the same file. They're basically just using a handful of if-desks to direct it so that you can actually get all three in a single file. Yeah, I'll have to. Unfortunately, I haven't really had the time to follow through on it. So it actually makes some translation. But the idea looks attractive. So I mean, the question, the statement was that there's layout information. There's possibility to do layout with Varylog AMS. I haven't looked too closely at Varylog AMS because it seemed like it was very targeted at simulation. And that's not what I was interested in. Yeah, I will also check out your presentation. But not before then.