 Hello, and welcome to this session on peak microcontroller serial communication module USART. Myself, Mr. Vipul Kondekar from Vulture Institute of Technology, Sholapur. So, these are the learning outcomes of this video. So, these are the contents of the presentation, introduction, then the various control registers like TX, STA, RCS, TA we will discuss. Then, border generation, we will go for how we can have standard border generation for the peak microcontroller. And then we will go for the transmit block diagram as well as receive block diagram for this USART module. Now, this universal synchronous, asynchronous reception transmission module, which is also called as SEI, serial communication interface module. So, for peak microcontroller, this USART module can be configured in the following modes. You can have a synchronous communication, which works like full duplex, which can be used for communication between a microcontroller and computer, or microcontroller and CRT, etc. Then, it supports synchronous communication also. So, where this microcontroller can behave like a master or slave. So, synchronous master, synchronous slave, these are the other two modes of operation. But if you are working in synchronous mode, the communication will be half duplex communication. Now, when this module is available in peak microcontroller, what are the important blocks present in that module are border generator circuit and sampling circuit as far as the reception is concerned, and then a synchronous transmission block as well as a synchronous reception block. When you are doing this a synchronous communication or a synchronous communication by using this USART module, so there are two pins of microcontroller used. So, you are using this port C pin number 6 and port C pin number 7. And then in order to configure these port pins, you will be taking the help of tree C bit number 6 and bit number 7. So, these are the direction control register bits. As well as there is one bit available in TC-STA, which we will discuss in this particular video bit number 7. So, these are the control bits for this particular USART module. Now, let us go for understanding. If I want to make the use of this USART, I need to take the help of these registers to configure this particular module either in synchronous or asynchronous mode. So, let us go for understanding. One spatial function register related to this asynchronous communication is TX-STA. TX-STA stands for transmit status and control register. Let us go for understanding what is the significance of the bits present in TX-STA. This register will be used whenever you are doing the transmission of the data. It starts with CSRC, it is a clock select bit. This is basically used in case of synchronous communication. So, when it is a master device that will make this particular bit 1, if it is a slave it will make that bit as 0. For asynchronous communication, this particular CSRC is not used. Now, next comes TX-9. So, when you are doing the transmission, so if you are preferring 9-bit transmission along with 8-bit data, if you are transmitting 9-bit, that 9-bit may be used as a parity bit for the error control or that may be used for addressing. So, if you are using that 9-bit transmission, so this bit has to be enabled and whatever 9-bit you are transmitting for your data, that bit will be present here. This is TX-9D. So, this will be the 9-bit which will be transmitted. But for that, this TX-9 has to be enabled. So, this has to be made 1. So, RW-0, what it indicates here? Means this particular bit of this special function register, here you can read, this location you can read, here you can write as well as the slash 0 indicates that reset status means after reset this bit is 0. Means by default you are preferring 8-bit transmission. If you want to have 9-bit transmission, this TX-9 bit has to be made 1. Then transmission enable bit. So, this bit also has to be set. Then sync bits, it is used for synchronous communication. If it is synchronous communication, this will be 1. Then there is this bit is unused. Then this particular bit number BRGH. BRGH is related to the board rate selection. So, we will discuss when we will discuss that board rate generation that what is the significance of this BRGH bit. Then TRMT. So, TRMT is one flag. When you are doing transmission, so you are writing that data into the shift register. So, that parallel data will be converted into serial and then it will get transmitted onto the pin. But how you will come to know that the transmission of the data is over? So, this is the provision made here available here. The transmission shift register is empty. This particular bit is made 1. This is 9-bit already we have discussed. If this particular bit is enabled, so this will be the 9-bit which gets transmitted. Now, this is the register. One more register which is used at the receiver side. So, when you are doing the reception, this particular register you will be dealing with. This SPEN. So, it is serial port enable bit. When you are using this serial communication, this has to be enabled. When you are doing 9-bit transmission, TX9 will be enabled and 9-bit virtual transmitting will be TX9DA. On the same lines at the receiver side, if your 9-bit transmission is there, reception also has to be enabled for 9-bit. So, this is RX9, enable 9-bit reception and whatever that 9 transmitted bit is at the receiver side will go into RX9. Then it is single reception enabled bit. So, this is basically used for synchronous communication. If you want to have single byte reception, so if you can enable that particular reception or you can disable it. And this is CRN, this continuous reception enable or disable bit. Now, this USAR model provides one facility of having error control. So, there is one possibility of framing error. Means, whatever frame is formed is not in the proper format. So, it can get reflected as there is error in the frame format. So, that is one bit framing error bit. As well as overrun error bit is there in RC-STA. This is RX9D. So, these are the two special function registers which we will be using for a synchronous as well as synchronous communication. So, when you are preferring a synchronous communication, there is one important aspect that the board rate of the sender as well as the receiver should be same. Now, the thing is there are certain standard board rates and then your microcontroller should be able to transmit the data at those standard board rates. Now, how we can decide the board rate for the peak microcontroller? So, basically if you are using this SYNC bit as 0, means you are preferring a synchronous communication. In a synchronous communication there are two possibilities BRGS bit is 0 and BRGS bit is 1. Already we have seen that BRGS bit is present in TXSTA register which is used for board rate selection. So, let us try to understand how we can have board rate decided board rate. Board rate is decided by this formula. Board rate is equal to oscillator frequency divided by 64 into X plus A. What is X plus 1? What is X here? X is the value which you load in one spatial function register called as SPBRG register. So, that is 8 bit register. So, that can take any value between 0 to 255. So, you can load that X value and oscillator frequency and based on that you can generate certain board rate. Only thing is if I am making BRGS bit as 1, then this becomes the formula for board rate generation in the asynchronous mode. And in synchronous mode if BRGS is 0, then this is the clock which is used for synchronous communication. So, this will be the clock generated FOSC divided by 4 into X plus 1. So, these are the formulas for calculation of the board rate. Now, let us go for one example. Calculate the value of SPBRG register. So, what value I should load in SPBRG register? So, as to get this standard board rate 960 formation is available. So, this is how we can do the calculations for the value which is to be loaded in SPBRG register for getting a particular board rate. Now, think what is the significance of this BRG? Now, this is the block diagram for the transmitter side. You may see when you are doing the transmission, these are the blocks involved. So, whatever data you want to transmit, you will go to TXREG register and then it will go to the shift register where that parallel data will be converted to serial data and that will be made available onto the PIN based on the status of the enabling of the serial port enable. As well as this status of this transmission shift register is reflected if it is becoming in empty, this will be made work. As well you know that when you are doing the transmission, you need to generate the board rate. So, SPBRG value is used and TXEN has to be enabled and then based on SPBRG value, it will generate a certain board rate. So, that board rate will be the clock used for the transmission. Along with that, then the data will be available serially onto this particular PIN. Along with that, it is possible that the transmission of the asynchronous module may result into interrupts. So, TXIF flag bit is set, provided that transmission interrupt is enabled. So, when this particular flag bit is set, when the transmission is complete and if the flag is enabled, it can result into interrupt also. On the same lines, what happens at the receiver side? So, whatever transmitted data TXPIN will be connected here at the RX side. So, there will be a buffer and control. So, that will be controlled by serial port enable bit and then the data is recovered by doing the sampling. Remember that when you are recovering the data, you need to generate the clock again at the receiver side. So, again board rate generator will be there at the receiver side and then whatever data are received, that will go into a receive shift register. And then if it is a 9-bit reception, so that transmitted 9-bit will be again stored in RX 9-bit and remaining 8-bits will be available here. If there is some error, so that is reflected in framing error, if framing error is there, if error bit is there, in RX STA, so that gets a set. Overrun error, if collision occurs, this particular flag bit is set. And then otherwise, if the reception is successful, if 9-bits are transmitted, 9-th received bit is available here, 8-bits are available here as well. This may result also again into the interrupt. So, RCIF, if that particular flag bit is set, when the reception is successful and then that particular interrupt is enabled, this user receive module also may result into interrupt. So, this is how the synchronous and asynchronous communication module where we have seen how we can have transmission in asynchronous mode and reception in asynchronous mode with the help of block diagram. So, these are the references used for this presentation.