 Hello, and welcome to this presentation which describes the control of the input and output signals of the GPDMA and LPDMA channels. The DMA-CXTR2 register defines the input control, request, or trigger events, and the output control transfer complete event of the transfer handled by the Channel X at the LLI level. This enables a flexible event-driven and hardware-based scheduling of a transfer under the global control of the software. In the figure, a timer is used to trigger the transfer of the data received by the SPI module. When this transfer completes, a link to LLI2 is performed. The LLI2 handles an I2C transmission. When this transfer completes, a link is performed to restore the settings related to the SPI receive transfer. When the next time-out occurs, this sequence repeats. The inputs of a DMA channel are the request selection, for example, the SPI-RX and the I2C-TX signal in the figure. The trigger input, a programmed DMA transfer, can be triggered by a rising falling edge of a selected input trigger event. For example, the time-out in the figure. The transfer granularity condition by the trigger can be either the burst level or the block level, or the 2D repeated block level for Channels 12 to 15, or the link level for the GP DMA. The transfer granularity condition by the trigger can be either the single data level or the block level, or the link level for the LP DMA. The output of a DMA channel is the transfer complete event, which can be used as a trigger input of another channel for inter-channel transfers chaining. Unlike the related software transfer complete flag, the software does not need to acknowledge and clear the transfer complete signal. The transfer granularity for the transfer complete event generation can be either the block level, or the block level, or the 2D repeated block level, or LLI level, or the channel level for the GP DMA. The transfer granularity for the transfer complete event generation can be either the block level, or LLI level, or the channel level for the LP DMA. This timing diagram illustrates the trigger hit, the trigger memorization, and the trigger overrun in the configuration example with a block level trigger mode and a rising edge trigger polarity. The DMA monitoring of a trigger for a channel X is started when the channel is enabled or loaded with a new active trigger configuration, rising or falling edge on a selected trigger. The monitoring of this trigger is kept active during the triggered and uncompleted transfer. In this timing diagram, the first rising edge of the trigger starts the transfer because the peripheral request is active. If a new trigger is detected, this hit is internally memorized to grant the next transfer as long as the defined rising or falling edge and trigger selection are not modified and the channel is enabled. This is the case for the second rising edge of the trigger. It occurs when the first transfer is in progress. The second transfer is then triggered and starts when the peripheral request is asserted. This is the state called fire in the timing diagram. After a first new trigger hits N plus 1 is memorized, if another trigger hits N plus 2 is detected, and if the hit N triggered transfer is still not completed, hit N plus 2 is lost and not memorized. A trigger overrun flag is reported and an interrupt is generated. This is the case for the fourth rising edge of the trigger. The second rising edge is used to start the second block transfer. While this transfer is in progress, the third rising edge occurs and is memorized. Then the fourth rising edge causes an overrun condition because the second transfer is not completed. Note that the channel is not automatically disabled by hardware due to a trigger overrun. Transferring a next LLI N plus 1 that updates the DMAC XTR2 with a new value for any of trigger selection or trigger polarity. Resets the monitoring, trashing the possible memorized hit of the formerly defined LLI N trigger. In addition to this presentation, you can refer to the other presentations on the GPDMA and LPDMA. DMA overview. DMA transfers hardware and software views. Autonomous DMA and low power mode. DMA linked list. DMA circular buffering and double buffering. DMA 2D addressing. DMA register file. DMA error reporting.