 Hello, and welcome to this presentation of the ARM Cortex-M0 Plus Core, which is embedded in all products of the STM32G0 microcontroller family. The Cortex-M0 Plus Core is part of the ARM Cortex-M group of 32-bit RISC cores. It implements the ARM V6M architecture and features a two-stage pipeline. The Cortex-M0 Plus has a unique AHB light masterport, but supports concurrent instruction fetch and data access when the data access targets the fast IOPORT address range. STM32G0 microcontrollers integrate an ARM Cortex-M0 Plus Core in order to benefit from the incomparable performance per milliwatt ratio. All Cortex-M CPUs have a 32-bit architecture. The Cortex-M3 was the first Cortex-M CPU released by ARM. Then ARM decided to distinguish two product lines, high performance and low power, while maintaining the compatibility between them. The Cortex-M0 Plus belongs to the low-power product line. It's designed for battery-powered devices, very sensitive to power consumption. The Cortex-M0 Plus Core delivers more performance than the Cortex-M0 Core, thanks to the two-stage instruction pipeline. Let's start our description of the CPU by the processor core in charge of fetching and executing instructions. Most V6M instructions are 16-bits long. There are only 6 32-bit instructions, and most of them are control instructions, rarely used. However, the branch and link instruction, which is used to call a sub-program, is also 32-bits long in order to support a large offset between this instruction and the label pointing to the next instruction to be executed. Ideally, one 32-bit access for every two 16-bit instructions results in less fetches per instruction. During clock number two, no instruction fetch occurs. The AHB light port is available to execute a data access when instruction N is a load-store instruction. On a given branch, fewer pre-fetched instructions are wasted thanks to the two-stage pipeline. In clock number one, the processor fetches instruction zero and an unconditional branch instruction. In clock number two, it executes instruction zero. In clock number three, it executes the branch instruction, while fetching the two next sequential instructions, instruction one and instruction two, called branch shadow instructions. In clock number four, the processor discards instruction one and instruction two and fetches instruction N and instruction N plus one. Cortex-M0, M3 and M4 implement a three-stage pipeline, fetch, decode and execute. The number of branch shadow instructions is larger, up to four 16-bit instructions. The Cortex-M0 plus has neither a cache nor internal RAM. Consequently, any instruction fetch transaction is steered to the AHB light interface and any data access is steered either to the AHB light interface or the single-cycle IO port. Note that the STM32G0 implements a SOC-level cache, external to the CPU. The AHB light masterport is connected to a bus matrix, enabling the CPU to access memories and peripherals. Since transactions are pipelined on AHB light, the best throughput is 32 bits of data or instructions per clock with a minimum two-clock latency. The Cortex-M0 plus also features a single-cycle IO port, enabling the CPU to access data with a one-clock latency. An external decoding logic determines the address range in which data accesses are steered to this port. In the STM32G0, the single-cycle IO port is used to access the GPIO port registers, enabling these ports to work at the processor frequency. When the address of a load or store instruction does not fall into the single-cycle IO port address aperture, the transaction is performed on the AHB light port, preventing the CPU from fetching instructions in the same clock. When the address of a load or store instruction falls into the single-cycle IO port address aperture, the transaction is performed on this port, possibly concurrently with an instruction fetch. In the Cortex-M0 plus core, the memory protection unit, called MPU, is used to protect address ranges according to the configured access permissions. The MPU in STM32G0 microcontroller offers support for eight independent memory regions with independent configurable attributes for access permission, allowed or not read-write in privileged unprivileged mode, execution permission, executable region or region prohibited for instruction fetch. For more details, please refer to these application notes and the Cortex-M0 plus programming manual available on st.com website. Also visit the ARM website, where you'll find more information about the Cortex-M0 plus core.