 Hello, welcome to the session on cache memory principle. I Mr. Dayanand Patil, working as assistant professor in department of computer science and engineering, Walsh and institute of technology, Solopu. At the end of this lecture, we will be able to explain the cache memory principle and differentiate between the main memory and the cache memory. What is cache memory? That cache memory is a small and high speed RAM that is located between the CPU and main memory. This memory is small compared to the primary memory and the secondary memory and it is much the speed is high compared to the primary memory. The cache memory holds a copy of instructions that is currently being executed. We are already familiar with the basic concept of the memory while executing the program that program will be loaded from main memory to the secondary memory to the main memory. So after loading to the main memory, CPU will access those instructions from main memory and it will execute. So, while accessing from main memory that instructions which are currently being used, those are loaded into that cache memory. That cache memory will hold that copy of the instructions currently being executed. When those instructions are repeatedly used, those instructions are accessed from the cache memory only. The main purpose of cache is to accelerate the computer speed because that cache memory is speed is very high compared to the primary memory. If the instructions are copied in a cache memory, if it is repeatedly used, so that time that CPU will access those instructions from the cache memory, so that time that speed of execution will be increased. So, while considering this reading the instructions from the cache, these are the two important term that is cache hit and cache miss. That cache hit is when that executing application needs the data and that data will be find first in a cache memory. If that data is available in a cache, that if that data is accessed from the cache that no need to access the main memory for that instructions. So, if that data is available in cache memory, that cache hit occurs. That cache hit means the data which is required for that executing applications. If it is found in cache memory, so that is the cache hit. So, then cache miss is when the application needs a data and that data that data does not find in a cache memory, then that CPU needs to access that data from the main memory and it will execute. So that accessing that data from the main memory will be slower. So, if that data does not find in a cache memory, we will say that that is the cache miss. Here we can see that CPU that cache is located between the main memory and CPU. So, that word if it is found in a cache that word is transferred in the CPU and cache. If that CPU is accessing the main memory in case of the cache miss, it is accessing that block from the main memory at a time. In the next slide we will see that what is block and what is word transfer. So, to calculate the hit ratio, so that formula for the hit ratio is total number of hits divided by total number of hits plus total number of miss. This we can say that total number of access, either it might be cache or main memory. So, that total number of hits occur divided by total number of hits plus total number of miss is the hit ratio. The cache or main memory structure. Here we can see that. So, assume that this is that main memory structure and this is the cache memory structure. So, here So, here we can see that main memory is divided into the equal number of sorry the number of words the size of each word is same. So, we are saying that this is the word length usually it will be 1 by 2 by 4 by but here we are not interested in the size of the word. So, here we can assume that that size of each word is 1 by if I use the word 1 by or 1 word they both are same here in this lecture. So, it is divided into the number of words the length of each word is same and again this memory is divided into the block. So, here in this lecture we are assuming that the number of words are divided into that 1 block equals to the 4 words that memory is again divided into that number of blocks each block containing the 4 memory word here we can see this is the zeroth word this is first word second word third this is the binary address this these first 4 words are considered as 1 block. So, these are binary address up to 2 raise to n minus 1 here the n is the number of bits used to give a binary address for each word. So, based upon the memory size we are using the number of bits to address each word in a main memory. So, these blocks whenever that CPU access the main memory it will read that 4 blocks at a time and loaded into the cache memory. So, here this is the cache memory we are considering. So, that block length that block length means the CPU will read the 4 words that is 1 block at a time it is loaded into the cache memory we are saying these are the cache lines zeroth line first line second line up to c minus 1. So, that it will be divided into 4 words as a 1 block and it will be loaded into cache and whenever it will read the 1 block that is loaded into the cache line that the size of the cache line equals to the block size of the main memory. So, 4 blocks are read at a time those 4 blocks are loaded into each line of the cache. So, these are the line number this tag and this is block the block is that 4 words are loaded into the block and what is this tag. So, here we can see these are this is the minor address of each word. So, this based upon that size we are using the number of bits, but always last 2 bits identity the 2 bits are identifies that block number the word number in each block. See this is the zeroth block in the zeroth word in the first block this is the first word in the first block second word in the first block third word in the first block next again see here we can zeroth will repeat here zeroth this is zeroth block from the next zeroth word from the next block first word from the next block second word from the next block. So, so on. So, this will repeat again for the next block. So, these are these last 2 bits identifies the word address in each block. So, the remaining bits will be common for each block here you can see the MSB 6 bits are same for zeroth block again the next 6 bits are same for next block. So, these MSB 6 bits are considered as tag address and this will identify each word we will see the next video lectures. So, this tag address hold which block that word belongs to and if that tag address is present in any of these cache lines then all those blocks in that line belongs to that is stored in the cache line. This is time to reflect the question is the total number of memory access is given that is 12 and heat ratio is given 0.5833. Now, we need to calculate the total number of heat and total number of miss that we have as we have discussed the formula is the heat ratio equal to total number of heat divided by total number of hits plus total number of miss the total number of memory access is given that is total number of heat plus total number of miss and the heat ratio is given that 0.583 0.583 divided by total number of hits divided by 12. The total number of hits equal to that 12 into 0.583 is 7 and the total number of misses that is 5 is the total number of miss this is the simple mathematics. So, you can calculate from the given parameter that basic principle of that cache memory. So, starting CPU request the content from the main memory location if the CPU request for the main memory location first it will check for that required data whether it is available in a cache. If it is found in a cache then we say that cache heat that access from the cache. If not present read that required block from the main memory and that block is loaded to the cache and deliver it to the CPU parallelly. I cache includes that class includes tag to identify which block of main memory is in a cache slot just we have see that first we will check for the that cache tag and if that block address is found then the all words in that block will be present. We will see in the flow chart. So, this is start at the starting that is CPU will generate that receives that address that array from the CPU that CPU generates the read address. So, that based upon the read address it will check whether that block is containing in a that read address is containing a cache that the tag address available with each cache line. So, if the tag that block address is available in the cache tag means all the words are available in that clashed cache block. So, then the next step is if it is yes then fetch that required address word from the cache and deliver to the CPU and that execution is done and what in case of no. So, if it is no if that block is not available so that access the main memory from that access that particular word from the main memory that containing in which block and then allocate cache line for that main memory block once that it access that block from the main memory it will allocate that cache line for that particular block from the main memory and that block is loaded into the cache. Here the two tasks are performed parallely that one that load main memory block to the cache and deliver that required address word to the CPU. So, after performing these two tasks so that it will complete and that is done. So, this is the cache read operation that is flow chart for the cache read operation or that cache memory principle. These are the references I have referred. Thank you.