 We are doing already frequency response of amplifiers. Today we start with the first of the most important device of analog which is an operation amplifier nicknamed, short named opamp. We want to talk about, of course I will show you little later. This is a figure which I am showing you which is a sketch for two stage opamp. There is a possibility of Thursday in real opamps which is right now put dotted one, okay. The first stage is essentially what we call high gain stage which is followed by another gain stage which is basically high swing stage and then it is connected to buffers which is typically push pull types, output amplifiers as they are called and that gives the output to you. Next opamps used are single ended. What does that mean? The output is only at one output. There are no differential two outputs, okay. But let us say if you wish to have two outputs there are possibilities and I will show you one circuit which does that. So a CMOS opamp which is either double ended or single ended. Normally if it is double ended you use current source biasing and if you are using single ended opamp normally it is current mirrored biasing, okay. Normally it is not necessary you can do any kinds of biasing but normally it is done through current mirrors. This normal word should be taken seriously because not every circuit uses exactly the way I say individual requirements may push you to some other ones, okay. So this is typically what we want to know. So what is the first stage, second stage and third stage which allows you to do this kind of features, high gain followed by high swings and then finally the buffer out. Buffers are always required for driving larger loads, okay. And in the case of MOS circuits 99.99 they will be capacity loads. So you are driving a large capacitor which may be the input capacitance of the next chip or next stage of the circuit, okay. And like in the case of digital circuit we typically expect the load at least 4 times these yawks which is called FO4 loads. So even in this case at least whatever the highest capacitance you put 10 times CL so that becomes the maximum possible load. But in general in our design right now we will specify for what load this needs to be designed. The features of OPAN will discuss when we start designing OPAN what exactly the parameters we are worried about like gain CMAR, bandwidth and what else. But let us do some basic thinking on this. So once I declare that I want a high gain stage the possibility of such high gain stage is either through a cascode amplifier but it will give only generally single ended outputs and require large power dissipations. So we will go for DIFAM. So the first stage of OPAN is normally a differential amplifier or difference, okay there is a word I keep saying differential amplifier and a difference amplifier I will differentiate later. But in looks sometimes they are same, sometimes they are not. The difference amplifier is essentially outputs are also different. Two outputs, two inputs which are required in many filter organizations, okay. So first stage is a DIFAM which whose output can be single ended or can be double ended and it is given to another stage which is normally high swing high gain stage. Most of the gain picked up here the rest gain is picked up here plus swings are improved. Then there is a last stage which I am showing you buffer, output buffer or this output amplifier. Typically it is pushful kind but not necessarily everywhere but take it normally it will be a pushful. What does pushful means? Are you have the top transistor will be on or the lower transistor will be on, okay like a normal output stage of any digital hardware. So that is the but the importance there is they can drive larger capacitance because they can provide larger currents, okay. Yes. Sir, arc line is a high swing. Yeah, it is a gain stage but it gives the output swings. V out max V out min is picked up from there, okay and not from the DIFAM stage, okay. Is that clear? Then in most op-amps for the case of stability or by without doing thinking over it there will be a feedback capacitance connected. CGDs for example always there or other parasitic capacitance may appear which may give you output to input connections at the at least the output stage, this stage and in that case you will have a feedback. Now this feedback also creates feed forward, okay. So in all our analysis we try to avoid feed forward situations, okay. What does feed forward can give you? A 0. So we are trying to see that 0 does not appear at least in the range of frequencies where we wish to operate. Now the feedback is what we few days, few minutes we will discuss later but if you see carefully this, if you look at the DIFAM, the first two transistors may be here is may I put it, new slide just for the heck of it. Just look at either of them. This M1, M2 receives input voltage and converts them into GMV1, GMV2 kind of currents. So this is essentially called V2I converters. When these I's are fed to these they give an output which means current to voltage converter starts here. Is that clear? This block is V2I converter, this block is I2V converter, okay. So this first two stages, DIFAM has two parts, one is the V2I converter part, the other is why I am giving you these figures but this is how one designs, which area we are looking into, okay. So the first part is converter from V2I, they are the I2V which together makes DIFAM followed by a gain stage like shown here or shown here. Now this gain stage you can see from here since this is an output, M5 is receiving VGS and therefore converts currents. So next stage of this is a V2I converter and that current passes through M6. So this will then give you I2V converter at this output, okay. So typical OPAM, two stage OPAM has two V2I and two I2V converters, okay. Is that point clear? This is only a statement, nothing very big just to tell you how fundamentally one should look the circuit from inside. Is that okay? So first is V2I then I2V then V2I and then I2V, this is a two stage OPAM. The two possible, of course they are minimal but these are the two most popular ones which are used in OPAM designs. This is a double ended output and this is a single ended output. So in this, this is your DIFAM. Now since it is not diode connected, so normally current is not mirrored, actually you apply through VB another transistor and create ISS and you also bias this VBB these to make it current sources, okay. So as just W by L of the last transistor to suit this currents which is going to go down. Is that not the other way? The VB and W by L of this is so adjusted that the currents which I am receiving from the current source are essentially received at the ISS which you want to use as a design spec, okay. So since this is from where VB I can create voltage reference preferably if you want a very nice stable reference, band gap reference or at least VT references. You can see it is a double ended so one output is taken here, one output is taken here and then you have two single stage output stages which is essentially the same one which is in the single end also. So I can create a VO1 and VO2 and if I choose M5, M6 not identical I will have VO2 separate from VO1, is that clear? So I have a double ended output of my choice which is proportional to input voltage VIN, is that clear? Please remember I can make a ratio of this, I can make a ratio of this and can change the currents in this and therefore VO1 and VO2 that is V2I and I2V converter can be modified to suit different VO1 and different VO2 for the same input VIN. This is essentially double ended output if all are equal then the VO1 will be equal to VO2 then you do not need that. If you are using same then why do you want to? At times you still need to, in a layout it is sometimes preferred to have same output going other two sides so you may as well use this but that does not help too much because it consumes power for nothing. So this is a, as I said not very often used but if needed can be employed in many opiants they are specific opiants which gives you double ended outputs. Many of the LM series which is a low noise opiants they are double ended outputs. Even 8576 is also double ended very famous low power low noise device. This is the one which is most of the 741 series 741, 747, 725, 723 whatever standard opiants you see in the labs they uses single ended outputs, a diffam whose load is decided by diode connection. We have already done analysis for this. We have also done this individually so it is not that they are too different it is only a question of load which you put there. In these cases most times both this M6, M7 if there are any other stage are driven through a current mirror the biasing is not shown here. So there will be a biasing circuit which will give you a current mirror and that same output is connected to a mini transistors as you want to have same currents is that correct? Okay so when I start looking into this design all that I have to design is the W BIOS of this and W BIOS of this to meet specification. What else I can design the size of M7 which may design the RSS or RSS values okay. Because I can mirror whatever current I want is that clear? I do not have M7, M6 same either I can have different M6, M7 if need rises normally I will not do that but if I need I can do that because I just have to make different W BIOS for this. The problem there is different how much will be decided by this because this is going to push the current. So it is not too much in your hand okay. Is that okay? Okay so my end product is OTAN will be given some specification to me and all that I will design or I will get an output is sizes of all transistors okay that is what design is about because once I know the size they are not done layout may be in between before we go details one class on the design layout may be helpful just a minute I will come back to it. A typical transistor I already said this is a black line which is think it is red or pink it is a gate this is a green line which is diffusion this is source drain gate this is essentially what you are doing this is the transistor cross section those drain and if you have window here let us say oxide on the top and contact here so I can open a contact here these are all oxides contact here this may be my drain this may be my great and this may be my source so I can open a window inside this and make a metal contact on this I can open a window here and I can put a metal contact here I can open a window here cut and I have a contact here this is called layout what is the transistor length and width here from the this is length and this something is width so what do you show here which is your length and which is your width obviously the poly thickness is your length and poly width on this diffusion width are essentially a width of transistor so this is essentially convert this is what I designed from circuit and once I design I give you designs they transfer it on the silicon to create this actual structures so my gate at the end for any designer is to create patterns that is what all that we are going to do at the end so what do I need lengths and weights if you give me this I will be able to draw the correct sizes of transistors and if that is so I believe that the technology people can translate what I said on silicon and therefore the performance should actually be as values of W well I have chosen if it does and I will took something and come back once again that is called turn around so this please remember so as a designer we are our output is only sizes okay some specification electrical special given using all that circuit analysis we should arrive at sizes and of course connections because to transistor how will we connect them how many points will go on a single load so this is another connectivity problem which is interconnects so all that we design is the W by L for transistors and possible interconnects interconnections of thickness and widths because that will decide R and C for the circuit so these are all that we design as from a designers point of view technology people pick up this mask actually print one by one and typical process is around 24 mask for a standard CMOS if you want extra anything else you thought I should do another this another mask it may go as high as 32 mask in some cases each mass cost hell hell of a means millions and dollars so do not just say I could put another window and do something because that may cost the profit to expenses is ratio which people calculate in D1 they may do that extra also because D runs should be sold in millions same way they may say do it in my purpose because they are off shell any number are sold okay but if you say some specific chip they will be sold hundreds or a company only will buy that much or 1000 2000 then you cannot put extra money okay so vendor will decide what we will do so exactly as a designer my job is only to get sizes okay interconnects I believe I can independently handle those not really easy that is becoming the worst part right now but for the sake of NLM right now I say okay I am interested right now in W buyers of the oil transistor which I see and if I put their values I can create this and if I create this I believe that technology people will be able to translate into a actual silicon chip that is the output from us transferred to actual circuits is that clear so please remember for us it does not matter any other thing is not relevant for us of course you may have limitation of bandwidth you may have limitation of gain powers lee rates we are max we are mean ICMR you may put any PSIR CMIR you may put any number of constraints or specs for you but at the end of this what best among them you can get for the design you are asking find W buyers for all of them so I will give a opamp design later for those who have access to SMDP sites otherwise ask someone who works in VLSL lab there is already an opamp design sitting on my SMDP site under one course which I did from IEP is called there is an opamp design for a butter I will actually change my specs for your course so that it is not be identical but the method will remain same so those who wish to see that can even now see that okay it is around 10-12 pages of 15 slides or more more just to show you how designs go at the end okay is that pointless of what is our is having taken a circuit and given specification okay this is also our choice this one this one any other architecture you can choose either depend on your thinking but then this it should meet the given specs for given technology node as well because you will be specified 0.25 micron process 0.35 0.18 or 96 whichever technology they say that must conform to that technology node what will change there beta beta dash will change vts will change power supply will change so many parameters and their variations will change and therefore the design will become even tougher as I go down in the node values okay so designing 0.35 is the ideal or 5 micron will be the best because everything will work so when we design why we choose 5 micron but then we are sure that in case per say you translate I assure you 100% it will work okay but if someone does it on 45 nanometers me and you will keep kissing may or may not okay that is the problem with technologies okay so having shown you is to hardware part this one which I am going to use now okay and there are two stages the defam stage in a output stage second gain stage so the net gain is everyone into AV2 AV1 is nothing but the gain of a defam AV2 is gain of a single ended up what is this just a minute before you write which is this amplifier is please remember I never said all input should be only on N channels this is a P channel device which is taking an input you can see an input is coming there this is the load for it so this is a common source amplifier with a P channel driver okay so do not look the other way that the input is given to 5 which is a P channel device okay and to keep it minus Vgs this actually the source is given higher voltage okay so that minus values are automatically created is that clear that we do in CMOS that is what we did here okay so please take it this is a standard defam followed by a gain stage single common source amplifier what is W by us will give you whatever currents it will keep will give you GM sign ROS and once I know them I can I will be able to evaluate gain of this stage and gain of this stage okay so the example is the AV1 will be minus GM1 R02 by R04 for the defam the AV2 will be minus GM5 into R05 R06 so the gain finally two stage gain is GM1 GM5 R02 R05 R06 please take it in the first case the output is picked up here is that clear these two transistors are not diode connected so they have ROS okay so they may be GM parallel one by GM parallel but R0 will take care of them whereas in this case one upon GM is its R0 actually R0 parallel one upon GM but I am not taking output here anyway is that clear so that base terms are missing simply because I am not picking output from that in I am only picking output from here so GM times either this GM or this GM because currents will be half off into R parallel of these two is the output is that correct same way whatever I am receiving here this size ratio R06 in parallel R05 into GM of R05 GM of 5 is the gain for common source this is that clear so it is very simple what we did and therefore not gain and again solving we already saw defam we already saw common source common drain common everything so we just substitute whenever is that okay so there is nothing very big this is a defam this is a common source amplifier there I have written it but you can see that I can just multiply the two gains I also know I can calculate GM 1 and GM 2 by writing 2 beta 1 ideas 1 2 beta 2 ideas 2 beta 1 normally a 99.999 will be equal except the variation part the thresholds will be equal the sizes will be equal but do not think 3 and 4 will have same W1 as 1 and 2 because they are loads they may be different values compared to this why other other reason also they will be different sizes the lower transistor what kind and kind the upper ones are P kind so even for the same current new ratio will appear okay so for that matter their sizes may be equal between M3 and M4 but will not be same as M1 and M2 as we did earlier okay so I can calculate GM 1 GM 2 RO 1 RO 2 RO 3 RO 4 all this knowing the currents and once I know the current now the question is how much current this will draw I am example I show you this please remember this current there it is showing from here I do not know what is the size of M6 I need okay I will see that this current is same as this current okay we have both P channels same current flows here to flow the same current here this will not be same current here is that clear to you let us say this is ISS this is ISS by 2 this is ISS by 2 so current which will flow through M6 is not ISS but ISS by 2 so for that W by L will be different is that point clear though it is made here but their size may not be equal is that clear to you so this are the issues we should quickly look at it from where current I that is why the first figures are shown P2I I to be P2I this is P2I which is pushing current in the load is that clear so the current is coming from M5 and not from M6 is that clear to you yes you can see from it why it should have because if these two values are very different which you can I mean there is no physical problems the problem with this the current which it will draw and current which it will able to push may not be sufficient then if it is too high from there at best this current can be pushed here okay now if that increases too much then this will not be able to sustain this maximum current is that correct let us say the ISS goes through so that till ISS it will happen but beyond that I can always increase 4 times 8 times 20 times then the currents cannot be overall be actually available to you so device will not remain in this device may go out of saturation therefore the best possible solution is run this current into this which you both transistor to remain in saturation is that clear these are the tricks when you do simulation if you do hopefully some you realize what have you change yourself and figure out what has happened okay and that is the trick yes it will I please take it this is this gate and this is the source this value is can always be equal to this if the currents are same if this current and this current are same this values will be always equal so that is why I am saying I am sizing that way I am exactly telling you this I is equal to beta by 2 W by L VGS minus I am keeping things fixed so that I can push the same current is that clear is essentially not this is divided by these this is the ratio this is an AC current you are you do not confuse between ACs and DCs is that clear the first part was the DC biasing situation now I am talking of AC current please get this 2 moves differently working okay so I did expressions I figured out I can just tell you we are just running the jokes what we have done I can find R o 1 by 1 upon lambda 1 R is by 2 R o 2 R o 3 similar way I can calculate all R o's and I can calculate all GM's okay and if I know one of them then I can start like all lambda are equal let us say for P channel and all lambda are equal for N channels so only 2 hours will be required to be calculated for those ISS is known so go back and calculate GM for them and keep doing till you get W bias for all example I am just going to show this is the formula is only that I designed use for design of a defam is that correct defam to this so I have an example for you you know this doesn't look to be very nice expressions is that okay what I did I am just trying to say I can evaluate R o I can evaluate GM in terms of size and currents ISS by 2 and W by else will decide my hours and GM's is that clear if alpha lambdas are known typical lambdas for 5 micron process is 0.06 per volt okay others may have 0.04 0.025 but which one is better higher or lower 0 is the ideal that is always infinite okay 0 is the ideal but 0 you will not get the larger technologies are larger lambdas okay in general so it typical values which my problems taken from boys book is 0.06 is typical value they choose but in your life when I give a problem I may not choose 0.06 it may be much different from the then I may use a technology of 0.25 so the specs given by 0.25 I will use it in your calculation right now as I said I am using boys data and therefore I am using his values but otherwise please take it the given data is coming from where technology file on a spice there is a technology file which will give you all specification for that technology node of a transistors is that clear so pick up actual data from there which in my case I will give a table or at least give the values okay so is that point clear so let me start having a problem which may clarify many of those doubts let us say at total bias current in defam is 20 micro amps I says I was one upon lambda ID and GM is under root 2 beta ideas it now it juggled it low I agree it is relevant but that much you can think okay yeah look over here it must have put a job here I was single ended all single ended you know as I said double ended are specific devices required not that they are not used by the user differential systems but as of now okay please remember I am using just to give ideas using data from boys Baker these work or these work so pardon me if that data is copied as it is and problems is maybe slightly modified or used there also but I have solved myself I have not checked with them if the bias current is chained on as 20 micro amps then the each arm will get a DC will be of Isis by 2 which is 10 micro amps so I can calculate if given betas lambdas okay so I calculate GM 1 which is 2 beta 1 Isis by 2 I know beta n dash I just do not know right now W by L but that is what I need to know R01 is equal to R02 lambdas are given to you which is lambda by 2 Isis by 2 R02 parallel is 1 upon lambda 2 plus lambda 4 there will be equal but if you wish you can write lambda 2 plus lambda of into Isis by 2 is that I am not saying lambda equal then I have lambda 2 plus lambda 4 times Isis by 2 is 1 upon R02 parallel R04 so this value I calculate 0.06 it is 0.06 per volt both of them all actually I am not chosen same actually even that is not true P channel lambdas are different from N channel lambdas for that is what I say for the simplicity okay so what is the current in each arm of a defam Isis by 2 is beta 1 by VGS minus VT 1 so root Isis root beta 1 by 2 is VGS minus VT 1 I am using this for what purpose you know the expression become any do I know this for a 5 micron process I know VGS 1 how much it will be V over V plus VT for this technology V over is 0.37 volt as I declared earlier okay voice book is that okay what is the purpose of doing this if I know these two values okay then and if I know this value then I know beta dash then what can I calculate W by L that is the purpose of all this evaluation is that here root Isis is beta 1 by 2 so if I do this so if we have is chosen 0.37 volt for a VT of 0.83 for N channel and 0.9 minus 0.9 for P channels then VGS 1 is equal to VGS 2 equal to 0.83 plus 0.37 which is for a 5 fold supply VSS is 2.5 minus VD is 2.5 total supply voltage is 5 fold for which these values are valid so I get VGS 1 equal to 1.2 Isis is 20 micron each is a half current and if you solve this that becomes W by L N is equal to 15 by 5 and by same argument same current going up I can I will have to calculate VGS 3 and VGS 4 from where instead of 0.83 use 0.9 okay because I still believe excess voltage is same for both N channel and P channels so if I know VGS 1, VGS 2, VGS 3, VGS 4 I will be valid W by L of 1, 2 and for N channel as well as for 3 and 4 for the P channels. Please I have already said whenever I calculate W by L's I neglect all 1 by lambda VDS terms okay but when I calculate arrow I actually use it because other arrow becomes infinite okay so all calculations of W by L's and GM's you may forget about 1 plus lambda VDS term okay but whenever you will calculate arrow that time do not neglect lambda because that will create high walks for you okay. So I know these values now to find an open loop gain what is the open loop gain the first stage GM 1, arrow 2 parallel arrow 1 is the first stage GM 6, arrow 6, 5 and 6 is not providing that name 5 and 6, arrow 5 parallel arrow 6 is the GM 6 5 times that is the gain for the second stage so this is GM 1, GM 5, this is arrow 2, arrow 5, arrow 5, arrow substitute the values already I have evaluated is that correct so if you substitute this I did not calculate but roughly I did some calculations this is called back up envelope mine calculation so no envelope but just by looking at it yeah, yeah, yeah, yeah. So around just write down this typical value which will get is around 2500 what should the unit both per voltage amplifier specified properly they does not matter because the ratio but even then do specify which amplifier you are using so give a unit V by V now why this whole game was is that point clear I am able to evaluate and why this L was written no feedbacks are right now used in any part therefore it is called open loop gains the next part that we will put close loops now that is the next thing we want to do so right now itself I started writing open loop okay so that later we do not have to say what is open loop so I have calculated is that everyone written so AAL is typically I am not exactly it may be 25, 24, 90 or 26, 50 whatever it is because my hand calculation has just cut out but along that now the game which we want to see very clearly from this expressions of AAL GM may root ISS or lambda may ISSA denominator so when lambda times RO sorry GM times RO so proportionately 1 upon ISS has to be 2 stage key square arrival so we say open loop stage gain for a 2 stage amplifier open is essentially inversely proportional to ISS is that correct this is a feature which you should use for your designs is that clear what is the feature I got why did all this calculation I figured out if I reduce the current by 10 okay what I will achieve low power fantastic 2 things I may lose image I may improve bandwidth also okay I may lose bandwidth also but I may get gain higher another thing I may hurt is that I will see the slew rate it will not charge faster okay so that if I want very high slew rate I want higher bandwidth I will increase GM that is I increase ISS but I will lose the gain because gain and bandwidth will go opposite is that clear to you so this is what design has to which one you have to cater to okay and how much closer you can come from either side so I wrote again hence the increase of ISS may improve bandwidth but decrease AOL or vice versa please remember in real life we are not just worried about these values but we want that these values remain constant okay for what variations process variation temperature variations and even power supply variations so if any variation in power supply appears currents will change any variation in W Biles of process kilometers change currents will change and in any time temperature changes so are the current change so our worry is we do not want gain to vary with any such environmental or design related variations this where that they should be very low sensitivity for them essentially makes system should have some mechanism which actually monitors the change and corresponding proportional something it returns to input which corrects it either way if it is increasing it should decrease if it is decreasing it should increase such a system which we do is called feedback systems is that clear so why feedback because these are not constant values in other assumption right now we assume everything 5 volt remain same W Biles are same everything is same between M1 M2 itself they will not be same okay and if there is plus 5 percent minus 5 percent you are 10 percent variation which is possible this may not be possible this may not happen on your layouts because that is a screen graphic does very well but when it goes to silicon the lithography technique does not allow everything as good okay okay so we wish to visit before we go to the open design that since I want a stable gain stable everything I like to quickly look into little bit of feedback which I did in second year many of you might have done it many of you still remember better than what I know many of you never wanted to know so long now either way so let us refresh ourselves from the feedback because we know feedback and stability that related obviously this word is true that one kind of feedback may actually spoil the stability the other may actually stabilize so all other tricks is to see that the one which stabilizes always remains and in some other case that is the joke every designer in a lot says if I am designing an amplifier it oscillates if I am designing a oscillated amplifiers so okay so the trick is the amplifier must work as an amplifier and the oscillator must oscillate at a frequency okay and the issues are always the opposite okay when you design a oscillator you want something happen and suddenly damping starts so what happened same way amplifier you think everything should be okay then it starts giving outputs like this so the values are very important in design and these should be understood from the basic perspective of feedbacks okay so let us look at feedback once again typical feedback system is shown here as I say this is only a precursor to what we are actually looking for but I am just going quickly through the basic feedback theory which will make us understand why we are doing something so this is an open loop amplifier this is the signal r i f is the input impedance seen from that this is some kind of a summer or adder signal term okay the impedance seen by the open loop amplifier is r i and this is an input x i output resistance seen inside out to the open loop amplifier is r o output is x 0 and the impedance seen outside x 0 is r o f which receives essentially some network impedance from beta the feedback is through a fraction of x 0 is returned please remember beta is always less than 1 so fraction is returned to the summer and then x s plus x f will happen depending on the sign either x s minus x f occurs or x s plus x f occurs depending on the sign of 2 which you receive okay so a l is called open loop gain beta is called feedback factor normally beta is passive element okay normally but need not be okay and if it is need not if it is the other way then the analysis becomes very very complicated okay but right now we will say assume constant so we say x 0 is the gain times x i x i is the input to open loop gain amplifier x 0 is the output so x 0 is a l j j omega x i a l j omega x i is nothing but x s minus x f the way right now signs are shown x i is therefore x s minus x f because of this I wrote this and x f is nothing but beta times x 0 so x 0 is a l x s minus a l beta x 0 so if I am going to find the closed loop gain which is x 0 by x s then it is a l upon 1 plus a l beta the sign of this can become minus depending on the a l is of what sign is that clear a l is negative it will become 1 minus a beta if it is 2 stage it may become 1 plus a beta so right now I did not want to put a sign in real life I will put a minus or plus as it appears okay now this fact that closed loop gain is related to open loop gain through a l upon 1 plus a l beta and in the control system theory or in feedback theory we give some names for this if you have any book these are standard definitions in any book including the book yesterday I said about said Rasmith and me so they may be here a l is the open loop gain this is called mixing area this is called sampling area so you sample the output return to input to a mixing so a l is gain without feedback acl is the closed loop gain with feedback and we define a term a l beta as the loop gain okay as the loop gain also it is called return ratio some books like grace day on Mayer's book use it return ratio okay so if you are policy Raj who happens to see the Gray and Mayer's book will a loop gain name will a return ratio Bode also use the return ratio not the loop gain okay so essentially the 1 plus a beta actually decides the feedback available to you okay because a l is the open loop gain and this is additional term which is coming so it is deciding the part coming from feedback okay these are definitions if you see the expressions everyone has these are standard and as I said at least the fourth year students who are taken my course second this slide I actually copied from that you can see this number appearing here is that okay one upon a beta decide how much you are away from you if open loop is a l that is the term which is changing the gain by putting 1 plus a beta so if that is larger a l will be net gain is smaller if it is smaller that is higher but it will never reach a l anyway okay unless beta is removed if let us say the loop gain a beta is greater than 1 then a l a l cancels or a cancels and we see closed loop gain is 1 upon beta is this good or bad it is very good because beta is a passive network okay which is relatively can be kept constant okay so if you have a feedback and you are gain for a l loop gains are higher then you are safer because your feedback is very much stable okay so why are you in all this calculation is we always assume beta gain once you do this it is constant no actually beta itself may vary okay beta register high obi temperature coefficient like you are okay but that is how we say R1 upon R1 plus R2 hold on hold on the company them okay however beta is less than 1 then ACL can be greater than 1 and however ACL is a 0 1 plus a beta can change with beta and value and sign of a 0 okay so there are 2 possible ways the feedback can affect us if you see our figure if the x sign x f are in the same sense then they add and their opposite sorry are the opposite sense they add if they are in the same sense they actually subtract okay battery high plus minus plus add ho jaiga plus minus minus plus subtract ho jaiga so essentially one which reduces the XI value from its excess value we say it is negative feedback but it does not mean always reduce it it also can correspondingly change output will return less feedback and try to adjust okay where do you think positive feedbacks are used oscillators for all amplifier will prefer negative feedback and that is what my issue was that when I design an amplifier I will end up in this when I design an oscillator I will end up here okay because both our functions have some parameters one may dominate over other and you forgot to bring them well so okay so basic idea is to design a negative feedback circuit just for the heck of completeness if you are a negative feedback what essentially we gain in an amplifier is that okay everyone this is standard okay the first thing it actually does is desensitivity of the gain what does desensitivity means it reduces the sensitive if you see a closed loop gain which is a 0 upon 1 plus a 0 l you can write I have sometimes I wrote a 0 sometime a well so it is a 0 upon 1 plus a 0 beta d acl is d a 0 1 upon differentiate here then we say d acl is d a 0 upon 1 plus a beta this still connecting this d a 0 this into 1 plus a 0 is come multiplied here okay so this essentially give me d a 0 by a 0 is equal to 1 upon a 0 beta d acl by acl so you can see any change in a 0 will be reduced by 1 plus a beta for the closed loop system so you are desensitized change in a 0 is now reduced in the acl system by as much as 1 upon 1 plus a beta so this is called desensitivity parameter or factor so any percentage change in a 0 please remember this is the standard technique of showing sensitivities as if d a 0 by is d y by y equal to d x by x correlation though percentage in this percentage change in how much okay so essentially they say the change percentage here will be reduced this because by this factor so this is a desensitivity the second advantage which feedback gives from an amplifier specific is let us look at the so the second feature of nearly feedback is it improves the bandwidth okay let us say your open loop gain is a mid band upon 1 plus s omega 0 where omega 0 is the first pole dominant pole we call it done a m upon 1 plus s omega 0 is a 0 a l is a 0 right now then with the negative feedback acls is a ls upon 1 plus a ls beta substitute this quantity here and here okay so you get a m upon 1 is mid band gain a m upon 1 plus s by omega 0 upon 1 plus a m upon s plus 1 into beta collect the terms and define acl 0 as a m upon 1 plus a m beta which is independent of frequency so dc closed loop gain dc closed loop gain a m is the dc mid band gain for open loop system so I get acls is acl 0 upon 1 plus s time s by 1 plus a m beta times omega 0 so now the pole has been shifted from omega 0 to 1 plus a beta times omega 0 so you have improved your bandwidth by this much amount by just putting a feedback is that clear so why is that clear but if you see closed loop gain what it has done it has reduced by that much amount so bandwidth is increased by that much amount okay please take it these are my notations names you may have if you are reading from any other book and they are followed but follow universally what you follow once like spice uses K as the beta okay but some spice new versions use K by 2 or rather beta by 2 as K but think of it this can vary you because you are losing 50% on that okay like spice level 3 level 49 versions use the beta dash by 2 as K dash whereas the 3.3 of the old versions in G spice they only use beta dash as K dash the next of course this I made a statement obviously the bandwidth improves gain falls a third most important reason why one works with the feedback near a feedback says it actually reduces what we call nonlinear distortions in amplifiers what does nonlinear distortion means if you have a characteristics V0 versus V in for a given V in value if the linearity is not held then the since the curve is not linear it is a nonlinear term so when you actually find V0 in terms of V in your square cube polynomial terms will appear so much of the power or energy will be lost in other frequencies okay second harmonic third harmonic and higher harmonics whereas you want all the energy should go to fundamental so that means larger the slope change more and more energy is being lost that is V0 is not getting at that frequent for null frequency exactly transferring from V in okay that is called harmonic distortion the third harmonic distortion is the worst among all because that phases in exactly with the first ones so it gives huge interference so in RF design or any other designs the various THD but that will see later so let us say this is the kind of characteristics without feedback and in this range V0 V in is linear beyond this of course it changes the slope it may actually fall further so these are nonlinear terms so any input here or here with this slope will give you second and third or fourth harmonics however if you add a feedback you are just now seen gain is something like reduced now but but this but now you can see this frequency term up to which sorry sorry that is what I was saying how it is opposite okay that is fine so what essentially is time to say is as I change dv0 by dv in changes that means the linearities correspondingly changing so the idea behind putting a feedback is increase linearities okay so what is the purpose then you may increase linearity but your gains will be correspondingly different from your requirements so if the bandwidth will be different but at least for large signal operations probably you will be able to operate better okay okay so this is the three things why everyone goes for linearity feedbacks so from where the in other opiants or anywhere from where or any amplifier where the feedback is coming in a transistor normal transistor if common source for example is there where if the which is the feedback which is coming from Cgd okay Cgd is the output node she is the input node so the capacitance between gate and drain essentially is always available to you as a feedback factor okay so irrespective whether you put any external C there Cgd is always going to put you in negative feedback system okay and if that happens that is why systems have lower bandwidth we have calculated with Cgd but it is relatively will be stable operations one more stability that she will build actually increase but doing that what else will you see that that is our designs okay so we want to use this before we quit for the day here is something which you should know there are the two terms we use in feedbacks or any bode system of frequency response we call those terms as gain margin and phase margins okay these are most important parameters in design we will be specified phase margin for an amplifier okay or if not specified as a designer you will have to choose it how much I should have should I have 45 degree phase margin 50 degree phase margin 55 degree phase margin or 65 or 90 okay you may choose either of the phase margins how will they influence the performance is what we are going to see okay so what is the phase margin we will like to see this is our case loop system the case loop gain is as upon 1 minus as beta s and as I said we define the loop loop gain as as beta s here the s is taken minus so sign is going accordingly there is a standard criteria which is called Barkhausen criteria for oscillations or non instability which says a j omega 0 into beta j omega 0 which is l j omega 0 should be less than the magnitude y should be less than 1 for stability where omega 0 is the frequency at which the loop gain phase is 0 I repeat omega 0 is the frequency at which the loop gain is sorry the angle of phase of that is 0 angle means phase phase is 0 at that frequency at that frequency a times beta must be less than 1 then the system will remain stable in case of oscillator what we will do it we will actually break this to make it oscillate okay because gain is minus though this is taken as like this but this sign is taken as a return with a minus signs because the gain is less than db the way we calculate okay so you will just check it we will come back to it again now here is the important graph which is given in every book if not you can note down from here this is a representative graph nothing very this is the bode plot I am plotting a loop gain versus frequency okay let us say I have a pole P1 where the loop gain starts falling from this frequency P1 and let us also say for design the second pole is at the gain bandwidth point which I can design tbw is this where the gain becomes 1 the pole actually occurs there okay is that point clear the P2 pole occurs right here this is just to explain nothing it may occur later or it may occur earlier but just to make the case important study case is that the first pole is here second pole is actually starting here at this point okay we know from the Bode's plot that once the poles this 3 db point goes the loop gain will start falling by minus 20 db per decade okay and it reaches if there is no pole till then it will go to the 0 db point or it crosses the omega axis at this point which is your gain bandwidth point and let us say the second pole occurs here that will also give you another 20 db per decade fall so this 20 let the second pole 20 so the next fall will start going by 40 db if there is another pole somewhere here then a 60 db it will start falling down afterwards let us say the third poles occur here at this point 60 db will start falling but once the gain falls below minus 20 db or even 0 db it is not a gain anyway is that correct gain means log of something which is positive only if it is positive db otherwise it is a fraction and if it is a fraction you may still call it a gain but it is not really a gain so gain is only up to this as long as it is plus db it is okay now if you if you have done your complex algebra well and as last day I did tell this tan inverse or the angle for this is tan inverse imaginary by real essentially gives me what they call argument or tan inverse points and for these you study it if not some other day at first pole it should at least have 45 degree down from the mid band point mid band point start 180 degree because that is where the loop gain starts okay so from 180 at the pole it should have gone to 45 degree down because this slope is 45 degree per decade why 45 tan inverse 1 is 45 so there is a 45 degree so from 180 it goes to 135 at the pole position 45 degree down per decade assuming okay at the pole and it continues to fall by 45 degree per decade as the frequency increases but since there is no pole ahead then below this after this total of J1 J is over 90 degree the phase will become constant and it continues to remain constant but it wants that at the second pole it should go 45 degree further down so from this 90 degree it should go to 45 degree so this 45 degree per decade must cross at 45 degree point at the second pole is that clear so this therefore slope becomes something like this and this is the point please remember these are the points of interest to me at the pole P2 or at this gain bandwidth point the phase of loop phase loop gain phase is how much 45 degree is that clear if you increase further this gain 60 dB or 40 dB down then finally phase will become 0 okay phase will become 0 if you further go down it will actually increase further minus of that value as if you say when the oscillation starts when the output and input becomes in phase if they are out of phase they will remain in negative feedback stable situation what we are trying to see now is if when the gain is 0 you are still in the negative feedback phase 45 degree you are away from it is that correct let us say at this point would have occurred here I do not have figure here somewhere then what would have happened the gain would have been positive a 0 and your phase now is 0 other side which means the signal is now returning phase with the input is that correct which is the condition of growth that is instability. So to keep it stable what is the criteria when the gain is loop gain is positive the phase should not cross 0 so the margin up to this is available to you is called phase margin so how much is phase margin with me here 45 degrees so 45 degree is the phase margin available till that time the gain you can see from here beyond this the gain has already crossed 0 and my phase has not gone to 0 is that correct beyond if this could have gone somewhere here the gain would have remained positive and phase would have crossed 0 then I would have in phase component in the feedback in which case the growth would have started so this is essentially called phase margin then at 0 degree phase if the gain is negative then you are safer this is called gain margin at 0 degree phase how much you are away from GBW point is it called gain margin okay right now this is negative but let us say if you are the opposite side gain margin will be positive and phase margin will become negative which means you will have an unstable situations is that correct so in normal case gain margins are not specified because they essentially represent 5 in a way so we only say as long as phase margin is 45 degree why 45 degree is important for me why not even as long as it is anything between 45 and still safe what is the worry we do not want to go below 45 anything any additional capacitor parasitic appears how much phase it can give you 90 degree okay that may push it down earlier than what you thought okay so the minimum because 50 percent point I have to get it so I say at least 45 I should have so that the worst is gain margin is 0 at phase margin is 0 so you are exactly cutting each point is that clear so the minimum phase margin for stability is 45 now we will see tomorrow some more details of this and improve that the phase margins are essentially adjusted because what will phase margin will do they are deciding poles is that correct we know poles decide the bandwidths okay so by changing the phase margin you are also designing the bandwidths for the amplifier so how much about the 90 also you say very safe very safe may have a lower bandwidth because then only this can occur okay that very safe may create your bandwidth very very small so you need higher bandwidths and you also need safe margins so somewhere between 45 is very lower so never tried 55 degree to 65 70 degree is the ring in which and this number has something to do with transient response also which we will see next time zeta functions we are right now looking which frequency response frequency response if I see a time response I will suddenly see something else is happening at the phase changes okay and that I will say okay how much margin I have really to work with see you next time.