 Hello, and welcome to this presentation of the STM32 Independent Watchdog. It covers the main features of this timer, able to reset the microcontroller on expiry of a programmed period of time, unless the program refreshes the content of the down counter before its value becomes equal to zero. The Independent Watchdog is used to detect and resolve malfunctions due to software failures. It triggers a reset sequence when it is not refreshed within the expected time window. Since its clock is an independent 32 kHz low-speed internal RC oscillator called LSI, it remains active even if the main clock fails. Once enabled, it forces the activation of the low-speed internal oscillator, and it can only be disabled by a reset. One of the main benefits for applications is its ability to run independently from the main clock. Since the IWDG belongs to the VDD power domain, it remains active when the microcontroller enters the standby and shutdown power states, in which the V-Core power supply is switched off. The Independent Watchdog offers a wide range of timeout values. From 125 microseconds to 32 seconds, it is clocked by a 32 kHz RC oscillator, which cannot be disabled when the independent watchdog is enabled. It generates a reset when the program timeout value elapses, or when a watchdog refresh occurs outside a program time window. It is possible to automatically enable the independent watchdog after a system reset thanks to the device option bits. It is possible to define the behavior of the independent watchdog in debug mode. Once running, the IWDG cannot be stopped. It remains active in stop and standby modes. Independent watchdog registers are located in the core voltage domain, while its functions are in the VDD voltage domain. Two clocks are needed. The APB clock is required in order to access registers. The LSI clock is required for the functional part of the watchdog. This architecture allows the independent watchdog to remain active even in stop, standby, and shutdown modes. A programmable 8-bit pre-scaler is used to divide the LSI oscillator frequency. A 12-bit down-counter defines the timeout value. This diagram illustrates how the independent watchdog operates. When the down-counter reaches zero, the watchdog reset is activated. This happens when the application software did not refresh the window watchdog on time. If the software refreshes the watchdog while the down-counter is greater than the value stored in the window register, then a reset is generated as well. To prevent a watchdog reset, the refresh must occur when the down-counter value is other than zero and lower than the time window value. The independent watchdog hardware is enabled by the device's option bytes. If the hardware mode is enabled after every system reset, the watchdog automatically loads the down-count with OXFFF and starts to countdown. To prevent any reset, the key register must be refreshed at regular intervals before the counter reaches zero and within the time window if this option has been selected. The independent watchdog software start is configured in only a few steps. The first step is to write the key register with value 0X000CCCC, which starts the watchdog. Then, remove the independent watchdog register protection by writing 0X0005555 to unlock the key. Set the independent watchdog prescalar in the IWDGPR register by selecting the prescalar divider feeding the counter clock. Write the reload register name IWDGRLR to define the value to be loaded in the watchdog counter. After accessing the previous registers, it is necessary to wait for the IWDGSR bits to be reset in order to confirm that the registers have been updated. Two options are now available. Enable or disable the independent watchdog window option. To enable the window option, write the window value in the IWDGWINR register. Otherwise, refresh the counter by writing 0X000AAAA in the key register to disable the window option. The IWDG timebase is pre-scaled from the LSI clock at 32 kHz. The IWDGPR prescalar register can divide the LSI clock frequency by 4 up to 256. The watchdog counter reload value is a 12-bit value written in the IWDGRLR register. A formula can be used to determine the independent watchdog timeout. The independent watchdog time is based on the LSI period and its prescalar, as well as the selected watchdog counter reload value. Note that the reset and clock controller unit named RCC provides registers indicating the source of the reset. In that way, the boot program can check if the reset was caused by the independent watchdog. The IWDG can be active in all modes. So, when low power modes are implemented, periodic wakeups are required to service the watchdog if the microcontroller state has to be preserved.