 I'm very, very pleased to welcome Dr James Beely from the University of Glasgow, who'll be talking about designing custom chips and sensors and lab and a pill technology, thanks very much. Thank you. Can everyone hear me? Okay, I'm going to talk today about the process of designing and fabricating chips, and I'm also going to talk a little about some of the research prototype chip projects I've involved designing. So, I'm basically going to look at the process of designing applications to the integration circuits, ASICs. I'm going to look a little bit at chip foundries and processes. I'm going to look at the process of designing and verifying analog chip hardware and digital hardware. I'm going to look at a little reverse engineering and fake chips. Then I'm going to look at a couple of projects I've been involved with, which are capsules for doing auto fluorescence and ultrasound examination side of the human intestine. So, the first question is, if you looked at a chip, what would you find? Okay? If you look around the edge of the chip, you will see a padring, and you've got little bond pans. These allow you to bring out bond wires to a chip package or to a circuit board. They let you bring in power and bring out signals. This is an RF chip. I think they're quite prominent on the chip are inductors in the middle of the, and to the right. These are fabricated on the middle layers of the chip. There's also a digital block on the left. This has been synthesized by Digital Synthesis Tool to fit into the space on the left of the chip. Chips are built on a number of different fabrication technologies. Okay? The most common, the most dominant is silicon. The really dominant technology is CMOS, complementary metal oxide. This is where the most widely used technology used in the great bulk of digital chips. Bipolar analogue is also not uncommon. They're also more specialized silicon technologies like BiCMOS, which combines Bipolar and CMOS in the same chip. This is generally used for op-hamps and RF work. There's also BCD, which is used for power electronics. But CMOS has really become the dominant technology. The simple reason being that the, there are two main transistor types. Bipolar transistor, this will, if you're using your devices as a digital switch, a Bipolar transistor will draw current when it is switching and it will also draw current in the steady state. A CMOS transistor will only draw current when switching. When it's switched on or off, it will draw almost no current. This is really why CMOS has become the dominant technology for digital design, simply because the power consumption is much lower. Because so much of the hardware designed is done in CMOS, there's been a great emphasis on putting other functionality in CMOS chips. There's been a lot of interest in putting analogue functionality on CMOS chips to produce mixed signal chips. There are also more specialised technologies. For example, silicon carbide power transistors, silicon germanium for radio frequency work. And for LEDs, light emitting diodes, there are a number of different technologies, gallium phosphide, zinc salinide etc. But the really key thing with this is, although CMOS is dominant, there is no one technology that will do everything. Although the semiconductor industry is heavily geared towards CMOS, there is no single technology that will do everything that you want to do. The main building block of a CMOS chip is a MOSFET transistor. It basically shows what you'd get if you took a vertical slice through a CMOS transistor. It's basically fabricated on a silicon wafer. When you're fabricating, you're basically using a series of masks and a series of etching processes. You're basically implanting impurities into the silicon to create pn junctions. In the case of the CMOS transistor, you're also fabricating a silicon gate on top. When you apply a voltage between the gate and the source, this will cause a current to flow between source and drain. It effectively means your CMOS transistor is a voltage-controlled current device. The main defining feature of a CMOS process is what's called feature size. Feature size is basically the smallest gate width that you can fabricate in a given process. This will be recorded in the process. It might be 0.5 microns in a power process, right down to 7 nanometres in the state of the art, let's say, Intel processor. There was a nice talk at CASE Communication Congress by R.A. who went into this in a lot more detail, so I'd strongly make it a recommend you look at that. On your chip, you've got transistors, you'll have resistors, capacitors, inductors. Now to interconnect, you'll have metal layers. Coming up from each of these devices, you'll have vertical metal vias. Then you'll have typically between 2 and 12 metal layers. Now your chips will be fabricated on a silicon wafer, which is typically 30 centimetres diameter. After fabrication, the chips will be separated using a dicing saw. The set-up cost of a process is very high, the order is £100,000. If you're prototyping, and the work I've done is basically developing early stage proof of concept prototype chips, you use a multi-project wafer service. In this case, if anyone uses PCB pool or similar, basically the MPW service will basically do a wafer and it will have a number of different chips in a single wafer. This will bring the cost down from £100,000 to maybe £10,000, £15,000, in other words to what a university research budget can afford. There's a whole range of devices you can have on chips. You can have resistors, which will be fabricated in polysilicon. You can fabricate capacitors using the capacitance between 2 adjacent metal layers. You can have inductors, which are tiny coils made of metal. You've always got bond pads to bring signals out. You can also do sensors. For example, charge-cruple device or CMOS sensors for light sensing, photodiads, S-pads, single-photon avalanche diodes for sensing very low light levels, ISF sensing pH. There's a lot of interest in putting sensors on CMOS because it means that you can put the sensor and the processing electronics on the same chip. A lot of the old digital cameras use CCD, charge-cruple device. Charge-cruple device needs a separate chip to address and process signals. The CMOS sensor allows you to put the imager and electronics on the same die with a result in saving in cost and size. You can also process things, for example, optical fields on top of the chip. I'm going to talk about the design process. This is what I do for a job. There are only three major dominant manufacturers. There's basically synopsis, cadence and mentor graphics. The problem is because it's quite a specialised process, there aren't a lot of companies. The software is very capable. It's expensive. It can leave a bit to be desired in terms of usability. Open source support is very limited. This is quite an old and limited open source package. Basically, pretty much everyone will use a commercial package for one of the three major manufacturers. One side, obviously, is the design software. The other side is the design kit. This is supplied by your chip manufacturer, your chip for injury, and it's specific to the chip design process. They'll give you a set of simulation models. They'll give you digital standard cells for digital synthesis. They'll give you design rules because each process has a set of rules in terms of things like gate width, track width, spacing between structures. These are manufacturability rules that have to be adhered to pretty strictly. If you don't meet these rules, they won't even try and fabricate your chip. The other thing is that a lot of the devices are parameterisable, so that you could, for example, have a transistor, and you could define, with the length ratio, to define its gain, or you could have a resistor where you define its resistance. The other thing that you can often pick up from other manufacturers are IP blocks, intellectual property blocks. Because of the expense and complexity and risk in designing chip hardware, there's a strong emphasis on design reuse. In other words, if you've got hardware that works, or a subblock that works, you would tend to reuse that, and it means that there are many companies who are actually selling validated and verified third-party IP blocks. Again, these could be parameterisable. You might, for example, buy a ROM or a RAM block for a processor, and when you buy it, you would specify the ROM depth and data bus width. There are three two kinds. You've got hard cores. Hard cores are specific to a particular chip process. You also have soft cores. They will come in a hardware description language, and you can put them through your synthesis tool, and you can synthesize them into your own process. So there are all sorts of blocks, for example ADCs, digital envelope converters, op-amps, buffers, phase lock loops. There are various bus cores, for example PCI Express, CAN bus for automotive USB, which, again, will be pre-verified. You can even buy an entire processor. This is really how this is ARM's business model. ARM don't actually make processors. ARM sell processor cores to third parties who integrate those into their own chips, along with other functionality. So if you want to design a chip, your starting point will be a specification. You define what you want your chip to do, your power budget, pin-out, et cetera, and that will take you on to a particular fabrication process. Then you'll partition your design down, you'll partition it down into manageable units, into analogue blocks and digital blocks. Then you carry out your design, and you'll spend a lot of time simulating and verifying, because the problem with the chip is, with a circuit you can pull out your craft knife and soldering iron and rework it. If you write a piece of code in its buggy recon part, you cannot do that with a chip. With chip design, you spend a lot of time in verification. You spend a lot of time on simulation, analogue simulation, digital simulation, mix signal simulation, and design row checking and layout versus schematic checking. Before you submit a design, you want to be very confident that that design is valid and it's going to work. In the real world, you often go through multiple iterations. It will often take you quite a few iterations to get something that actually meets spec. So, I don't know how many people who have done PCB design. The analogue entry process is very similar. You have a schematic tool, and you have a library of transistors, resistors, capacitors, et cetera, which is supplied, they're part of your design kit. You'll basically enter those in your schematic tool, Cadence Virtuous, so for example, and you'll parameterise them. You will set the value of a resistor, the width-length ratio of a transistor, et cetera. Then you simulate each of the design tools that will incorporate an analogue... It's basically a P-spice-type simulator. Cadence case, for example, AD or Spectre, synopsis do H-spice, and you will define inputs. You can do it basically a transient suite, for example, where you define inputs at times, and then you'll get a waveform output. You'll basically have to look at that and see if that meets spec. You can also do things like frequency sweeps. You can also sweep over a range of temperature, because obviously device behaviour will vary with temperature, with process tolerance, and with supply voltage. You can also look at things like phase and gain margin for stability amplifiers. Again, you'll go through iterations. Once you have something that meets spec, then you move into the layout phase. You basically have an analogue layout tool. In your schematic tool, you basically pick each device. The layout tool, it will generate an appropriately shaped transistor, resistor, inductor, et cetera. You then have to manually place them, and you also have to... When you place them, you have to consider carefully signal integrity, for example, keeping noisy digital circuitry away from sensitive analogue circuitry. You will then have to manually run wires on the metal layers, wires and wires between those devices. Then you can do a layout versus schematic check. That will check that your layout matches the schematic. You also do a design rule check. That checks that this layout matches or meet complies with the designer's design rules. The other issue you have is parasitics. You've so far simulated transistors with ideal connections between them. Now you've done a layout. You have now added extra wires on the metal layer. These will bring in stray inductance and capacitance and resistance. These will tend to have an effect, particularly on RF circuits. Then you run parasitic extraction. This will add to your simulation model. It will add additional capacitance and inductance. You then resimulate with parasitics. Once you've done that, again iterated a few times, you have a valid analogue block. The digital design process for anything but the simplest designs is built around hardware description languages. You're basically writing a programming language description of the functionality you want from your chip. Common languages are VHDL, Verilog, System C, System Verilog. You're basically coding up a description of functionality of things like counters, buses, addressing, state machines etc. Now these languages, unlike conventional coding, they're inherently parallel because you're coding up a number of functions in hardware which will operate simultaneously. The other thing to be careful about is each of your synthesis tools only implements a subset of Verilog or VHDL. You could code something in C or Python. You could write it five different ways. It'll work. Verilog or VHDL, you could code something in this entirely valid VHDL or Verilog, but only a subset will work. Each tool has its own subset, so again you've got to read the documentation. You really need to follow, let's say, cadence or synopsis, recommend way of coding. These languages are also modular to allow design reuse to allow you to read your IP blocks. An important feature is a test bench. A test bench is basically a top level. You basically instantiate your design as a module. The test bench provides a set of inputs for testing. Which you'd use in simulation. Once you've got syntactally valid VHDL, you'd put that and you compile that in your test bench into a simulation tool like VCS or NCSIM. This will give you a waveform output. You would basically define all your input signals, define your clocks, define your data buses. This will give you a waveform output. This allows you to verify that your code is functionally correct. At this stage it doesn't include any timing delays. Again, it's right this multiple times until it works. The next step is synthesis. Once you have a valid VHDL description of your circuit, the synthesis tool, this will convert that into a net list of gates. The gates are process specific. The gates will be provided, or gates or blocks, they'll be provided by your ASIC foundry. You'll give your synthesis tool a very large VHDL net list input. You'll give it the timing information for the gates. You'll also give it constraints. You can constrain power. You might say this pin's a clock and it works at 50 MHz. You might say this pin has to have a clock to output. They have more than five microseconds. You give it those constraints. The synthesis tool will then attempt to meet those. Again, you may need to iterate this a few times. Assuming that since the synthesis is successful, it will generate a net list. You now have a net list of gates provided by the ASIC manufacturer. You've also got a standard delay file, SDF. This provides system time delays, in other words, the propagation delays within each block or gate. Now, because it requires iteration, the process is heavily command-line driven. You can see a graphical interface there, but a lot of the functionality is command-line based. This is so you can script it because, again, you often go through many iterations so the whole thing is scriptable using TCL tool command language. You'll basically take your commands from your first iteration, put those into a text file, and that will give you a script that allows you to rapidly reiterate and have to go back and make design changes. From your net list, so you've now got a net list, a very long of the HDL net list of gates and timing. You'll put this into a place and route tool, for example, Cadence Encounter. The place and route tool, it will take that net list and it will physically lay it out within actual silicon. So your starting point, you'll define the boundaries of your digital block. Think back to the second slide I put up the chip, there was a digital block which had irregularly defined boundaries. You can shape your digital block to fit around other devices. So basically you determine the boundary of the digital block, you set up power and ground rings around it, and you'll import your net list, and again you'll give it timing constraints, you'll define which signals are clocks, which are asynchronous. Then the place and route tool, it will auto place those cells in rows. It's basically row based. If you were to look at a digital chip very closely, you'd see row of chips. It will auto place, it will then generate a clock tree. The clock is basically the source of synchronisation for all the synchronisation in the circuit. The goal of clock tree generation is to minimise the skew or the time difference between different clock signals within the chip. So it will basically place a clock net and a clock buffer. It will basically prioritise that first. Then you run the auto-router. The auto-router will attempt to auto place tracks, which will interconnect the cells. Then you run a static timing analysis. This will basically check each path through the system, then it will check it meets the constraints. If it doesn't meet the constraints, the tool can, to a certain extent, fix timing violations. It can insert buffers into clock paths or signal paths. But again, if you have major timing issues, you may just have to go back and re-iterate design. Assuming you get through place and route successfully, again you run verification, you'd run design rule checking, then it will generate an output block and cadence, for example, in the ASUS format, which you can import back into virtuoso. Then it will give you an output net list, which you can use for simulation and an output timing signals. This means that you can then do a post-placing route simulation. It means that you can re-simulate with gate delays and interconnect delays. Again, you want to check that, meet your specification, and if not, again, re-iterate. Your next step, once you have valid analogue and digital blocks, is chip assembly. You'll basically lay out the complete chip. You'll have bond pads, analogue input and output pads. You'll basically place a pad drawing around the edge of your chip. You will place your analogue and digital blocks in the chip, again, taking care over signal integrity, taking care to keep digital signals, which are noisy away from analogue signals. Again, you will manually put wire tracks to connect those blocks together. Again, you'll do a lot of time spent doing design row checking, lay out versus schematic, parasitic extraction, mix simulation, et cetera. You're simulating the whole chip. This stage is slow and you're often rushing to do this to be a chip deadline. Once you have a valid chip, the process, if this was done years ago in tape, it's still referred to as tape out, so you'll submit a GDS2 file to your chip for injury to your manufacturer. You'll then wait, certainly in our case, wait several months, you'll get a small number of chips back and spend a lot of time testing. Now, a chip on its own is not a lot of use, so a chip needs to be bonded onto a circuit board or onto a package. The bulk of chips will be wire bonded into a package. It will be a dual-in line or a pin grid array or a ball grid array package. You'll have little bond wires, which are typically golden aluminium, and these are bonded by an ultrasonic bond head. If you look at the picture on the top right, there's a chip which is bonded to a package with little bond wires. They're basically bonded from the chip bond pads onto bond pads on the package. These pads on the package, these in turn are connected pins. Traditionally, the traditional package has been a dual-in line package with pins at 0.1 inch spacing. The limitation of that package is limited pin out. You can have a limited number of pins. The other limitation is stray inductance and capacitance, which tend to impact badly on radiofrequency circuits. So a lot of chips now will tend to use surface mount, they'll tend to use ball grid array. In this case, you have a chip bonded to a substrate, and then there'll be little solder balls on the underside of the substrate, which are basically ball grid bonded to the circuit board. You can also have multiple substrates on the, or multiple chips on the same package. As I mentioned earlier, no one chip process is really suitable for all functionality. So on the bottom right is a WS2812, I was known as a new pixel. This is a programme of multicolour LED. It was on the EMF badge from two years ago, and if you look closely, you can see they've actually used, they've got four separate substrates. There are three chips at the bottom. These are three LEDs in different colours, and the top chip, this is a CMOS chip. So the CMOS will basically take a serial input command. It will then drive the three red, green, blue LEDs to give the programme colour. There's a whole industry devoted to reverse engineering of chips. Whether that's hobbyist, whether it's people looking to paint in violations, people trying to figure out what the competition is doing. Now most chips are packaged in resin. Now to get the resin off requires nitric acid, which I wouldn't recommend for safety reasons. And beyond that, once you've taken off, once you've actually exposed the chip, you can then strip away the individual layers step by step. Again, if you want to look into this, a couple of nice websites, they've got some very nice chip pictures. If you want to look at a chip yourself, there are metal case chips. There are devices, this for example is a power transistor. You can get them off eBay. The case will easily come off with a hacksaw or dremel. So that will give you a fairly safe way to, if you feel like decapping a chip yourself. This is actually quite an interesting issue of fake chips. This was something that turned up on the Zepto bar site. They were looking at Nordic NRF, this is basically an UHF-RF transceiver. The original chip comes in at about $10. And they've come across a fake. Somebody's obviously somewhere, looks like they've got a bootleg copy of Cadence. They've actually managed to reverse engineer the complete chip. Again, Morstofen's Zepto bars, and Bunny Huang has quite an interesting thought on this. I've talked about some projects I've worked with. This is the fluorescence imager capsule. This is a project which I've worked on at Glasgow University. You may have come across white light imager caps. It's basically a capsule you swallow, and it has a camera, LED, and it lets you image the entire intestine. It's basically used to image disease, and it will cover parts of the intestine that endoscopy won't cover, because endoscopy will only cover down to the stomach, and the large intestine. Endoscopes won't cover most of the small intestine. Now, off to fluorescence. If you illuminate intestinal tissue with blue light, it will fluoresce green. You get weak fluorescence. This fluorescence lets you see early signs of disease that you're not going to see with white light. So we developed a prototype capsule to do fluorescence imaging of the intestine. Now there is a well-proven fluorescence endoscope, but it only goes down to the stomach in geodium. So basically, we did a 32x32 single photon avalanche diode SPAD array, and power management impulse counting on a chip. We basically integrated it into a miniature capsule. We've integrated it with an FPGA for control, and an 868 megahertz wireless link. So far we have validated this on intestinal tissue for a pig. This is actually on a lab bench. I had to go out to a slaughterhouse to pick up a pig intestinal tissue, which is kind of fun. This is the fluorescence imaging asic. We did this in a 0.35 micron high voltage process. High voltage in the asic world means anything above 5 volts. The little chip is about 3.7 by 3.7 millimeters. You've got a single photon avalanche diode array. This is an array of very sensitive amount. It'll basically give a pulse each time it gets hit by a single photon from multifluorescence. We've got pulse counters. We've also got a charge pump that generates 37 volts from a 3-volt hearing aid battery. This draws about 1.8 milliamps on average, imaging at one frame per second. The capsule runs for about 12 hours, which is ample to work through for human testing. Another project I'm involved at the moment is a sonopill. The basic idea is to do ultrasound examination below the surface of the human intestine, because you can look from outside the body with ultrasound, maybe 2 or 5 megahertz. It will let you see through the whole body. For example, ultrasound used for imaging pregnancy, it doesn't let you see much detail. If you increase frequency, you get less depth, but you have much greater detail. The goal is to put 30 megahertz ultrasound inside a capsule to see a few millimetres below the intestinal surface. The basic idea is we'd have eight ultrasound drivers, a 32-element receiver array, data acquisition embedded processor and an ADC on chip. This was the chip we designed. Again, this is done in a 0.18 micron high voltage process. We've got an on-chip processor. We've got a data acquisition block. We've got 32 low-noise amplifier receivers for acquiring data from the receiver array. We've got an ultrasound transmitter. We did this in an AMS, an ultrasound process, about 16,000 gates. This is currently bench tested. We're currently testing this with transducers. It's showing good signs so far. I've been given hints to finish quickly. This is just one more project. I've had some involvement. This is a multicorder. The idea in this case was to put multiple medical diagnostic devices, bench top devices on a single chip, a single handheld disposal chip. We're basically looking at pH, luminometer, spectrophotometres. We're basically looking at metabolites which are indicate markers for disease. This basically had a 16 by 16 or a 30 by 32 array pixel which are basically S-pad for low-light imaging, pH, and photodiode. This chip basically had enzymes bonded to the top. It's actually been proven with two different processes. One was an enzyme which suggests a colour change in relation to cholesterol level. The second which was a pH change in relation to blood glucose. This is basically a research prototype to demonstrate a small handheld device that can be used for disease diagnosis. I've been given more hints to finish. These are just a couple of sites you might look at if you want to look at more decap chips. Thanks guys, we might have time for questions. I'm afraid we're probably not going to have time for questions. Where might they find you if they want to come and ask you questions? I'll be outside. I'll be over there. Thank you. Please thank James very much for this fantastic talk. Thank you.