 Hello and welcome to this presentation of the STM32G4 flexible memory controller. It covers all features of this interface which is used to connect external memories such as NOR flash, NAND flash, SRAM and PSRAM. The FMC controller integrated in STM32G4 products provides external memory support through two memory controllers, the NOR flash and PSRAM controller and the NAND memory controller. This enables the CPU to communicate with external memories including NOR and NAND flash memories, PSRAM and SRAM. This interface is fully configurable allowing easy connection with external memories or other parallel interfaces. The benefits of the FMC controller include not only RAM and flash memory space extension but also the ability to interface seamlessly with most LCD controllers which support Intel 8080 and Motorola 6800 modes. This LCD parallel interface capability makes it easy to build cost-effective graphic applications using LCD modules containing embedded controllers or high performance solutions using external controllers with dedicated acceleration. The FMC controller offers two independent banks to support separate external memories. Each bank has an independent chip select and an independent configuration. Each bank features programmable timings, a configurable 8 or 16-bit data bus and can access memory in asynchronous or burst mode for synchronous memory such as NOR flash and PSRAM. Synchronous memory can be accessed at maximum frequency of 8 o'clock divided by 2. The FMC controller supports a wide variety of devices and memories. It interfaces with static memory mapped devices including static random access memory or SRAM, read-only memory or ROM, NOR or one NAND flash memory, PSRAM. The FMC also interfaces with NAND flash memories and supports error code correction or ECC for up to 8 kilobytes of data read or written. Three interrupt sources can be configured to generate an interrupt when a rising edge, falling edge or high level is detected on the NAND flash ready busy signal. Furthermore, the FMC interfaces with parallel LCD modules supporting the Intel 8080 and Motorola 6800 modes and is flexible enough to adapt to various LCD interfaces. The external memory space is divided into fixed size banks of 256 megabytes each. Two external memory banks are dedicated to the FMC. Bank 1 is connected to the NOR or PSRAM controller and bank 3 is connected to the NAND controller. Banks 2 and 4 are reserved. The flexible memory controller supports non-multiplexed and multiplexed PSRAM and NOR interfaces. The non-multiplexed interface has separate address and data signals. The multiplexed interface drives the 16 address LSBs on the same pins as the 16-bit data. Thus an external address latch is required to maintain the lower part of the address while the data is transferred. This latch is embedded in some NOR and PSRAM devices. The latch-enabled signal is provided by the FMC through the FMC-NL output pin. This signal is named address valid ANA-DV on some NOR flash devices. FMC-NEX is one of the four chip select signals, one per subbank. Regarding the PSRAM interface, the FMC accesses the right data through its by lanes FMC NBL 0 and 1. Bank 1 is used to address up to 4 NOR flash memories or PSRAM devices. This bank is split into 4 NOR or PSRAM subbanks of 64 MB each with 4 dedicated chip selects to interface with 8 or 16-bit synchronous or asynchronous NOR flash in multiplexed or non-multiplexed mode, 8 or 16-bit asynchronous SRAM and ROM, 8 or 16-bit synchronous or asynchronous PSRAM memories. The FMC outputs a unique chip select signal to each subbank and performs only one access at a time to an external device. The external memories are connected either to the NOR and PSRAM controller or the NAND controller and share address, data and control signals. The NOR PSRAM controller allows the configuration of various timing parameters for the supported memories, address setup phase, duration of the first access phase, address hold phase, duration of the middle phase of the access cycle, data setup phase, duration of the second access phase, bus turn around phase, duration of the bus turn around phase, clock divide ratio, number of AHB clock cycles or H clock within one memory clock cycle, data latency, number of clock cycles to be issued to the memory before the first data transfer, access mode. Bank 3 is used to interface with the NAND flash memory. It's divided into two memory spaces, common memory space and attribute memory space. Both spaces are similar. The common memory space is for all NAND flash read and write accesses except when writing the last address byte to the NAND flash device where the CPU must write to the attribute memory space. This allows the implementation of the pre-weight functionality needed by certain NAND flash memories by writing the last address byte with different timings. Each memory space is subdivided into three sections. Data section, 64 kilobytes, used to read or write data from NAND flash memory. Command section, 64 kilobytes, used to send a command to NAND flash memory. The address section, 128 kilobytes, used to specify the NAND flash memory address. The FMC generates the appropriate signals to drive NAND flash memory. The address, data and control signals are shared with the NOR and PSRAM controller. The command latch enable or CLE and address latch enable or ALE signals of the NAND flash memory device are driven by address signals from the FMC controller connected to address line 16 and address line 17 respectively. The ALE is active when writing to the address section and the CLE is active when writing to the command section. The FMC NAND memory controller includes support for the following features. Error code correction. The ECC algorithm can perform 1-bit error correction and 2-bit error detection per 256 to 8192 bytes read or written from or to the NAND flash memory. It's based on the Hamming Coding algorithm. Three interrupt sources can be enabled to detect a rising edge, falling edge or level on ready busy signal output from NAND flash memory. Weight feature management. The controller waits for the NAND flash memory to be ready before starting a new access. The MPU memory attribute of the FMC NAND bank must be configured as a device. Each common and attribute memory space can be configured with different timings for the NAND flash's command, address write and data read write accesses. The attribute memory space is used for the last address write access if the timing must differ from that of previous accesses in case of ready busy management. Otherwise, only common space is needed. Four parameters are used to define the number of age clock cycles for the different phases of any NAND flash access. Setup time, wait time, hold time, date bus, high Z time. The NAND controller offers three interrupt sources, rising edge, falling edge and high level detection on the FMC int pin when it's connected to the ready busy signal from the NAND flash memory. The FMC is active in run, sleep, low power run and low power sleep modes. An FMC interrupt can cause the device to exit sleep or low power sleep mode. In stop zero and stop one modes, the FMC is frozen and the content of its registers is kept. In standby or shutdown mode, the FMC is powered down and it must be reinitialised afterwards. Wearable applications require low power management together with a high quality user interface. This can be achieved using the STM32G4 FMC to connect the display thanks to its flexibility and widely programmable parameters to interface with LCD modules. In addition, the FMC or Quad SBI interface may be used to access an external flash memory containing all of the graphical content needed such as background images, high resolution icons or fonts to support multiple languages. Additional audio data for ringtones can also benefit from the large space offered by the external flash memory. Thank you.