 We begin the discussion on module 2 of the non-classical MOSFETs and in this module we talk of silicon on insulator SOI MOSFETs. Last time when we discussed we said or we have seen that the drain current depends upon the injection velocity and that injection velocity depends upon thermal velocity which is 10 to power of 7 centimeter per second and the product of mobility and the electric field at y equal to 0 that is here. At the point of injection what is the mobility what is the electric field that is low field. So, we talk of low field mobility that means mobility near the source end where electric field is low that is the one which controls the injection velocity. You will never get the saturation velocity of 10 to power of 7 centimeter per second, but it will be less than that how much it is low depends upon the mobility. So, what we said is if you want to get better performance you need to have higher mobility at low electric field that is at the source end because everything depends upon how much is the mobility when it is injected. These are very important particularly when you go to short channel devices because you are trying to get as close as possible to the saturation velocity or the thermal velocity. So, if you want the mobility to be high what we have shown last time is that the doping concentration in the channel should not be high. Number one the other factor which affects the mobility of electrons or carriers in the channel is the electric field in a vertical direction or normal direction. In a direction normal to the electric to the channel that is that E x which I have marked x is in that direction that depends upon what is the oxide thickness and also how much is the doping here is in the more or the doping more charges in the depletion layer comes up. So, the electric field in that direction will be higher. So, you can see that to reduce that vertical electric field you need to go to lower mobility. So, both these point to the fact that you need to reduce the mobility of doping concentration as much as possible. Ideally you can go to undoped such things are not possible in the classical MOSFET. You have to go to some special type of devices like the SOI MOSFET that is the idea. And also of course, supply voltage you must keep low to minimize power dissipation. Then you need to when you go to lower supply voltages you have to have lower threshold voltage. And to effectively turn off the device when the gate voltage is 0 when the drain voltage is present you must have excellent sub threshold slope. In the sense 60 millivolts per decade is important when you want to go for lower supply voltage. So, that if you have 0.3 volts as the threshold voltage by the time you reduce the gate voltage 0 the current will fall down by 5 decades 300 by 60. So, that is the idea of that. So, much important thing is to have these two mobility as high as possible by keeping the doping concentration as low as possible. And for getting these sub threshold slope 60 millivolts per decade just close to it is very it is impossible mostly in the bulk MOSFET. So, you have to go to this non-classical MOSFETs or what are these high performance non-classical MOSFETs then? One is the SOI MOSFET which you will take up in module 2. There you change the structure so, that you can control the doping concentration and reduce it. And you can have multiple gates. So, that the gate has tremendous control over the channel as compared to the drain. See the sub threshold slope and all gates affected short channel effects coming to picture more and more because the drain takes control of this barrier at the source end. Now, if you have wrapped around a gate which is all around the channel then the gate has excellent control on the channel. So, that is what in high frequency high performance nano-scale MOSFETs you when you choose you will see as you go on to the SOI MOSFET you can ensure that you get the sub threshold slope which is 60 millivolts per decade. The other approach that you use for this high performance devices is basically change the material from silicon to germanium where you can get high mobilities. Both electron mobility and whole mobilities can be higher than silicon only in the material like germanium. You can get close to 4000 centimeters per volt second for electrons mobility, whole mobility something like about 3000 as compared to 450 in silicon. Or you can go to materials like gallium arsenide where only the electron mobility is high, but the whole mobility is not high that all we will take up. So, germanium MOSFETs also we will discuss in the as a new material lot of research work is going on on that. Everywhere you will see that you have problem of the interface states killing the performance of the device. The another non classical type of device is the source and drain of the MOSFETs are metal semiconductor contacts that is the short key barrier contacts as compared to the p n junction. Why we should do that we will see the main reason to do that is to reduce the series resistance resistance of the source region. And of course, one more thing that I pointed out last time was you can have the channels which are strained. So, that you can control the mobility or increase the mobility by either increasing or reducing the strain depending upon whether it is p channel or n channel. Ultimately of course, you can go to gallium arsenide VSTFETs. Then there is one class of hetero junction devices called high electron mobility transistors because you can get very high mobility particularly when you go to low temperatures. This is the usual bulk MOSFET structure in a very simplified way. There are slight variations in all the things you have got the p n junction p n junction and gate gate gate poly silicon gate. Today people talk of metal gate also is the cross section of the silicon wafer bulk 1 0 0 oriented. This is where the device cross section. Now if you recall the discussion on short channel devices you not only reduce the dimensions in the lateral direction keep on shrinking in the direction. You also shrink in that direction vertically because only when you shrink vertically you can get shrinking in a lateral direction possible. For example, in this junction if I make this junction depth 10 microns let us say there will lateral diffusion. So, this junction will move into the channel at least 7 to 8 microns. So, it becomes very difficult to control the channel length reduce it to 1 micron half a micron 0.1 micron. So, you need to keep the junction depth very very shallow. So, when you keep the junction depth very very shallow you encounter with some other problems. Like when you put a metal here on the top if you have a metal there if it is aluminum particularly you run into problem because that can if this junction is very shallow it can spike through this junction it can short because there is p type material on substrate. Of course, you today you change the material to some silicides then that problem is reduced drastically. Main thing is lateral diffusion is the one which you want to control you want to keep the junction depth shallow. So, now instead of taking this conventional bulk MOSFET you go take make use of a SOI paper. You have the silicon at the bottom you have the red color that is SOO 2 then you have the silicon layer top. So, notice in the case of bulk MOSFET strictly you are using only this portion only the top portion only the dotted line that I have put below that it is of no use. So, the SOI is nothing, but the top layer cut there and realized on this side on this layer. So, if you go to this device there on the right hand side you can see it is nothing, but the same thing cut and put here it is not the way it is done. So, you start with the wafer which is silicon on insulator there are different ways of making these devices. So, if I have this is called box buried oxide it looks as if you have buried oxide below the surface it may not be buried really, but in some cases when you make the SOI you actually buried oxide we will see how to do that. So, SOI layer this you use now once you have this thing how much is the layer the junction depth here there is a junction here where it diffuses all through there is no p type layer the silicon is rutting on the oxide. So, when you put a metal there even if the metal spikes and goes through there is no short circuit because there is oxide below. So, you can use aluminum itself very comfortably here. So, you can see how much is this junction area see in this case the junction area is vertical horizontal vertical the horizontal portion may be at least few micron you must keep it wide enough. So, that the metal that you put here that may be taking 5 microns let us say then this must take at least 10 microns. So, that extra junction is present in that portion whereas here the junction is only here vertical that may be 0.2 microns 0.2 microns very small junction area what is the junction area the depth multiplied by the width it goes perpendicular to that area plane of paper it goes like that depth. So, depth is perpendicular to this plane here. So, W into the stage silicon that is the junction area whereas in the previous case is W into the total area there this may be large 10 microns or 5 microns, but this will be only about less than a micron you will see it is even goes to nano today. When you talk of nano devices you talk of the layers which are of nano dimensions 10 nanometers 20 nanometers of that order you will see the benefits of that as we go on. So, junction area is small here and you are not worried about reducing the thickness of the layer you are not worried about spiking metal sorting. So, shallow junction formation and metal spiking and sorting in the junction of what is available here will not be there and since the junction depth is very shallow here lateral encroachment of the junction into the channel is minimized. So, when you want to make smaller devices these are called beneficial. Now, let us just take a look at what are the different types of SOI wafers which are present. Classically or historically the SOI was not SOI SOS not save our soul it is silicon on sapphire. This is sapphire single crystal sapphire L 2 O 3 you can crystal grown you can buy it very expensive much more costly than silicon several times costly. On that you grow 100 oriented silicon epitaxially you can have this point of microns or of that order use this particular for making the device. Now, you see entire layer below that is insulator fantastic if you can get that you can get that people use this even today for some of the very sophisticated radiation hardened type of devices for defense applications they use this. But the very expensive you get 4 inch wafers not I do not think there are other dimensions are they bigger than 4 inch because of difficulty in going in the tail 2 O 3 that is a high temperature process. But there is some issue here the channel mobility here is not very high because the quality of this layer when you make it thin is not as good because this is does not match very well with the substrate lattice match is not so good. So, the quality is not so good. But if you are not looking at the high mobility if you are looking at other performance like radiation hardening and also if you are looking into the you know the routing capacitance. For example, when you connect one device to another device on the surface of oxide if this insulating layer is very thin the capacitance of this routing capacitance with respect to substrate is very very small. So, you know those parasitic capacitance are very small in this case and also when you make a device like that and you make a device like that the junction capacitance also is small because junction area is small. So, here you just make the device there you get junction area small capacitance small, take capacitance small that way you get much better performance. Ultimately in the integrated circuits you know that the culprit is just take a parasitic capacitance. So, you want to reduce that you can do that with this. So, most of the difference application they use that this is start with single crystal see it is a hexagonal structure that is why 0 1 1 2 is the orientation. That particular orientation only there is fairly good lattice match between between silicon and sapphire, but if you want a cheaper way of doing this you go to go to this type of structure where the silicon is an oxide you can choose it one micron whatever thickness you like not too thick. So, instead of taking the whole thing as sapphire you have got as I go to there this also will reduce the parasitic capacitance because of the cocter below that parasitic capacitance will be reduced. So, how do they do that? This is a very popular way which by which the SOI layers are made in IBM. In their mainstream integrated circuits they use the SOI layers which are called SIMOX layers. SIMOX is separation by implanted oxygen. Here actually you are really burying that oxide. How do you do that? Take a silicon wafer the full thing is silicon there cross section implant oxygen atom implant atoms itself implant in that when it comes it comes it as ion, but it gets neutralized after implantation it is neutral. So, implanted at energy is like 100 to 200 kilo electron volt. So, that the oxygen atom gets inside the layer and it is implanted into the bulk of silicon. The dark region which I have shown here is actually the region into which you have implanted. Actually what happens is when implanted depending upon energy the depth at which it is implanted is decided may be half a micron 0.1 micron that depends how much lower energy will be implanted close to the thing close to the surface. Now, I put a band of region because when the implant the impurities or any material it is not going to stay in one place. It goes through a surface most of them land at one particular depth, but there is a spread because after all where it lands depends upon the number of collisions it experiences. In the sense it comes with let us say 100 K e by energy. It collides with one atom the host atom it is like a billiards ball. So, it collides with that gets scattered the lattice atom of the host atom also moves even the billiards when you play that move this also gets reflected. So, in one collision it loses some energy after undergoing several collisions it comes to rest. So, how far it goes to rest depends upon what was the energy, how much energy it loses in each collision and how much it loses also depends upon the host atom and whether it hits head on collision or at a slight angle. So, if it is head on collision then maximum energy will be lost in one collision. If it is at an angle cost it of that energy will be lost it is actually proportional to the product of the two masses. Revere masses will lose energy faster it will be difficult to implant deeper. So, this oxygen atom you will see at a spread because depending upon the angle and number of collision experiences it is a statistical phenomena it will landing at one place there here it will be around that region that is why that depth band is put there. So, when you implanted it it was just oxygen atom. Now, raise it to high temperature like 1300 degree centigrade silicon does not melt at that temperature because melting point is 1400 degree centigrade. So, that I change the color here because it has become a servo too, silicon dioxide because of oxygen reactive to silicon. So, what happens is when the reaction takes place there will be swelling volume will increase you know that if you just look at number of atoms per centimeter cube of silicon is 5 into 10 to power of 22 per centimeter cube. So, I will just put some numbers here just we will come back to this slide. So, if I have one micron oxide formed there it has it is the thickness of this is one micron I am giving an example. The thickness of silicon is 0.44 micron even in thermo oxide here also 0.44 whatever atoms which are there in 0.44 micron would have reacted with oxygen in 0.44 micron there will be number some number of atoms will be there into 2.27 number of oxygen atoms will react to that into 2.2 into 2 whatever number of atoms is there into 2 for one silicon atom 2 oxygen atoms. So, twice the number of oxygen atoms will react with that to get this thickness, but the volume or the thickness will be 2.27 times. So, what I have just put here is to make it clear number of atoms in silicon 1 micron silicon dioxide is 5 into 10 to power 22 into 10 to power this is number per centimeter cube silicon atoms into 10 to power minus 4 is in 1 micron though so and so second atoms are there. So, in 0.44 micron silicon that will be the number of atom present number of oxygen atoms in 1 micron will be that into 2. See so many number of silicon atoms will react with twice the number of oxygen atoms. So, that is number of oxygen atoms. So, what I have said is in 0.44 micron thickness of silicon how many silicon atoms are there. Now, twice the number of oxygen atoms will react with that to give you the SiO2 which is 1 micron that is the idea. So, whatever was 0.44 into 2.27 is the thickness because it expands. So, in 1 micron there is a thing if I take 0.4 micron oxide if I want that will be 4 times that about 1.8 into 10 to power 18 oxygen atoms per centimeter cube centimeter square. I put that number because I have written here implant 1.8 into 10 to power of 18 centimeter square of oxygen atoms to get about 0.4 micron that is 400 nanometers that working out I gave here. So, what we are telling is you put that number of atoms you will get 0.4 nanometers of 0.4 microns thickness of buried oxide. So, this involves high temperature process this is what IBM uses for realizing the swive wafers which are called SIMUX. Typically, how much is the buried oxide is controlled by how much thickness is there controlled by what is the implantation dose. So, that is because it consumes so much of silicon atoms usually it is 100 to 400 nanometers is the thickness. This annealing is done for very long time because after all you have implanted oxygen and the reaction takes place there is a technology. So, you can see you require lot of implantation system etcetera for this and industries do that, but if I want to do it in our lab in a university level where you do not have implantation which will cost you several cores and lot of space will take you use a simpler methods that is BESOI bond and HBAC this is very simple the SIMUX implant anneal you get the oxide layer buried. Here thermally oxidized silicon you want 1 micron grow 1 micron 0.1 micron grow 0.1 micron take another silicon wafer put them together it will bond provided you allow it to bond. In the sense what you do is this wafer is there another wafer is there both of them you must make hydrophilic you give a chemical treatment. In fact, when you use some chemicals like ammonium hydroxide, ammonia, H2O2 etcetera for cleaning up automatically there is hydrogen. So, HCl and hydrogen peroxide you use for cleaning up the wafer then they have water cleaning automatically there are OH ions. So, it is when you put them together it is bonding between the OH and OH from the two atoms two layers you call it as under wall force a weak binding. So, put them together press it you can heat it to 400 degree centigrade totally good bonding takes place take it to high temperature like 1100 degree centigrade couple of hours. It was OH OH bonding and heat it at high temperature hydrogen comes out you get silicon oxygen silicon bonding. So, it is completely as I would. So, this bonding takes place you have got a single wafer now which has oxide in between. So, you got virtually buried to the oxide, but now this is 300 micron 300 micron how do you get SOI? H that layer to reduce the thickness we can just keep on etching it chemically wet chemical or dry etching you can use. How much thickness you get depends upon the H duration there are different ways of controlling the thickness you can get this exact thickness. So, this is the process press the two hydrophilic wafer what is hydrophilic hydro it is not hydrophobic water heating and water loving. So, OH ions are there then afterwards any then etch it is called bond and H by PSOI. In fact, this type of bonding we can do in the lab level where if there is very clean class 100 or even better clean rooms are there you can do the bonding. This type of wafer are very popular in members because you have this thin layer here you remove the silicon from the bottom here you get a membrane you just etch out somewhere in between the center from all the way you have got oxide and then this silicon which is a membrane and I will not go into that this is in the MAMS course that we talk of other method is not cut see here there is one issue. See for making one SOI wafer you have used two wafer polished wafer. So, two wafer and at the end of the process you have other wafer you have just dissolved it is a waste. So, in order to overcome that and also precisely get this thickness here the precise thickness is controlled by timing of the heat which may go off a little bit if you want to if you want 20 micron thick layer 0.5 micron difference in the 20 you may not very much if you want one micron thickness here that becomes very crucial. So, in those cases and also if you want to use only one wafer per SOI what you do is use smart cut method this patent of some company. So, what you do is take this is dark is coming afterwards take a silicon wafer oxidize it to get the buried oxide oxidize it implant hydrogen through the oxide. How much deep the hydrogen goes depends upon the energy of the hydrogen it is about 1 kilo volt energy in a implanter if you use it will go about 8 nanometers below surface that is 80 angstroms. I use 10 kilo volt it will be 800 angstroms 80 nanometers. So, what deep you have got this hydrogen below the surface depends upon energy that is under your control. So, remember I can get this even as low as 0.1 microns or even as low as 80 nanometers very easily. So, once you do that you take another wafer and bond on the top on the top of that you bond it. So, that bond this is the B is called the handle wafer see for example, here when I get the SOI this is the handle wafer this is not doing any job it is only the mechanical support for holding this SOI layer. So, that portion will be the handle wafer which comes below. So, once you do that what happens is when you have hydrogen implanted it results in cavities that is hydrogen makes cavities in silicon in this layer. You put heavy dose of about 10 to power 15 per centimeter square you will get weak link between that this portion and this portion cavity. So, hydrogen is included there in the silicon that is why it makes cavities. Now, when you bond it and anneal it even at low temperatures this fits up because of the weak link there it just comes apart it is like putting a hat and taking it out. So, that comes out like this. So, what has happened now this layer thickness is this thickness and that thickness is controlled by how much energy you had hydrogen atoms. So, you can precisely control the thickness here you can precisely control this thickness. So, you put it upside down you have got the SOI layer on top you have the wafer like that you put it like that you get the you put it like that you get the SOI layer reverse it. So, now you can see this layer thickness of 300 microns out of that let us say half a micron is gone on to this. So, still you have got 299.5 microns of silicon which is separated. So, once this is separated out you have got the silicon on insulator already you have to put it upside down of course. And this wafer which was there is available for you for reusing all that you have to do is you may have to slightly polish it polish it reuse it start all over again oxidize and go through with it. So, in effect what has happened is you have used 2 wafer to start with, but one wafer is available for you reuse ultimately only one wafer is used one advantage other advantage is the thickness is precisely controlled by the implantation energy. So, this is very popular commercially available. So, you can buy Psymox wafer you can buy smart cut the only thing that you will be concerned be if I want for MEMS application I may need a thick membrane say 20 micron etcetera that you may not be able to get because you will not be able to have energies of that height implanted deep below 25 microns. So, in that case what you do is take this wafer which is 0.5 microns grow epitaxially 10 microns of silicon then you will get 10 microns of a soil here. So, if you want 10 micron of smart cut this wafer you can buy it, but if you want thicker ones better way to go is this one because you do not worry about slight change in thickness, but waste one wafer you have used two wafer to get one. So, now let us see the benefits of those are the technologies some other technologies also have come, but these are the most popular techniques. Now, already I have mentioned to you some advantages of the bulk silicon MOSFET and the SOA MOSFET clearly the drain and source junction capacitance are small here because junction area only this much into the W channel width and here that plus all this thing it will be order of magnitude the area of the junction will be large compared to that because this will be sub micron this will be several microns because it has accommodate also the metal content there you cannot have this nano here this will be the one which will occupy. So, the junction capacitance is small straight away one straight capacitance is reduced to the routing capacitance from one device to other device because of the buried oxide below is also reduced plus the junction leakage current junction leakage current depends upon the area of the junction in the SOA layer the junction area is smaller. So, leakage current is smaller. So, if the leakage currents are smaller even at room temperature you will be able to use this for high temperatures. So, the bulk MOSFET when you can use for 100 degree centigrade probably but devices here you can go to 200 degree centigrade fairly comfortably. So, higher temperatures if you want to use SOA MOSFET is the way to go also you can use it in the radiation environment because the problem in the radiation environment is and the high energy particles like the gamma radiation etcetera comes into impinges here it generates whole electron pairs in the silicon and the whole electron pairs are generated here in the depletion layer below this point it is collected it gives rise to the drain current large drain current plus it will also if you have a CMOS structure it will also lead to latch up problem that we will see what it is because of coupling between the P channel and N channel MOSFET you will have the problem you will not have the problem. So, this type of devices can be used for high temperature and operation in harsh environment like the radiation environment ok capacitance is low other benefits this is actually to show whatever I have said here you can see this is junction capacitance which depends upon looping and this is the junction capacitance which depends upon the buried oxide which is very thick. So, capacitance will be small in fact there is no junction here it is a capacitance this layer and this substrate and this area can be small here and junction is only here I am sorry it is only the buried oxide we are showing it is easy to see here it is only buried oxide this capacitance from here to down put in this and this this is reiterating whatever I have said before and also here we can have capacitance between this and that below the field oxide field implant additional capacitances. See here what we have shown is that the full layer is there you can etch this silicon to have MOSFET completely isolated from other MOSFETs. If you go back into whatever you had discussion in the case of MOSFET integrated circuits below that between the two transistors you have that P plus implantation to prevent it from inverting here you have got a thick oxide very thick oxide below that and if you want any implantation you put it down there, but you do not need that because complete isolation is there there is no silicon. Now what you can do will be one question there is a step here from one device to other device, but you want a planar structure why do you want planar structure lithography becomes difficult if there are steps big steps. So, what you do is suppose I want to etch silicon from here if I do not have that it is a step. Now instead of that what I do is I etch the silicon from here supposing this is one micron silicon just as an example a soil layer is one micron I etch it leaving 0.44 micron and this is nitride deposited on the top so that by leaching it can protect. So, etch a soil layer partially leaving 0.44 micron of a soil layer un etched as shown here. Now oxidize it see if I did not have this nitrides low pressure C V D is a technique by which you deposit by the reaction of silane and ammonia you can get silicon nitride that nitride is tough one tough in the sense if you put it in an oxidizing ambient it oxidizes very very slowly. For example, if I have nitride here and a step here and I subject it to oxidation on this surface this layer will get oxidized the oxidation rate depends upon the temperature. So, when this oxidizes this portion hardly gets oxidized because nitride is there nitride the oxidation rate of nitride silicon nitride 3 and 4 is about 30 times smaller than that of silicon. So, even by the time if I grow 0.1 micron of oxide nitride will oxidize 1 by 30th of 0.1 micron hardly any oxidize there. So, nitride is intact silicon is not getting oxidized protecting it from oxide. So, that means what you are doing is you are oxidizing locally here that is called local oxidation of silicon or low cause at some time when we were discussing in the field oxide you see the local oxidation it may get inside slightly here, but ideally it will be the same. So, now, if I had used 1 micron silicon and 0.44 micron silicon was left by etching I oxidize it this silicon after oxidation expands 2.27 times and this thickness becomes equal to 1 micron. So, 0.44 micron of silicon when you oxidize thickness becomes 1 micron. So, you can see that oxide thickness here is 1 micron and this is in flash with this you can ship off that nitride afterwards or the phosphoric acid or dry etching you can remove this nitride. So, you can have the plane parallel structure silicon isolated from each other with oxide all round. You can see that the silicon layer is isolated from the bottom silicon layer like that and each island is isolated by oxide in between and there is no step all these advantages are there. So, that is what I have shown here I want to make CMOS how do you make you can first create this island. One island another island that may be very lighted out P type all over. So, what you do here is protect this side completely you can implant the source strain regions always you implant and then annihilate. I am not going through those steps you can create make this transistor by protecting the other side implanting source strain region. Now, you can protect this side with photoresist you can use photoresist as mask for implantation that is a nice thing about that. Clue lithography these are photoresist from some portion implant wherever photoresist is not there implant it see if you want we have a P type layer here completely I can implant on to this n type dopants make this entire layer and n channel n type material. So, instead of making P well n well etcetera you make this P type and n type P type originally make it n type. Then the usual procedure to make the source strain regions here source strain regions here those steps are same I am not going through that this is policy this is policy. So, this is the structure of CMOS schematic what about the bulk MOSFET this is schematic simple version if I do not do anything exotic what we will have will be this is the n channel MOSFET that is the source drain of the n channel MOSFET and a source is connected to a guard ring the ground bit. So, because after all you see substrate is connected to the source in the MOSFET that is always there in you make a MOSFET if you remember you always connect the substrate to the source. So, that the bipolar action of that comes out of action. So, you have this connected to the ground that is the n channel MOSFET and to create the P channel P channel MOSFET you had implant n type regions n well and here also you make this n plus to terminate it. So, that you can make ohmic contact and these two together substrate connected to the source substrate connected to the source. So, these are these are usual structure there may be variations of this arrangement. Now, you can see what happens here I do not know whether you are aware of the thyristor action PNPN structure you can see here you got PNPN this is a thyristor wherever you get that type of structure the thyristor characteristic is it is off usually, but due to some spurious pickup somewhere let us say this injects holes into that supposing this drain voltage from spike there may be voltage spikes coming up or some noise pickup this voltage goes up this gets forward biased more this injects holes and this PNP transistor that is PN and P that is what I have marked here this PNP transistor injects electrons into the emitter to the base collector and collector is drawing the base of the NPN transistor this is the NPN NPN. So, this PNP transistor drives the base of the NPN transistor if there is spurious pickup even if there is a radiation that can generate whole electron pairs and that can give forward bias this there will be injection. So, if it drives the base of this transistor what happens NPN transistor you drive the base this turns on. So, this emitter current increases that drives the base of the PNP transistor. So, it is a positive feedback situation PNP somehow to go triggered base driven other base drives goes on building up and current goes on building up till the external current is limited by till the current is limited by external resistance either that or device will get damaged there is no limiting factor in logic circuits there will be malfunctioning of the logic state. So, you want to prepare how to prevent that prevent this collector driving the base of this transistor there may be spurious response here prevent it from driving this base of the transistor how to do that isolate this by putting shallow trenches you can remove this portion completely put a trench there put oxide I do not know I have the diagram here yeah you can see here. So, you have put trenches in between here you see already by the way you made the very thin layer is there you can local oxidation you can do you can isolate them physically isolated electrical isolated completely from each other. So, you do not have to worry about the latch up problem this is called latch up because once it is a driven positive it went on building up it gets it remains transistor gets turned on it remains in on state how can you turn it off either you have to remove the supply you cannot do it in integrated circuit you cannot turn off or you must have commutating circuits where the force the current in opposite direction to bring it on all that you can do in power electron is probably, but here you cannot do it in the IC. So, you must prevent that latch up phenomena which is a generic problem in the bulk CMOS it is not there here. So, in bulk CMOS you know you do this type of thing you can see that you see how complicated the structure is you have got lightly doped regions you have got these regions all these things and in between you have got a trench created it is not enough if you create trench you have to again fill up that with oxide this is shallow trench, but it has to go deep enough so that covers all these portions. So, what they do is trench you create fill up this oxide then you have to make it plain parallel by lapping and polishing. In fact Intel does not go for SOI that is what they say they believe in shrinking the dimensions in the bulk CMOS, but the process is so complicated that to get the planar structure you have to lap it. Lap it means that abrasive reduce by force holding like that rubbing it. So, yield may go down in that in fact when we were talking some of the people in Intel they say yeah that happens over yield. So, but still I think everywhere they try to see how far SOI can be used. So, these problems are not there in SOI and this is another version of that I just show this is more simplified way different way the SOI like this N channel P channel metal contact metal contact oxide everywhere. Redrawn in a different way that if there is thick layer you can go like that, but you can have them planar lecture almost like that. If it is very thin layer usually you will see that you will go to very thin layers in integrated circuits. Now in summary of these things about the SOI we have seen the technology of that how to make them we have also seen what are the benefits benefits are low parasitic capacitance, drain source junctions and interconnects all those capacitance are reduced because of the thick buried oxide. Ability to operate at high temperatures and radiation environment I am showing even when you talk of a single MOSFET it is that simpler technology no welds and trenches shallow junctions easy to fabricate because there is no junction here it is only at the there is no junction here it is only here that is what makes this capacitance also less. Then better dielectric isolation devices are isolated P channel and N channel MOSFETs are isolated that is dielectric not PN junction isolation if you go to the bulk thing it is a PN junction isolation N well and P well things. In both vertical and so the isolation is both in the vertical direction substrate is isolated and in lateral horizontal direction latch up free CMOS we discussed that low voltage operation I did not we will understand that when we go into the analysis of this device that is you can if you if you need low voltage operation low supply voltage you need to have low threshold voltage you will be able to go for low threshold voltage if the sub threshold slope is ideal 50 millivolts per decade you can never get that in the bulk MOSFET between 70 80 or 90 here you can go right up to 60 63 millivolts and that of that order in the SY we cannot get 60 may be 63 so very close to that that is why you can go to low supply voltage and that means low power devices when you want to go for low power integrated circuits invariably we will go in for the SY type approach ideal substrate should slope 50 millivolts per decade. Now that we will just continue with few things now on this that the summary of summary of what we have discussed now so far. Now what are the what are the what is the structure of a SOE MOSFET let us quickly see that since there is some few minutes are there we can discuss that we can take on from there next lecture so substrate I showed it thin but it is thick one buried oxide and channel device gate oxide gate notice there are the structure is different from the conventional bulk MOSFET I can have gate on the top I can have gate on the bottom because there is oxide here but you will say this oxide can be made thick thin and have good control on that I can make this also thin but you may lose some of the advantages that you have in the isolation but we will see that can be overcome by appropriately choosing the structure called thin fact you can still have thick buried oxide but we can have both top and bottom it will be on the bottom it will be coming on the sides. If I have a SOE layer like that now we are talking of gate from here gate from here I have the SOE layer like that I can have the gate like that and I can have thick oxide below so gate from this side this side this side all around wrapped around that type of structure you can get to understand that before you understand we will just so you still can have the thick buried oxide get that type of structure. What we are pointing out is you can have more than one gate or wrapped around gate you can have in the case of this type of thing that is really not conventional structure. Now you can have symmetrical means if I have two gates symmetrical means was the work function of G 1 and G 2 are same the thickness of this oxide and this oxide are same that is symmetrical dimensions here and here are the same thing that is symmetrical if any one of them are not same we can call one symmetrical. But now notice one thing if I do not talk of anything else I use this as this layer is thick enough I can have the MOSFET structure with the inversion on the top I can have the MOSFET structure by applying this bottom gate inversion at the bottom so with the same channel length I will have double the current current from this top gate current from the back gate. But you will be wondering what the use of that but if I have a gate like this I have wrapped around gate this thing is equivalent of top gate is bottom gate this may within thickness will be that whatever you have got there. So, you can have current much more than that and you can keep on reducing the thickness entire layer is inverted see the inversion layer we take it as a charge sheet actually there is a charge from the surface going down below similarly if this gate is inverted there is a charge extending into the bulk if the thickness is very small the entire layer will be inverted that is called volume inversion you can have that type of thing there are terrible or terrific advantages tremendous advantages of volume inversion we will see that you can get mobility which are very close to ideal value and doped case if I can make the whole thing and doped but also you will see how it is see if I have two gates here the two gates are competing to have control on the channel. So, the gate the drain is prevented from having control on the channel to a less extent because these two are there from both sides coming. So, the short channel effects are definitely reduced here qualitatively you can have if that is the thing you can have undoped ultra thin body MOSFETs also those are the different types you have got today people talk of undoped layers here we will have very interesting features which we will be discussing. Now, you will have you will have fully depleted or partially depleted MOSFETs see if you go to bulk MOSFET what happens the thick layer is there only a top gate there is inversion part of it is depleted rest is bulk. Here part of this layer will be depleted from front gate part of the layer will be depleted from that gate if the both the depletion are meeting together that is fully depleted if the they do not meet together it is partially depleted. So, you can have fully depleted or partially depleted partially depleted we will see that operation is same as the bulk MOSFET. Why middle region is not depleted only so you have the entire theory that you discuss for the bulk MOSFET top gate you can discuss and the bottom gate you can discuss at the two there is no need of new theory, but if it is fully depleted the entire theory will be different. You have to go into the modified discussions on this particular type of device I think I will get back to those full details of these SOE MOSFET operation theory involved etcetera in the next lecture. So, we have gone through the many advantages that this SOE type of device is there and how to achieve that what are the characteristics of devices we will discuss in the next one or two