 Hello, and welcome to this presentation on designing and optimizing your NFC system. My name is Dan Marino, and I'm an application engineer for ST and support our RFID portfolio. Today's agenda focuses on designing the RF portion of your NFC system. We'll start by explaining the matching circuit, what it does, how it operates, and what components are used. We'll then take a look at antennas and the important parameters that are needed to properly calculate the matching circuit components, as well as how to measure them. Next, we'll take a detailed look at our antenna matching tool and walk through the steps needed to determine the matching values. Finally, we'll discuss how to optimize both the antenna and the matching circuit after the values have been calculated, followed by a brief overview of the design tools available to our customers and layout suggestions for your designs. The matching network in an NFC system essentially defines the analog and RF performance of the system. This is why it's so critical that it be designed efficiently and correctly. Let's start with a brief overview of a typical system block diagram. Here, we see the digital portion that encompasses the MCU and a part of the reader IC. The interface to the reader is either SPI or I2C, and there's a digital and RF power supply applied to the reader. It's important to note that the difference between an NFC reader and an NFC controller is that the NFC controller has an MCU built in, as indicated by the segmented blue line, and the interface is NCI, which is NFC controller interface. For this presentation, we'll focus on a standard NFC reader. The analog RF circuit consists of an EMC filter, the matching circuit, the antenna, and the receiver attenuator. In the following slides, we'll go into more detail of each of these blocks and their individual functions. So the first question is, why do we need a matching circuit? Essentially, the matching circuit matches the output impedance of the reader, which is mostly resistive to the antenna, which is primarily inductive. If we were to look at a vector diagram of the antenna, we would see a very large inductive component and a very small resistive element. The resulting vector would look similar to what we see in the bottom right corner of the slide. So the ultimate goal is trying to make Z out equal Z load. Because the antenna is mostly inductive, we have to add capacitance to counter the inductive component of the antenna. We do this in the form of a series and parallel capacitance. This seems very easy and straightforward, and if this were the only step involved, we would be done. However, as we'll see, additional components also affect the values that we place here. The output of our reader is a 13.56 MHz square wave. In order to remove the high-frequency component of the output, an EMC filter is needed. This filter is typically a two-pole, low-pass filter with a cutoff frequency of approximately 13.56 MHz. This will add both inductance and capacitance to the output that will also have to be compensated for in the matching circuit. Additionally, the RX attenuator will also add additional capacitance that needs to be adjusted for in the matching circuit as well. Here, we see the entire output circuit connected to the differential outputs of the reader is the EMC filter, which is a two-pole, low-pass filter consisting of an inductor and a capacitor. Following that is the serial and parallel capacitor and the damping resistor, and finally the antenna. Also shown is the capacitor divider, which serves as the receiver attenuator. Notice that there are two capacitors in parallel, C405 and 406, and C407 and 409 for the parallel capacitance. The reason for this is to provide the ability to fine-tune the value if automatic antenna tuning is not used. Now, let's take a closer look at each of the output circuit components and their functions. A common question that's asked is, what type of antenna should I use? We typically suggest a two-turn antenna with an inductance value between 200 nanohenrys and 1 microhenry. An important item to consider when selecting the inductance of the antenna is that a larger inductance will necessitate a smaller parallel capacitance to achieve resonance at 13.56 MHz. If the design intends to use automatic antenna tuning, it's best to design the antenna with an inductance in the lower range to allow for the added capacitance of the tuning caps. The EMC filter function is to reduce the harmonics generated from the RFO stages. It's no big surprise that the cutoff frequency is set to approximately 13.56 MHz. The matching and serial capacitor essentially controls the impedance match from the EMC filter to the resonance circuit. It also cuts the DC path between the two RFO outputs. And finally, the parallel capacitor forms the resonance circuit with the inductance created by the antenna. The Q factor adjustment can be either a serial or parallel resistor near the antenna. Its main function is to set the Q of the system. Because it can only reduce the Q of the antenna, the antenna Q must be higher than the required system Q. A higher system Q produces more field strength but reduced bandwidth, thus used for lower data rate protocols. A lower system Q produces less field strength but allows for more bandwidth, thus supporting higher data rates. Target system Q values are typically between 8 and 25 and are based upon the protocol data rate chosen. And finally, the receiver attenuator reduces the RFI input to less than 3 volts peak to peak per the datasheet by means of a capacitive divider. The target matching impedance is directly related to the amount of field strength the reader will produce. A higher matching impedance will produce less field strength, lower power consumption, and higher efficiency, while a lower matching impedance will result in higher field strength, higher power consumption, and less efficiency. The matching impedance range is between 8 to 20 ohms, but in most cases it will be between 10 to 30 ohms. So the common question is, how do I control the output power of the reader? The answer is through the matching impedance. In almost every NFC application, the antenna is usually defined by the mechanical space that's allotted for it, meaning that there's no standard antenna. This is the reason that a matching circuit must be designed for each antenna. In order to do this, it's important to understand the various antenna parameters, how they can be adjusted, and finally, how they are measured. Here we can see the main parameters associated with the antenna. Coincidentally, four of these parameters are needed when calculating the values for the matching circuit. Of major importance is the Q factor of the antenna. This parameter must be higher than the required system Q. As stated previously, typical system Q values range between 8 to 25, so the antenna Q needs to be greater than 25. The other parameter that is somewhat important is the inductance of the antenna. Again, as mentioned before, a high inductance value will lead to a smaller parallel capacitor value. This becomes critical if you're considering using automatic antenna tuning in your design. This table shows you how to manipulate these parameters by adjusting antenna geometry. In order to calculate the matching component values, we have to measure the antenna parameters. We do this with a vector network analyzer and measure the DC resistance at 1 MHz. This is marker 1 here on the S11. We must also measure the inductance at 1 MHz. In the example on this slide, the inductance was calculated at 13.56 MHz. However, the antenna design tool that we will see in the coming slides is expecting this value to be measured at 1 MHz. We must also measure the self-resonant frequency. This is marker 3 here on the S11. In addition, we have to measure the parallel resistance measured at the self-resonance. These measurements can be done with an inexpensive VNA, such as the Mini-VNA, from Radio Solutions. In order to make it easier to calculate the matching values, ST offers an antenna matching tool that is available online. In the next few slides, we'll cover how to use the tool. Here's what the antenna design tool looks like. The first thing to do is to select the device and the topology that will be used for the reader implementation. This covers both the ST25R3911B and the ST25R3916 families. Upon selecting the device and topology, the associated circuit diagram will appear in the tool. This includes single-ended, with and without automatic antenna tuning, single-ended 50 ohm, and differential, with and without AAT. Here we can see some of the associated topologies. Once the configuration is selected, the measured antenna parameters are input into the tool. Here you can select if you want a parallel or series damping resistor to adjust the queue. Then the preconditions are set, which is either EMVCO or default. Choosing one of these will automatically select the EMC filter cutoff frequency, the target matching impedance, and the target system queue. These values can also be put in manually. In addition, you can select what EMC inductor is to be used along with its DC resistance. When these values have been input, you can select calculate matching values, and the calculated values are displayed on the circuit diagram. It's important to note that this calculation does not take into effect trace resistances or parasitic capacitances of the board layout. This is why we have built in a simulation tool. This also helps because the tool will calculate capacitor and resistive values. They may not be standard values. After the component values have been calculated, select save and simulate circuit. This will open the simulation tool. When the simulation window opens up, several blocks will display that include the simulations that have been run, the circuit models that have been used, AC equations, and most importantly the circuit components seen here in the expanded window. Here one can change the calculated values to standard values and see their effect on the S11. It's also possible to change the capacitor divider that sets the input level to the receiver. After changing the component values, you would then simulate the circuit by selecting the simulate icon at the top of the menu. It's the one that looks like a sprocket. This will bring up several more windows with results from the simulation. Here we can see the filter response info and more importantly the impedance match. The S11 we see here is ideally what we want the match to look like. You'll notice that the resonant frequency is close to the real axis and therefore mostly resistive. In addition, the matching impedance is within the recommended values. Additionally information regarding the antenna voltage, the receiver input, and the phase and amplitude is also provided from the simulation. The receiver input is very useful information as it will provide info as to if the capacitor divider on the RFI pins needs to be adjusted. The antenna voltage info is helpful especially when using the AAT function on the 3911B since the trim pin values have to be kept under 20 volts. So an output swing of more than 40 volts peak to peak would mean that the trim pin inputs would be greater than 20 volts, which would necessitate a capacitor divider on those pins. So now we've measured the antenna parameters and calculated the matching components. And we're done, right? Well, not quite. Now comes the real work. So what are the next steps? As mentioned before, the simulation does not take into effect the traces on the board. So in order to check if the matching is correct, we have to install the components on our board and re-measure with a VNA. This time we measure at the RFO pins with the power off, unless we're using AAT. We'll look at that later. We then compare it to the simulation and then adjust the populated values so that the measured S11 looks close to the simulated S11. Once they are similar, you then begin testing and optimizing based upon current consumption versus read range. Typically, this involves achieving the desired read range and then increasing the impedance match to reduce the current consumption to an acceptable level. So naturally, the next question is, how do I know what components to change in order to achieve the simulated results or to adjust the impedance match? Here we can see a cheat sheet of sorts that shows how each of the component values affect the S11. Previously, I gave a brief description of what each of the components controlled. However, in reality, changing one component will necessitate adjusting the other values as well, since all of them work as a whole. So looking at this slide, if one wanted to increase the impedance match, it would generally increase the serial capacitance. But additionally, you would probably also have to increase the parallel capacitance to put the resonant frequency back on the real axis. Unfortunately, this is the type of scale that comes with time. But the good news is that once you've increased the serial capacitance and re-measured, the resulting S11 would show you that you would have to increase the parallel capacitance. So ideally, you want the measured S11 to resemble this plot. The resonant frequency is very close to the real axis. However, in some cases, you may want to optimize for antenna loading. In order to do this, it's important to understand the effect of the device on the antenna resonance when it enters the reader field. Here we see the effects of both a card and metal approaching the reader antenna. We see that as a card approaches the antenna, the resonant frequency moves towards a lower impedance, while metal will move the resonance in the opposite direction. In both cases, the resonance moves along the real axis. So why is metal so important? Because most phones tend to contain metal, and if one were to optimize for communicating with phones, then perhaps you would want to select your match such that it was located at a more optimal position to account for this loading. This would mean moving your resonance further clockwise on the circle, thus increasing the parallel capacitance. The opposite would be true for optimizing card reads. So beyond optimizing static values placed on the circuit board, one could also use automatic antenna tuning to do this on the fly. The adjustment range is dependent on the values used. So larger values mean more adjustment range, but less granularity. Smaller values are just the opposite. As mentioned earlier, this feature should be considered when doing the matching, primarily because it will affect the value of the parallel capacitor and potentially impact the inductance value of the antenna. Automatic antenna tuning can be used to improve both the phase and amplitude on the received signal. Here we see the two different methods the ST25R family uses for automatic antenna tuning. Above, we see the ST25R3911B that uses binary weighted capacitors that can be switched in to change the parallel capacitance value. Below, we see the ST25R3916 that uses variable capacitors that are controlled by onboard DACs to potentially change both the serial and parallel cap values. In both cases, the RFI signal is monitored, and adjustment of these values are based upon an algorithm that can optimize amplitude, phase, or both. In order to design with automatic antenna tuning, the antenna is matched just as before. In the case of the ST25R3916, three-quarters of the voltage-controlled variable cap value is subtracted from the calculated parallel or serial cap, and that becomes the new value. This is because the voltage-controlled variable cap adjustment range is only on the top 50% of the full value as seen in the diagram to the right. For the ST25R3911B, the highest trim value is subtracted from the calculated parallel capacitor, and that becomes the new parallel capacitor value. In both cases, the subtracted values are reinstalled when the device is turned on, allowing the adjustment to be in the center of the range. Fortunately, our antenna matching tool takes care of this automatically by selecting the automatic antenna tuning topology version. The complete schematic will be displayed with the matching values after calculating matching values is selected. In addition, these values will appear in the simulation where they can be changed and simulated. In order to check the matching with automatic antenna tuning, it's very important to turn off the output drivers, since the device has to be on in order to switch in the capacitor values. If not, the result could be damage to your VNA. For the ST25R3911B, register 27 needs to be set to FF in the register map. Next, check to make sure the field is still off. From here, you can adjust the trim values in the antenna tuning tab of the GUI and see the range of adjustment that's possible. With the trim values set to 8, you should be in the middle of the range. For the ST25R3916, register 28 must be set to 7F and then ensure no field is being generated. Again, going to the antenna tuning tab for the 3916, you should be able to see the range of adjustment by changing the variable cap values. Because the ST25R3916 has the ability to adjust both the serial and parallel caps, the adjustment range is much more expansive compared to the ST25R3911B. Here we can see a comparison of the adjustment range that is achievable for both devices. For the ST25R3916, the impedance match can be placed anywhere within the shaded region, while the ST25R3911B simply moves it around the circle. Now that we've gone through the matching procedure, let's take a quick look at some of the design tools available to you to prototype your design. ST offers several hardware platforms to evaluate and prototype with our NFC readers. Both the ST25R3916 and the ST25R3911B have discovery boards as well as nuclear shields. The difference between these boards is that the nuclear boards tend to be self-sufficient in that they run a simple polling loop and indicate what type of card has been read. Discovery boards typically require a GUI that controls the board, but allows total access to the device, meaning that all registers and settings can be accessed via tabs in the GUI. In general, I typically suggest nuclear boards for software development since they provide a known working reader platform. The discovery boards I suggest for hardware development for few reasons, but primarily because they can be used to drive a customer antenna or a customer board. It's also a good platform for checking antenna matching. In all cases, the software, GUI, source code, and design files are downloadable online to facilitate your implementation. For those developing payment solutions, we also have an EMD Co. reference design based on our ST25R3916. It includes an L1 stack, a software GUI to control it, and of course the board, which has passed an L1 debug session. This reference platform is available by request. And of course, we have our antenna design matching tool, which you've seen earlier. It's available for download from our website for free and includes the QWUX simulator. The tool can be found at the URL listed on this slide. Finally, let's briefly discuss some layout suggestions. So here's some of our layout suggestions. We typically recommend at least a four-layer board, if possible, with signal ground power and signal being the stack up. We recommend that the RFO paths be symmetrical since the output of the device is differential, so you want to make sure both those signal paths are equal in length. This also goes for the RFI pins as well, although that's a little bit difficult to do based upon the placement of the pins. However, try to keep them as symmetrical as possible. Keep the traces short so the whole output circuit you want to be fairly compact. You want the EMC filter to be as close as possible to the RFO pins, and this is so that you don't radiate high frequencies throughout the board. Typically, I recommend people lay out extra paths for the serial and the parallel capacitor in case you want to do fine-tuning or in case the calculated value turns out to be a non-standard value and you have to put two capacitances in parallel in order to fine-tune the value. And then also something to consider is laying out paths for the automatic antenna tuning, and this is just in case. So when you're prototyping, it's very easy to just go into the GUI and change the values of the capacitor to see the changes on the tuning itself, and it's fairly easy to do. And then if you were not going to use the AET functions for either the 3911B or the 3916, then you could simply change out the device to a device that does not have that function and you just don't populate those capacitors. So here are some examples of layout suggestions that we have. On the left, you can see that we have our EMC filter placed right at the RFO pins. So this goes back to making sure that that EMC filter is very close to there. And then looking to the right, you'll notice that the inductors, these are the EMC inductors here, are placed at 90-degree angles to each other. And the reason we do that is in the past, we've used inductors that are wire wound. And so in order to keep them from acting like a transformer, we separate them. And the easiest way to do this is just to put them at 90 degrees. In addition, you can see that the RFI lines are routed symmetrically, but the distance isn't exactly the same because they're run on the opposite sides of the chip. And then make sure there's no long signal traces between the LC filter and the remaining matching components. So once again, you want to make sure that the output circuit signal path is very, very short. And then also keep vias away from the RFI lines. They should be avoided in the final design if possible. And here are some more examples of layout suggestions. On the left, you can see an example of where we put our decoupling capacitors. So this is layout 101. And you want your capacitors as close to the chip as possible. We typically use a 2.2 microfarad and a 10 nanofarad in parallel at each of these pins. To the right, you see that we've laid out a generous thermal pad with vias. And this is to dissipate the heat in the device. It's very common that you may be dissipating a lot of heat in these devices, especially if you match towards a lower impedance. And so it's very important to keep the device cool and we do this through the ground plane and thermal heat sink. And that concludes this presentation. I'll now take any questions that you may have regarding the presentation or any of our NFC readers.