 Hello and welcome to this presentation of the STM32 Universal Synchronous Asynchronous Receiver Transmitter Interface. It covers the main features of this USART interface, which is widely used for serial communications in embedded systems. The USART is a very flexible serial module that supports asynchronous UART communication, SPI or Serial Peripheral Interface Master Mode, LIN or Local Interconnect Network Mode. It can also interface with ISO, IEC 7816 smart cards and IRDA devices. It also provides certain features that are useful when implementing modbus communications. Applications making use of the USART benefit from the easy and inexpensive connection between devices, which only requires a few pins. In addition, the USART peripheral is functional in low power modes. The USART is a fully programmable serial interface featuring programmable data length, parity, number of stop bits, data order, baud rate generator and configurable oversampling mode by 8 or by 16. You also have the option to use basic RS232 flow control with CTS or Clear to Send and RTS or Request to Send signals. The RS485DE or Driver Enable signal is also supported. The USART supports a dual clock domain allowing wake-up from stop mode and baud rate programming independent of the peripheral clock or PCLK. This allows the peripheral clock to be throttled along with the core clock without disrupting communications. The USART features a multi-processor mode which allows the USART to remain idle when it is not addressed. In addition to full duplex communication, single wire half duplex mode is also supported. The USART also offers many other features including auto baud rate detection, receiver timeout and support several modes which will be described later in the presentation. This is the USART block diagram. The USART clock, FCK, can be selected from several sources. System clock, peripheral clock or APB clock, the high speed internal 16 MHz RC oscillator or the low speed external 32.768 kHz crystal oscillator. NRTS and RX are used for data transmission and reception. NCTS and NRTS are used for RS232 hardware flow control. The Driver Enable or DE which is available on the same IO as NRTS is used in the RS485 mode. The clock output or SCLK is dual on purpose. When the USART is used in synchronous master mode, the clock provided to the slave device is output on the SCLK pin. When the USART is used in smart card mode, the clock provided to the card is output on the SCLK pin. The USART has a flexible clocking scheme. Its clock source can be selected in the RCC and can be either the PCLK or peripheral clock which is the default clock source or the HSI16 LSE or system clock. The registers are accessed through the APB bus and the kernel is clocked with FCK which is independent from the APB clock. The USART receiver implements different user configurable oversampling techniques for data recovery by discriminating between valid incoming data and noise. This allows a trade-off between the maximum communication speed and noise clock inaccuracy immunity. Select oversampling by 8 to achieve higher speed up to FCLK divided by 8 where FCLK is the USART clock source frequency. In this case the maximum receiver tolerance to clock deviation is reduced. Select oversampling by 16 over 8 equals 0 to increase the tolerance of the receiver to clock deviations. In this case the maximum speed is limited to FCLK divided by 16. The maximum baud rate that can be reached is 10 megabaud when the clock source is at 80 MHz and oversampling by 8 is configured. With other clock sources and or higher oversampling ratio the maximum speed is limited. The frame format used in a synchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. The USART supports 7, 8 or 9 bit data lengths. A frame starts with one start bit where the line is driven low for one bit period. This signals the start of a frame and is used for synchronization. The start bit is followed by 7, 8 or 9 data bits. If parity control is enabled the parity bit is transmitted as the last data bit and is included in the data length count. Finally a number of stop bits 0, 1, 1.5 or 2 where the line is driven high end the frame. The standard frame was described in the previous slide. This slide shows an example of 8 bit data frames configured with one stop bit. An idle character is interpreted as an entire frame of ones. The number of ones will include the number of stop bits. A break character is interpreted as receiving zeros for a frame period. At the end of the break frame two stop bits are inserted. The USART supports full duplex communication where TX and RX lines are respectively connected with the other interfaces RX and TX lines. The USART can be configured to follow a single wire half duplex protocol where the TX and RX lines are internally connected. In this communication mode only the TX pin is used for both transmission and reception. The TX pin is always released when no data is transmitted. Thus it acts as a standard IO in idle or reception modes. This means that the IO must be configured so that TX is configured as alternate function open drain with an external pull up. In RS232 communication it is possible to control the serial data flow between two devices by using the NCTS and the NRTS output. These two lines allow the receiver and the transmitter to alert each other of their state. The following figure shows how to connect two devices in this mode. The idea is to prevent dropped bytes or conflicts in case of half duplex communication. Both signals are active low. For serial half duplex communication protocols like RS485 the master needs to generate a direction signal to control the transceiver or physical layer. This signal informs the physical layer if it must act in send or receive mode. In RS485 mode a control line is used. The driver enable pin is used to activate the external transceiver control. DE shares the pin with NRTS. To simplify communication between multiple processors the USART supports a multiprocessor mode. In multiprocessor communication it is desirable that only the intended message recipient should actively receive the message. The devices not being addressed are put into mute mode. The USART can enter or exit from mute mode using one of two methods, idle line detection or address mark detection. The USART can also communicate synchronously. It can operate as an SPI in master mode with programmable clock polarity or CPOL and phase or CPHA. The clock is output on the SCLK pin. No clock pulses are provided during the start and stop bits. The USART can be used in smart card mode based on a half duplex communication. The clock is output to the smart card on the SCLK pin. It supports the T equals zero protocol and provides many features allowing support for T equals one. Both direct and inverse conventions are supported directly by hardware. The USART supports IRDE specifications which is a half duplex communication protocol. The data from and to the USART is represented in an NRZ or non-return to zero format where the signal value is at the same level through the entire bit period. For IRDA the required format is RZI, return to zero inverted where a one is signaled by holding the line low and a zero is signaled by a short high pulse. The SIR transmit encoder modulates the non-return to zero or NRZ transmit bit stream output from USART. The SIR received encoder demodulates the return to zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The USART only supports bit rates up to 115.2 kilobits per second for the SIR end deck. In normal mode the transmitted pulse width is specified as 3 sixteenths of a bit period. The USART receiver is able to detect and automatically configure the BOD rate based on the reception of one character. The received character can be a character starting with a bit at one. In this case the USART measures the duration of the start bit falling edge to rising edge. Any character starting with a 10XX pattern. In this case the USART measures the duration of the start and of the first data bit. The duration is measured from falling edge to falling edge ensuring better accuracy in the case of slow signal slopes. 0X7F character frame. In this case the BOD rate is updated first at the end of the start bit then at the end of bit six. Or a 0X5F character frame. In this case the BOD rate is updated first at the end of the start bit then at the end of the bit and finally at the end of bit six. In parallel another check is performed for each intermediate transition of the RX line. The USART supports a receiver timeout feature. When the USART doesn't receive new data for a programmed amount of time a receiver timeout event is signaled and an interrupt is generated if enabled. The USART receiver timeout counter starts counting from the end of the first stop bit in case of one and 1.5 stop bit configuration. From the end of the second stop bit in case of two stop bit configuration. And from the beginning of the stop bit in case of 0.5 stop bit configuration. The USART is able to wake up the MCU from stop mode when the USART clock source is the HSI 16 or LSE clock. The sources of wake up can be a start bit, address match or any received data. Several events can provide an interrupt. The transmit data register empty flag is set when the transmit data register is empty and ready to be written. The transmit complete flag is set when the data transmission is complete and both data and shift registers are empty. The CTS flag is set when the NCTS input toggles. The received data register not empty flag is set when the received data register contains data ready to be read. The idle line flag is set when an idle line is detected. The character match flag is set when the received data corresponds to the programmed address. The receiver timeout flag is set when there is no activity on the RX line for a programmed duration. The end of block flag is set when a complete block is received. The wake up from stop mode flag is set when the wake up event is verified. The DMA request can be generated when received buffer not empty or transmit buffer empty flags are set. Several error flags can be generated. The overrun error flag is set when an overrun error occurs. The parity error flag is set when a parity error occurs. The framing error flag is set when a framing error occurs. The noise error flag is set when a noise is detected on the received frame. The auto-baud rate error flag is set when the baud rate measurement failed. The USART peripheral is active in run and low power run, sleep and low power sleep modes. The I2C interrupts cause the device to exit sleep or low power sleep modes. The USART is able to wake up the MCU from stop 0 or stop 1 mode when the USART clock is set to HSI 16 or LSE. The MCU can be awakened from stop 0 or stop 1 mode using either a standard RxNE interrupt or a WUF event. In stop 2 the device is not able to perform any communication. In standby and shutdown modes the peripheral is in power down and it must be re-initialized after exiting standby or shutdown mode. The STM32L4 devices embed 5 instances. USART 1, 2 and 3 have a full set of features. Instances 4 and 5 do not support synchronous and smart card modes. This is a list of peripherals related to the USART. Please refer to these peripheral trainings for more information if needed. General purpose, inputs and outputs, reset and clock controller, power controller, interrupts controller and direct memory access controller.