 Hello everyone, so we have been following this particular flow for understanding design compiler so in the last lecture we saw how to define the design manage before that we saw how to write the RTL and how to use that RTL in the design compiler and viewing the libraries are all in place last lecture we focused on the setting of design environment we can prove setting of the operating conditions of input moving conditions output loading conditions and so on. So now that our design is there are operating conditions and environment conditions are defined now we need to set our performance goals so this group of goals is called connected we call design constraint we just try and understand the difference between the design environment and design constraint for example for a let us say a chip has n number of designs which will get synthesized a pretty now each of those designs will probably have the exact same design manager why because each of these blocks is expected to work at the similar range of PVT since they all these block belong to the same chip they will most likely they will have although the input and output loading conditions might differ for each block but operating conditions via load model etc would be same for all those blocks but each of them will have a custom set of design constraints when we look at the design constraints in detail we will see what are the and why will they be different from block to block. So we will focus on the two sets of commands where design rule constraints and design optimization constraint and again so this this lecture would be the end of setting up the block for synthesis in the next one we will look at the different compile strategy and the actual compile command. So now design constraints are majorly of two types first is the design rule constraints design rule constraints are in most of the cases they are implicit constraints and they come from the standard cell logic or whatever cells we are using might not be standard cells might be a max analog macro memory a PLF for example so each of the cell each of the macro whether it be a standard cell or an analog macro we will define this these implicit constraints for itself these constraints are it is must to meet these constraints to make sure that design functions correctly. So any design will that will that uses a library will inherit these constraints and by default they have a higher priority over other optimization. The second group is the optimization constraints these are explicit constraints that means they need to be defined by the user they represent the design goals that is the performance or speed power and areas. So during optimization BQ will try and meet these constraints meet these goals but it will make sure that design rule constraints are met first the higher priority is given to design rule constraints. But let us say you specify some area figures to DC it might not meet area at the cost of violating the design rule constraints it will never try and meet this timing by violating the design rules. So first and foremost design rule constraints should be met then comes the performance thing obviously when we say the since the optimization constraints represent the target area power and speed they should be realistic enough for DC to work on them. This is the graphical representation of the kind of pro charts representing what are the different type of constraints the design rule constraints the most important of them is the maximum that is maximum transition time maximum timeout maximum pattern. We will not look at cell degradation cell degradation is not exactly used by design compiler it will be for some other features of design compiler like I get to use by design compiler proposal of the command tool called DC TOPO but that is outside the scope of our of the course and there is a minimum capacitance command also it is very very used. So we will focus on the maximum for this lecture again optimization constraints are of two types of areas we are not talking about power here I will have some discussion on power but for lecture for the sake of perspective let us forget about power for now let us focus on area and speed. So these are the commands that represent each of the constraint type set max transition set max timeout set max capacitance the area set max area or speed it creates block set input delay set output delay or set max delay let us look at design rule constraints for so design rule constraints are technology specific restriction that the design must need to ensure functionality we saw if we go back in to the library session and try to remember the non-linear delay model we saw that non-linear delay model is represented by a lookup table that lookup table for example for a for a buffer an inverted delay from input to output the delay and the transition at the output will depend on input transition on the output load and these lookup tables upper limit of so the lookup table will have two two indexes input transition and the output load each of these indexes will have a maximum value associated with it that means the designer has put a maximum limit for the transition of input concept and the output capacitance and he has one spice on till that maximum point. If these capacitance and transient go beyond those points then the delay calculation is not deemed to be accurate because it is not accurate then extrapolation is happening the design compiler will go and will try and calculate the delay but it will result into extrapolation and consequently some errors will be given this is why we say that the design rules have to be met to ensure the functionality of the development. If the design rules are not met the timing calculation that the tool does is not reliable. So what happens what does design rule constraints what do they do they will constraint the nets of a design but the commands then only pins so let us say you have a max capacitance limit on the output of the of a cell. So what does that mean is that the capacitance so the output capacitance seen by the grid will have three factors will have three components one is the inherent gate cap itself inherent cap of the output other is the cap represented by the net it dries in the synthesis case it will mostly be a viral model and third is the fan out that is how many gate it dries and the capacitance of all those input so the constraint is on the net but it is associated with the pins of the cell from the logic library. Most of the logic libraries have default design rules you can open up the synopsis go to a particular cell in fact I have showed in one of the module lecture that what is the capacitance of what is the max cap attribute so each of the output pin of each state will have a max cap attribute if the max cap attribute is not there then the tool will take the default max cap attribute from the window. So typical design rules can spend on the transmission times fan outflow is a cap the additional design rules can also be specified these we will not void it these even if it means violating the this delay an area codes we can in fact apply a more restricted constraints but there is more restricted and they limits in the library but less restricted constraints What it means is that the constraints cannot violate the limits design cannot violate the limits that are coming from the logic attribute. We could for some reason apply a more restrictive limit but we cannot relax that much. So we look at the constraint type, maximum condition time is very similar to max cap is the minimum limit, max cap is the maximum limit. So I will not discuss that separately. So let us look at maximum condition time, so maximum condition time for a net is the longest time required for its driving pin to change value values. So since the transition time at the input of a field will determine the delay calculation from input to output there is a maximum limit on it and that comes from the library. DC will attempt to make the transition time of each net less than the max trans value for example by offering the output of the driving pin, max transmission, many times designers apply max transmission limit based on clock frequency so that can also be done. Transition times are calculated from the non-linear to the bottom of the library, these node synthesis does not have accurate information of net that is why it uses the I load model for example. So to change so in most of the cases you would not need to apply this amount max max transmission because the max trans limits are implicitly coming from the library itself but if you want to change those values make them more restrictive then you could use a set max function command. If both the library max trans and the set max trans as the groups are defined for example the library has some value and you apply one more value more restrictive value using set max function DC will try to meet the most restrictive value which with sound quality. So when you start doing synthesis I would recommend not to use the set max function command which is used for very specific cases where you know that you want very good transition on some part of the purpose and part of the design only in that case it is used. Second is maximum fan out, maximum fan out again is a design in the most logic libraries have fan out system from that instance creating implicit fan out constraint. Usually the maximum fan out has two sides, so this constraint is also similar to maximum that if we apply a more specific value using an explicit command then DC will try to meet the most restrictive one and obviously the limit cannot be relaxed. So now the fan out has two parts one is the input part one is the output part see this example. Now the driving pin Z sees, so now it it writes four pins two inverters one output port and one multi input one bit. Now from the library the value 1.0 that is the fan out load comes from the library. So this is the fan out load seen by seen at the input of this inverter. So this is in terms of some integer some numbers. Now please note please go back to the multi input rate schematic and note that as the number of input increase in a year the capacitance increases for each gate input. So a multi input gate will present a greater fan out load compared to a single input gate. So here the inverter DC inverter has one this inverter is also one, but this multi input gate has a fan out load of two. So these values 1 1 and 2 are coming from the library you do not have to worry However on the output on the output port it is not clear since this design this out one is the output port of R design and maybe it is not clear that what kind of load it will drive. So the designer estimated something and sent the fan out load to be 3. This is a command set fan out load which is which belongs to the category of environment condition. So the out one is supposed to be the present the fan out load of 3. Now the max fan out limit on Z by virtue of either will define in the library or using a command of set max fan out is 8. It could be either it could be directly coming from the library but in this example we design a specifically sets the set max fan out to be 8 for the pin Z. Now what DC would do is it will sum up the fan out load presented by the fan out that is 1 plus 1 plus 2 4 plus 3 7 and make sure that the combined fan out load of all the input pins that Z drives is less than the max fan out. So max fan out is given to be 8 the sum is 7 so the constraint is met. Please take some time to understand of example note the difference between the fan out load and the max fan out. Fan out load is the represents the capacitance the load of the input pin which are being driven by the concerned the relevant output pin. On the other hand max fan out is a is a master view is a constraint that is defined on the output pin of a sense. So it is the max capacitance again it is the pin level attribute that defines the maximum total capacitance load that the output pin can try that is the pin cannot connect to a net that has a total cap that is the load cap plus the technical data that is equal to the max cap requirement of the pin. Maximum capacitance design rule it lets us to control the caps of the net directly. The max caps the max fan out and max fan will limit the net the capacitance of the net in directly. So a long net for example will have a bigger cap value plus it will have that transmission also. So it will represent both it will fail both the design rule it might need the max fan out because the let us say the gate at the end of the long net is the infinite input gate and the fan out load would not be much again note that fan out load represents the load represented by the fan out. So let us say there is only one fan out fan out load is less but the net capacitance will have a certain itself is city value it is a big value. So now what will happen is that the output pin of the driving gate will not be able to drive the long wire and thus it will violate both the max cap and the max fan. Max caps will be violated at the output so max cap is at the output so please again I will take the example of the look up table. So the inverted delay for example depends on the input transition at load and that is why there is a max transfer of the input it depends on the output caps cap at the at the output pin that is why max cap is a constraint defined at the output. So it is very similar in behavior to max fan but the cost is based on the total cap of the net instead of transition again DC will try to meet the more descriptive value among the library value of the custom value. So again the important point to note so yeah so important one notice max cap makes sense for the output pin of a gate max fan is the limit imposed on the input pin of a gate you can verify this by opening up the library seeing the total size makes please verify this point that where the max cap at the output is defined where the max fan is at the output is defined. Fan out load represents the load presented by the fan out of the fan the constraint precedence is in this order minimum cap max fan, max fan or max fan although DC will try to meet everything all the design will function before going on to the design code but maximum transition has to sit in for maximum fan out if the max fan out is not met you have to investigate the possibility of a connecting maximum transition culture. So if there is a max fan out DC will not make the transition time worse to fix the maximum fan out for this. So again max fan out has a precedence over max cap what does what does that mean so the output pin of a gate might be related to the max cap but might be valid in the fan out load. So max fan out will take precedence in this case and so idea is that usually the constraints should should be such that these final constraints usually go hand in hand that is usually they just do not conflict with each other and they all should be met but if they are connecting if DC is not able to meet one by fixing the other then these constraints should be revisited you should check that these constraints are defined correctly because that DC is able to meet them. Now let us move on to the optimization constraints. So the optimization constraints represent speed and area design goals power is the third angle but we will not get affected. So these are these are goals for example I set a goal of 1 gigahertz on a custom CPU design now what happens if the goal is not met it might happen that the CPU still runs that so the constraint performance constraint area constraint both of them should be realistic in nature that DC is realistically able to fix those the timing constraints are higher priority that the area will be by area is the lowest priority the priority can be changed but this is whatever I am talking about the difference of priority it is only all the default case any time by using some commands you could change the priorities of the constraints you could tell DC that area is the most important component so make the area lower lower even if the design constraints are valuable DC will do that by default it will not do that without the issues of command. Now the optimization constraints consist of creating input and output delays which are timing constraints minimum and maximum delay which are again timing constraints and maximum area. So what DC will do once it seems the optimization constraint what it will do is it will do something a process which is called timing analysis what is timing analysis. Timing analysis involves two parts first is delay calculation that is the calculation of cell delay that there is are these are also calculated but as they are estimated that is based on value set delays are calculated using the so for in cell DC will know what is the load that is driving what is the so this is a pick up cells from the library and then it will optimize the path so the the timing calculation it will do the timing calculation based on the non-digit delay model in the library for example and then it will break the complete design into a set of timing paths you will see what are timing paths and then it will try for each of those timing paths it will try and see whether the constraint is met. So there are two things there two keywords here one is the timing path other is the constraint so let us see so this is this type of synthesis is called constraint. So constraints are defined in limits of the circuit parameters area power and timing so constraints are the ones used by design compiler for decision making should I pick up a 2 input NAND gate pick up a 3 input NAND gate the decision is driven by the goals the goals we set using these commands so timing parameters are they take priority over design area because the timing constraint for example a hold time constraint must be met in all cases a set of time constraint might not be met but still the design will perform at the lower frequency but hold should be constraint should be met to ensure proper operation. We look at synchronous circuits that correct data must be present at the data input of each flip clock or latch before the clock is arrived under all possible. So let us look at timing paths so for proper constraining design the the tools with PC or in time time or any any synthesis or any timing analysis tool then divide the path into following. So it will start at the input and it will go through combination logic why it will go through combination logic combination logic do not have any any is the output of a combination cell depends on the only the present value of the input input. So whatever is that the inputs logic cell will implement the function and it will show some value at the output but for a sequential cell the output not only one input what was the last input what was the result and that is why a flip clock has a type of a whole time constraint this is the only reason by the tools like DC and PT to start from input and stop at any sequential element this week it starts from input it goes through combination logic it stops at the deep end of the first sequential element type of path are what input is the path again since it stopped here at the because the setup will needs to be kept at the design in the library example that the setup and whole timing constraints are defined at the data pin with respect to the clock pin. So again since the path is broken here it will start again at the two pin of the out of the clock two pin of the clock and again traverse through all the combination logic till it hits the next sequential element be it. So the second type of path is registered to register path again it does that repeatedly till it founds we find the output the third type of path is registered to output path. So the dash arrows in this example they tell us that these are these represent the timing path there could be one more time path here it starts from input goes through combination logic does not find any block and goes through output it is very common this type of path is called completely combination path that is the start point here will be the input pin of a design the endpoint would be the output port I would say I should say port the input port to output port. Now each timing path has a start point and an endpoint start point is the place where data is launched by the clock we are talking about synchronous design. So we will talk in terms of plotting the start point is the place where the tool will launch the data. So what is the start point it could be I discussed this it could be the input port or the Q pin of a sequential element sorry sorry the clock pin of the sequential element because the trigger is the clock. So it could be either the sequential element clock pin or an input port data is propagated through combination path and then captured at another clock in. So now we are talking about setup we are talking about the match timing constraint let us not worry about code synthesis does not do much about code because hold time first of all if you go back to the equations I deal with these equation in much more detail in unit size but we have we have seen these equations earlier the perfect hold equation if you go back to this equation we see that the hold timing equation does not have the clock frequency dependency what it means is that cause hold to meet hold timing the hold the whole time equation equation does not have clock frequency in a in a sequence if the hold timing fails there is nothing we could do the chip fail the design fail. But the hold timing constraints the hold timing paths they depend a lot on the clock free after the physical design is done since design compiler does not have any information about the clock free it does not fix hold unless an intelligent experience will do it. The design compiler the aim of synthesis is to fix the problems issue is to convert RTN into gates such that it needs the performance that is the clock frequency criteria this criteria is represented by the setup time equation. So, setup time is a factor in this equation this is why the timing tool that will be the design compiler or to be will launch it once the data on one edge and expect the data to arrive at another edge at the second edge but still meeting the setup time window of the capture clock. So, each time in part has a start point which can either be input code or the clock pin of the sequential element the data will be launched the next edge the data will be captured at either sequential elements data input pin or the output port. So, when we define the clock so, let us go back to the figure of the timing path let us focus on the register to register path. Now what does DC node we have not specified I indicated we have just read in RTN we have just set the design environment we have not set any design constraints till now. So, what does the DC node DC node the delay of this clock from the library it knows the delay. So, DC is already optimized that is DC is already DC will know the delay of this combination logic. So, DC knows all the cell delays whatever is there in your design. Obviously, the cells will only come up for optimization but assume that you did not provide anything apart from the design constraints we did not define any optimization constraint and went through the synthesis DC will still do the synthesis it will state the synthesis even if it does not know what your goal form it will by default optimize for lowest area. So, the design will be the the resultant design will be very slow it will be area efficient, but since there are no goals in place it is in the level. But what I am trying to say is that DC knows the cell delays from the library it will know the net delays that is the estimated values from the biodegradable. The only thing missing here what DC does not move is the clock situation. So, as soon as we tell DC that is ok the clock which is driving at CLK is of method 200 mega ohm. If we tell DC this all register to register paths are transferred. So, the the equation here is that the clock to Q delay. So, there are three things here the clock to Q delay combination logic delay the sum of these two that the data will be launched at this clock edge it will arrive at D after the delay of a clock plus the combination logic and it should arrive here before the set of time of the next clock edge. Different between the two consecutive clock edges represent the time period of the clock the inverse of which it is the frequency. So, just by defining the frequency of CLK we we constraint all register to register path. So, clock will take constraint on all register to register path things become a bit different for boundary that is at the input port we do not know mostly what kind of data is coming when at what time the data is coming. So, we have a concept of input delay similarly at the output port we do not know what is the capital logic. So, we have a concept of the output delay these two things input delay and output delay in many cases these are estimated value we will see how to estimate these terms. So, for the boundary additional data is required. So, one thing required is clock for the input path the arrival time of the data is unknown for output port the external logic delays are known. In order to analyze the input register and register to output timing external timing conditions must be specified. Input delay is defined as the external delay before input output delay is defined as the delay of the circuitry between output and the next register. Here is known both input and output delay are for the external word they are not for your design because you know input delay and output delay will be estimated values for the external interface. Now, let us see how these values are used to constraint default. So, input delay is now this is the design boundary this is the design boundary clock coming is in a CLP input port is in the path the this part which is this part which is left of input port we do not know much about this. We can assume that this is coming from the same clock it is a valid assumption in most of the cases it is coming from the same clock domain and it takes some amount of time it is mostly driven by a clock it takes some amount of time to reach the input this amount of time this estimated amount of time is called the input delay. How to delay again this is the boundary this is the design boundary output port again this is the part we do not know about. So, we tell DC that we tell a DC by using effect output delay come on we tell the estimate we estimate that the external word will take x amount of time this is called the output delay. Timing budgeting is the is it term which is used to estimate the value of the input delay and the output delays we have to make sure that there is enough margin in our design such that external circuitry can be connected to it properly the timing does not violate. So, how do we do timing how do we budget right that is the question how do we calculate the values of input and output delay. Usually in most of the blocks people will set some guidelines for example, somebody some designer might set a guideline that that input and output delay are both 40 percent of the clock period 40 percent of the clock period means that for example, you have a ten minutes you have 100 mega minutes clock and you say that the input delay is 40 percent that is 4 n m. So, input delay and output delay are always with respect to some clock. So, if we say that the input delay is 40 percent it means that the 40 percent of the clock period of the capture clock is reserved for the external world what does that mean is that the external world will consume the amount equal to the input delay from your clock period. So, in this case the input port at which we applied the input delay of 40 percent to consume 4 n s and remaining 6 n s is left for your design to consume. So, you should make sure that the logic from input port to the first sequential element does not consume more than 6 ns. So, this is the idea. So, now design compiler note that the constraint from input port to the first sequential element is that it should not consume more than 6 ns. This is how the input to register after constraint. I will have a lot of these type of equations in unit pipe that will make things much more clear because static timing analysis is much more extensive than the optimization constraints used by design compiler. So, since design compiler is only focused on performance. So, it needs to know what is the goal again if we say that the output delay is equal to 40 percent for a 10 n s period 10 n s period will amount to 4 n s again the remaining 6 n s is for your clock you can use it inside your clock. So, now let us say we set these to be 40 percent and then after connection to each other if this kept in all this then after connection there will be 20 percent period margin. So, what is the slide determined with that you set a particular value an input delay and output delay for example, 40 percent and then try to keep some margin for this margin will taken to account all the post way out variation consideration limit length limit loading and all. So, saying that the remaining out of the remaining 60 percent you could take again 20 percent as a margin. So, it is just a different way of saying it you could say that you could increase the output delay or input delay many in many designs. So, now see so there are a couple of recommendations of article into that is that into the register of article why is that? So, now we do not know what kind of if we do not know what kind of logic is going to drive the input port of the design. So, for example, this is this is my design and I do not know what kind of how heavy this logic is it is a normal target if we do not know how heavy this is and if we consume more delay between this input port and the clock here then it is going to be determined to connect the excellent heavy design. So, we could we could simply register the input port that means, the combination logic here is almost negligible. So, we consume very less delay from input port to the frequency measurement this will allow us to give majority of the time available to us that is most of the clock period available to us so, it is a move on. I have seen designers who give up to 80 percent of the clock period as input and output delay this is only possible when you register both inputs and output. So, now we we saw how the register to register for path has constraint by defining clock we saw how input to register and register output path has constraint by defining input delay and output delay. Let me just go back and into the commands. So, again we have dedicated lab session lab video meanwhile I would like you to go through the man page and the help of each command. So, I would like to you to focus on these three commands that math function, math command and math capital B although I would not recommend to use these in the initial class of the design these can be used later but it is good to know that it is good to know what they do. So, it will be useful to study in man page and the help of these commands. So, we now we saw that for timing constraints to actually constraint the register to register path the only thing you need to define is the clock. So, the command is called create clock I will go over this create clock in the lab session in the day then just to constraint the input to register path there is a command called to constraint the register to output path there is a command called set output. So, these three commands create clock input delay and set output delay in total they constraint all the three kinds of clock. Now, I also told that there is one more type of path which is the combination path the complete combination path which will go directly from input to output. So, now how do we constraint it? So, one constraint we could say is that set math delay or set mint delay please do not worry about set mint delay for now the command you could use a set max you could tell me that the full combination cloud between input port and the output port of my design should not take more than let us say 5 minutes. So, you could say set max delay 5 minutes from input to output port this will know this will let DC know that I need to optimize this logic to meet this course there is one other technique which is called the technique of virtual clock. So, I will just discuss this technique for now you could choose to study more about it and use it in your synthesis or you could choose to use the set max delay then it will make much of a difference for simplicity. However, virtual clocks are very much useful for timing analysis when we will go to unit 5 we will know one. So, I just this list down the method method. So, in some cases it is necessary to create a clock that is not part of the design, but it is part of the system that is it is let us say now here let us go back to the now let us let us let us take this view. So, now the design my design is a design I am planning to synthesize. Now, let us say the clock here. So, this is the clock port let us say the external word in the external word there is some other clock the price is input it is not the same clock, but this clock is external clock whatever the clock use externally is nowhere using your design the only use it has is that it launches the input data. So, now this is the case where this external clock is not part of our design, but it is part of the system in which our design will see. This is what I say here it is sometimes it is necessary to create a clock it exists in the system, but not in the design. Now the create clock command needs the pin on which the clock should be defined. For example, the clock port of a design is called CLT you say create clock minus period 10 nanoseconds and you tell what port to create the clock on which is CLT, but now if the clock is not actually part of the design there will not be any port associated with it. So, if you give this command without the port design compiler will create a clock and call it a virtual clock that will means it does not have any real source. So, when a source object is not specified a virtual clock will use which does not physically exist in the design. So, the source object represents the place of the clock in the design a source object can be input port or a pin inside the design. So, whenever you create a clock in most of the cases you need to specify whether you are creating a clock as input port or a pin inside the design. If this source is missing then the clock is called a virtual clock, virtual clock obviously has no sources it exists in the memory, but it is not part of the design. You can however define input delays and output delays with respect to this virtual clock. Now set input delay and set output delay command should always be used with some clock it cannot it should not be used it cannot can be used this will not be where it does not make sense. They should always be used in connection with some clock. Now this clock could be a real clock or a virtual clock as the case may be. Since it is not physically present in the design it is not connected to any case of the virtual clock. This is one example the constraint using virtual clock. So, we assume that CLK here is a virtual clock because it does not. So, my design is only combinational nature it does not get any clock pin, but I know that some kind of sequence is also to drive the input and capture the output. So, I assume that there is a virtual clock now let us say the CLK is the period is 10 nanoseconds let us say the period is 10 and I say that the input delay here is less than 2 NS and output delay here is 2 NS with respect to this clock with respect to CLK. Now CLK is a virtual clock again. So, what DC would do? It will start at the timing path the timing path starts at the input port. The timing path will start here DC sends the input delay is 2 DC knows that it will say that the clock is arrived at 0 it will always start at 0 the clock is arrived at 0 and since the input delay is 2 DC will assume the arrival at 2 NS clock is at 0 input comes at 2 whatever delay this combinational object takes for example, let it be anything let us say it takes X. So, data arrives here at 2 plus again output delay of 2 NS means that it is the output world here with the external world here will consume to the total delay 2 plus 2 plus X. Now since 2 plus 2 plus X should meet 10 NS the X should be 10 minus 2 for input delay 2 for output delay. So, this combinational object delay is now constrained to be take a maximum delay of 6 7 again. So, if this is how by using virtual clocks you can constraint the combination path it is very simple we constraint what is the constraint we constraint is that the maximum time is clock period minus input delay minus output delay this is the constraint. Now let us see a bit about clock. So, what what attributes is this is a clock have. So, and so there will be the clock has a period which represents the period is the time between two clock edges to conjugate the clock edges which is the thing with the invert of which is a frequency. A clock will have some amount of function time it will take some a realistic clock ID clock will have a zero function time for zero program, but a real clock will have some function time it will take a common amount of time to write from 0 to BDD. So, it has some function time it has a waveform not all clocks have 50 to 50 cycle 50 percent 50 cycle a clock will might have a 10 percent 50 cycle or 20 percent 50 cycle this basically means it has a waveform. Then latency that is how much time does the clock take from the place where it is actually physically present to reach to your design it is called latency then there is something called uncertainty which tells us that which models the clock detail. Most of the clocks will come from PLL the PLL clock has some detail in it that is even if let us say let us say you say PLL gives the 10 and a second clock the two edges will have some detail so the period will be very close to 10 in most of the cases but not exactly 10. So, uncertainty actually will represent that effect that physical effect. So, at synthesis level the tool will assume IDEL clock what it means that it will not have any uncertainty by default no latency no transition because it does not know anything this is this is why these parameters must be modeled that physical step what it knows and what it should know is the period because that defines the performance parameter and the waveform these two are important things these two are default they will come as part of the create clock command. But other things have to be told using separate command so there is a command called set clock latency which models the clock latency latency the time it takes from clock to be propagated from clock source to the sequential element in the design it has two components source latency and network latency. So, let us say this is the this is the design boundary and we know that at the chip the clock will come out of a PLL so the time it takes here this time either can be estimated or accurately determined depending on what state your chip is in this this time is called the source latency network latency is the delay from the clock definition point to the very specific. So, network latency will be different for each of the clock because of the time it takes for the clock to propagate from the input port will be clock means of the clocks will be different for each clock depending on what it will be in the clock path this is why it is since DC by default will not know these value it is essential to provide these value many in many cases source latency but network latency does. Clock uncertainty is the latest difference between arrival of a clock system at the instant when clock domain or between domains. So, what it tells here that clock at a arrives at some point clock at b arrives after some delay because of delay element here. So, with this difference in delay it is called the skew now this skew will change the way it should work this skew if the capture clock is delayed what it what does it mean if the capture clock is delayed compared to the source clock the launch clock time available is increased since the capital is coming later it should have come at x it is coming later so more time is available for the operation it is good for setup but again on the other hand not good for both. So, clock uncertainty we will see in unit 5 how does we will see a lot more detail in the clock and property. In fact, not even uncertainty but all the parameters the latency is important because of synthesis purpose it is a good practice to apply some value of uncertainty to model the clock creeps effect that will come in the in the course layout plus in modeling the deterioration. So, thing to remember is that uncertainty will have two parameters in synthesis one is the clock tree estimation other is the jitter estimation. So, clock tree estimation so, for example, in particular technology designer might say ok I will keep a plant meter since we have 200 years. So, we applied an uncertainty for all the clock in the design 200 years standard for all the time all the clock in the design. So, there can be different guidelines depending on how your block is how your block is for technology which is in and so on. So, the variation in the generation of clock synthesis as if with respect to nominal times represent the simple uncertainty the variation. So, so this this in fact, there is the pillar on the left hand left hand side it represents the clock tree. So, this type of structure where you have buffers buffer trees it represents the variation in the clock. So, clock is supposed to reach as both these points at the same time the clock edges, but it does not happen obviously there is some difference this difference is due to the clock tree variation. So, the clock tree gets built or there could be the launch and capture block are working on different blocks. So, this is the uncertainty which is coming as a result of the design set there can be two factors to it. The third factor is the transition time the time during which the signal changes from logic load to logic high or from logic high to logic low. The delay as the output in a transition time of the output signal. So, if you do not specify anything the clock transition time would be 0, but this is not realistic you should apply some value that you could apply a 100 base on transition on the blocks. What what does this effect this effect is set up in a hold constraint time calculation if you go back to normally the data model you would see that set up time of the depends on the transition at the plus function at clock the clock transition will change the way DC calculates the value of the set up and holding. So, this was all about clocks you will see a lot more detail in unit 5 about clock that is why I am not discussing all the equations here unit 5 is lot of equations, but for synthesis purpose as far as design constraints are concerned you should worry about the three three commands majorly. So, so design and I will not go I will not summarize we are to anymore we are to here it mostly comes from the library itself. So, for for optimization constraints for area in most of the cases you could say set the set back to be 0. This tells DC that there is no limit to which you can do the area. So, DC will work hardest although it is not very realistic, but many people they will just let us say set back to be a 0 in all the cases which is a good practice I would say for smaller domain. For speed create clock set in for today set output will be the three most important commands that you can do that as far as setting the clock parameters is concerned they are more useful for timing analysis than compared to synthesis. So, once you define the clocks define the input delay, define the output delay all the timing paths are constrained for completely combinational paths you could use virtual clock or you could use set max delay command do not worry much about set wind delay we will talk about it. So, this is four commands will constraint all the timing paths and you could start with the process of tissue in the compile command. We will see how is the compile command is used what are the different synthesis strategy which you could use to synthesize the design in the next lecture. Thank you.