 Hello everyone, in today's lab session we will talk about two things that we have been discussing in the exercise unit course. One thing you will see is we will see about the power, how power is represented. So again we will see the dot lift course, how power is represented inside the dot lift. We will look at the report power command, what numbers are reported, how they are reported. Then we will look at the clock rating, the power compiler clock rating. We will implement a clock rating style, we will see how the Netflix took place, what part of RDL helps you in, what part of RDL does design compiler take into account before clock rating the logic. We will see the clock rating cell types in the lab. So let us first open up a dot lift and see what is inside the dot lift that works for power. So this is the synopsis dot lift, it is open the slow corner one. Now we will just search for power. So now see here, there is a leakage power unit which is one people watch. There is a default leakage power unit, let us not worry about the limit to use. There is a default reliquid power unit which we talked about earlier. Labry features, report power calculation, all these things report delay calculation, more calculation, power calculation. They enable if they are set in the language, any tool that reads this dot lift like DC or CT. It will enable it will help you to find out how the power is calculated. We might see one example which just enables the when the user can see how the power or timing or noise is calculated. There is please note there is no dynamic power unit, dynamic power unit is always calculated from the units of voltage and current, only leakage power unit is given and both of them may be different. Now let us go to a so now similar to the delayed LUT templates there is a power LUT template. So this LUT template is for the delay for example this LUT template vio771, this is the delay, this is used for delay, there is power LUT template. So one of the template tells us that there is only it is a single dimension table, there are variable the only variable represents the input condition time, so there is one other LUT template power output. So one is the power inputs one, so this must be used for input power, so power input will depend on the input condition time, power output here, the table suggests that there are two variables input condition and total output net capital thing. So this must be used for power the output power and now let us look at a cell, so this is the first cell we encounter the I2X1, this is the cell leakage power here, this is a I this is a 90 nanometer average so leakage power is not a big problem here, the leakage power unit is equal what, so yeah the power is the leakage power is not used for a cell, but as the technology goes from here the leakage power keeps on increasing, you can see that if you have an access to the, if you ever have access to the lower technologies like 45 nanometer or 30 nanometer, you can look up the power number, you can compare the power number across the cell, so you will see that as a technology strength because of the leakage power increases. Now also note that the library does not contain a VT value, because the tools the EDA tools they are not concerned about the VT value, they are concerned about the effects of the VT value, so what VT value will do for example reduce VT value will result into a higher leakage power, so that will represent it in the power number, so the tool does not help you with the VT value, you can use this VT by product that is the timing, the power may be right, so this is the cell leakage power, so yeah now see that it also has the state dependent leakage power, so it is an I am 2 cell, so for all 4 states this is which tells us even 0 and A 2 1, this is both A 1, A 2 are 0, both A 1, A 2 are 1, A 1, A 2 are 2, these are 4 states and for each of those the leakage power is different, which is expected because each of these 4 states there will be 2 NMOS, 2 PMOS and plus there will be 1 NMOS, so AND gate is both side, NAND gate plus an inverter and 2 input NAND gate has 2 PMOS, 2 NMOS plus 1 2, they are total 3 NMOS and 3 PMOS right, 6 transistor in total and depending on the state some of them would be OFF or ON depending on each of these states, so the leakage power becomes different because the leakage power, the leakage current is different depending on all these cases, so we see that we notice that these 2 cases when they either both are ON or both are OFF, so this case has the highest leakage power when both are 0, A 1, A 2 are 0, it is 5.6 e to the power 4, I mean 10 to the power 4, when strong figures are even sorry this one looks more like 9.3 into 10 to the power 4, so each of these states has different power and there is one, there is one cell leakage power number also, I guess in this case the cell leakage power number is just the copy of the lowest power value right, this is the lowest power value not the lowest, this is the lowest, so in this case the cell leakage power just matches one of the one of the power numbers among all the postings, so but when DC will use this leakage power number since all the post states are represented, it will use the state, the state the state dependent power, it will I am not sure I am it is most likely that the cell leakage power number which is the default value will not be used by DC right, so however if there is some other tool is also free to leave this totally it might use it, so all the numbers are here the default cell leakage power number is here, all the state dependent leakage power numbers are here. Now let us see, so we so there are again I will repeat there are three types of when there are basically two types of power numbers and the leakage power and the static power number we saw how it is represented, then there is a dynamic power number, the dynamic number is divided into two parts the internal power and the switching power, what total is contained will be the internal power because total is the cell data the internal data, whatever power is consumed during switching during the dynamic activities inside the cell is the internal power, the switching power is calculated from the capacitor 10 component of the wire right, so that will come that synthesis among DC will use the clock frequency for the the formalized 1 by 2 series square f, so DC will use the clock frequency for the switching activity and it will calculate the switching power based on the net net parameters right. So, what what we see in total it will be the static power and the dynamic power internal, so now we see here that in A 1 as a as a table call internal power it uses the power inputs table index 1 as we saw represents the pin transition, so it has two power it has again it is state dependent, so A 1 the power that the consumed by gate then A 1 switches for the case on A 2 is 0, the rise power yeah, so this case is this case here is the internal power then A 1 switches and A 1 rises and A 2 will be 0, this is an A 1 solves, this is the case now this the second table here is actually does not tell the when attribute, so it is the default attribute the rise power and the fall power are the values same yes the values are same, this values are same and for particular case these values are the same. So, if the value if the DC finds the value in the derivative it will take it as 0, now let us look at A 2, A 2 will have a similar internal power table then not of A 1, it could the second table could have been when A 1 when A 1 is, so this table represents when A 1 is 0 table could have represented the value when A 1 is equal to 1, but so you will find that not all dotlets are same in terms of the representation it only depends on the team that is doing the characterization, what kind of characterization is that, what what normally we support put in how many state dependent tables it is, so all of the state dependent data depends on the more you the more data you want the more granularity you want the more simulation you have to run, the more machines it consumes the machine time it consumes, so you need to have a lot of approaches to do a complete accurate analysis, but many times the design the characterization guide will make some adjustments which are valid to reduce this machine time to reduce the complete time, so one of and they will make some trade off, so in some of the dotlets you might find that there is no state dependent internal power there is just one value again cell decay power you might find that there is not just the the default value, now the default value should be the first state of all the state that are possible and so on, so not all the dotlets are same not all characterization are same, it depends on the team that is doing it and how many this will be possible, so output again output will have the internal power now it has, so output power related with A 1 means that whenever A 1 comes in, so whenever there is a transition from A 1 to Y, how much power does it consume as the output rise power fall power again related to A 2 rise power fall power, so every cell in fact will have cell leakage power and internal power of inputs and internal power of inputs, so this is all about dotlets, now while we are on the dotlet let us also see the types of clock grating cells available for it, now before that let us first see the type of clock grating cell that is supported by a dotlet, so let us look at this cell, now this cell is a part description it is rising as latch based integrated cell, the key word here is your latch causes right, so in dotlet a clock grating cell which has the attribute latch causes will have this kind of structure what it means is that there will be a latch of course, again the clock grating without the latch is not a good method because it creates a lot of problems, the timing becomes much more complex as the latch makes sure that the enable here enable at this point, the latch makes sure that enable at this point does not transition, when for example for the AND grating the enable here makes the latch makes sure that, so this latch works on negative edge, this latch makes sure that enable does not problem when clock is on, this is very important, if the latch was not sure not there you would have to do extra timing check, extra checks to make sure that this this is the generated clock here does not glitch does not click, so the latch provides that functionality to you, obviously at the cost of the free data, but whenever you use clock grating in your cell please make sure it has a latch, so the latch causes attribute here tells design compiler that this is the kind of structure that is represented by the cell, obviously there will be a function attribute which will define the function, we will see the dotlet, so this rising edge means that it is used for this blocks that are triggered by the rising edge block, latch is there it has a latch and it is an integrated cell that means in dotlet this is one cell, it pins E n, C L N, B C L N, now we can it can have added functionality for DFT or a scan enable kind of pin, so whenever the scan enable pin is before the latch it is called latch voltage pre-control, the scan enable could be after the latch, so always the scan enable will be ordered with E n which what it means is that, so whenever enable is one the clock the G clock here will not be disabled that means there will be a pre running clock on GCN, whatever is on CLK will be passed on the GCNK whenever enable is one, now enable is a functional signal, it will depend on some functional conditions to be proved right, we will see one example to make this point clear, but in scan mode whenever you have we are doing DFT we want is that all the clock should be pre running that means the respective of the functional condition which would always be one, so this scan enable if the control comes from the top level, whenever we put the lock in scan we make this one and since it is an odd signal it will make sure that whatever is on clock appears on DFT or scan mode, so we do not want this clock to switch off during scan mode, because if let us say functional is not there, if it is the enable condition function is not enabled, we still want that in scan the GCNK should be proven clear, so that is why we give the control, if the control is before the latch it is called pre control, if the control is after the latch it is called post function, so the pre and post control where the odd operation takes place right, now there will be a similar circuit for the switch trigger on the negative, it is called latch negative, again it could have a pre control and a post control, in the positive edge trigger type logic the gating is and in the negative edge kind of logic the gating is odd type, the clock the polarity is inverted if the if the circuit here works on the triggers in the negative the clock, the latch will work on positive it will become transferent on the hyper in the case of positive logic rising logic the latch will become transferent on the clock locals, you can draw waveforms we have already seen one waveform in the exercise you can draw waveform and that indeed this is the functionality that we want, now let us see the daughter, now what I will do is I will search for this keyword latch underscore, so when we see so we see that the first cell it is is tg ln prxt this is the cell and the keyword tells us that it is latch negative we control right, let us look at latch positive we control, if it is there or latch positive it is there, so there is a latch positive and it is a latch positive pre control, let us see what all cells are there latch positive, tg lpp rx2, cg lpp rx8 so the drive is different, there is x2 drive there is an x8 drive and cg lpp sf, this is post control x15, post control x2, post control x4, post control x8, so there are the pre control has two drives, the post control has four drives and also y but this is the how it is in the library, so let us look at the one cell and it will form the bits, you can look at any other cell other other targeting cell and understanding of cell. Important thing do not use this tool, why because this is a very special kind of cell, this is a top gating integrated cell do not use means DC will never use it to infer any logic which is what we want, this is a very special kind of cell, it the functionality does not come from the RTL, this is an extra thing that DC has to save power, although the functionality remains same, the functionality does not change but this circuit is extra, it is not present in the RTL, it is only present in the net list if we choose to add it and DC should not use this cell to infer any other logic any other type of logic that is why do not use it, it is very important, do not touch this tool which is also important because it means that DC will not optimize into something else based on the function, so once the DC will instantiate it, it will in subsequent compile procedure this will not get removed, once it is inserted right, rest of the things are same, the state table is a special case here, so the state table tells here what is the functionality, so it so whenever clock is high for example, the clock e n f e and e n m, e n m is an internal signal, so whenever clock is high see this is the e n m is n v there is no change, so this works only when clock is low, whenever clock is low and either of e n m f e is high, so l h h l h s that means at least one of it is high because it is an odd way, so e n m f e will be odd, e n m will be high right, so why this DC knows that it is an odd time, so e n m f e is odd, again let us see the function attribute, so f e is there are few other attributes, f e is the clock gate test pin which which tells DC that this is for the f e the test pin, there will be the e n pin and it is a clock gate enable pin, so by these attributes DC knows what to connect there, what signal to connect to e n, what signal to connect to s e, then c l k s clock clock gate clock pin then e n m is nothing but the internal pin, internal means that this pin is not visible outside, this is not the port of this pin, if you see the value of e n m will not be present, e n m will not be hooked up when it is instantiated internal pin which is only useful to tell DC what is the representation of this pin, what is the functionality of this pin, otherwise e n m will not come outside of this pin, so that is why internal node is e n m, again g c l k is the clock, clock gate output, state function is what it is clock into e n m, so e n m helps us in making this state function consigned, so e n m we have seen earlier e n m is nothing but the last the output of the latch, before the latch the s e and e n are all together and here the e n m is dated with clock, so if we go back to the figure, so we are looking at this kind of circuit where so this is the e n m pin, this is the e n m pin, so sorry this is the e n m pin after the latch and this is the g c l k and e n m e n m e n m, so it perfectly matches with the the total disk function right, so now when we use the command state clock gate inside, we know that what cells we should use, so for positive edge trigger logic we should use this cell, we should use this cell c g l p p r x 2 or negative edge logic, we should use this country control cell, now we see that there are variance drives available, this is a good thing by because a clock gating cell at one time can have a very large amount of sound, why consider a 16 bit ship register which conforms to the functionality of the type where DC can add such a processor with impact logic perfect circuit for inserting clock gating cell, so DC will insert a clock gating, then one gate but now this one gate will be driving all the clock pins of the 16 bit register, all these blocks of the ship register, so the fan out would be 16, now consider what is there are 32 register in the ship register, again the fan out will be 32, so it is very important for the battery to provide you high drive clock gating cells, low drive clock gating cells actually have no use, why because there is if you remember in clock gating cell come on, there is a bit bit after you that means we want to insert clock gating cells only on register fans which are wider than a minimum bit, the default value of that is 3, so probably you would want to do it 4 or 8 to save on earlier, you want to save power in your host, you do not want to go to do, if you go 2 or 3 then there will be a lot of clock gates inserted with less saving in power, so you have to choose a value which is either 4 or 8 or something like that, something which is not too low and not too high, what that means is that if you choose the value to be 8, each of the clock gate would be driving at least 8 fan out, so it is very important to have multiple drives and higher drives of clock gating cells, the lower drives are of no use, so whenever you have multiple drives available, choose the one that matches your minimum bit fit, for example x8 is available, I would recommend choosing the x4 or not below x4, so this was about the dotlib, now let us go to design compiler and see some power numbers, so I will be using one of the labs and just, I already have the DDC, I will load the DDC where the clock gating is non-inserted and I told you what are the power numbers, how do we report power number, so the design is same, this is the design we are referring to, this is the design that we saw in the last session of the same design I am using, and we will do this again with command prime, but I have already written out DDC to same on time, so invoke decision, DDC, DDC first I will have to set the, anything you have to do, you have to set the third part, the target number, now I will do the DDC, so it loads all the links, now what I will do is, it is already, the design is already synthesized, it is already linked, what I will do is, I will just do a simple report power, you can also check whether the design has clock gating by issue in command for report clock gating, it will do some, it has to update some, but the design does not have any clock gating, so it shows the number of clock gating to be 0, number of gate gates to be 0, number of un-gated gates to be 2 and 4, now let us do a report power, let us where goes, so it will do something called, it will do update power and it gives some warnings that it is another, that it is an un-gated means that it is telling us that there is no switching activity, we have not annotated any switching activity, but we use report numbers, what numbers are going to be, it reports the by load model first, then it reports the global operating voltage, the voltage value comes from the dotlet we have read, so we have read the slope on the dotlet, so voltage value comes from there, now it tells us what are the units, dynamic power units are derived from DC and D units, it is 1 micro watt, VK power unit is 1 V2 watt, it directly comes from the dotlet, now it tells us what is the internal power, internal power is the dynamic power, it comes directly from the dotlet, so combination power is this much, sequential power is this much, so see the sequential power is much much more than the combination power, it means that there are a lot of registers in this, it is to a different area, so yeah the although the non-communist area which is the sequential area is less than the combination area, but the sequential power still is much much higher than the combination power, which is expected because the sequential power works on clock and clock is the signal that has the highest obel con and therefore the sequential elements consume a lot of power, even when a sequential element is not fitting because of the clock fitting is consuming power, so what I will do is yeah, so the internal power is this much, this is the total of combination of sequential power, other power might refer to any memory in macro, there is no memory of macro in this design, so the other power is 0, now it breaks down, so this is the sequential power total, now the next slide is the net switching power, this is the switching power, dynamic power switching, again it is a wire load, the net capacitance is not accurate, it is just an estimate and that is why you have very less net switching power, this power might increase by a lot when this design goes through creation now, so probably in unit 5 when we have placed the router designing for the lab, we will do a report power on that and see if the net switching power is, I probably try to find out a design which is like a pre layout and a post layout code thing design and we will try to see how the power is increasing after post layout, this is the total dynamic power and this is the cell eq power, again cell eq power is just a sum of all the eq power numbers of all the bits in the design, so you can also calculate the eq power by simply adding up the eq power value of all the cells that are using the design, this is how the power number is represented, now a question we did not read any, net power is fine that is independent state, but we did not annotate any switching activity, so what numbers it is taking, so but you can use this command thread switching activity and you can check these numbers, so it is again we talked about to value the static probability and probability, again this you can apply switching activity on per port basis, per cell basis, per pin basis, you could this is it has lot of you can select a clock for a particular signal, you can define the period, you can do a lot of things switching activity, but this is obviously a tedious job, so first of all you need to put some switching activity numbers on all the eq and associate the clock with it, from the inputs you can calculate the switching activity of all the internal eq, now what is still better is to get the vcd, you will get the phase from the vcd file which comes from simulation that is the best way to do it in operating of an integrated switching activity, I do not have any such example where I have simulation data, but you could do that in an assignment, what you could do is from the simulation, you might have an example even or even you can take a small attribute, have some combination and some register in it, take it through a test bench, generate a vcd, generate the phase from vcd and another device, and see how that affects the power supply, but what I have done here is what I will do is I will write out the same, I will do this command, write say, I have already written out the set, and by using minus complicated option, let us see this set, if the command is being write set, you specify the output by name, you specify if you want to see the complicated and you just specify the complicated, now this will let us, this will tell us what values of what toggle counts are used, this is the default set, now see this, direction is backward okay, just write it from the time compiler, if it, I guess if it comes from the vcd file, it is forward, I am not sure about it, version and all, so duration is default, it gives a duration of 1000 milliseconds, now these are the cell inputs, these are the design inputs, now for each of the design inputs, it is assuming that the static probabilities 0.5, that means that any input, every input signal stays in state 1 for half of the time, states 0 for half of the time, problem count is 50, so problem count is 2 percent of the complete simulation time, so this is the default, this is the default number, we can again change the default input, so these are the default, the static probability is 0.5, problem rate is 0.1 okay, problem rate is 0.1, our default problem rate type is for such property, we discussed this in the lecture session, what it means, the problem rate is 0.1, now this will be there, so problem rate of 0.1 means that for five unit time problem, not sure why problem count is 50, appears that problem count is 50 percent of the problem rate by definition, so problem rate, sorry problem count is double that of the problem count is double of problem rate, so it should have the one person would have been 10 times, so the problem rate is 0.1 and 0.1 means, so problem count is half of the by definition is half of the problem rate, problem rate being 0.1, so problem count is problem rate being 0.1, the total number of the problem count is problem rate into the duration divided by 2, so this is the default, so every input has the default value, let us see the clock which is more interesting, yeah the CLK, the problem count is 1000, what it means is that the problem rate is 262, so 2000 2 into 1000 divided by 2000, what it means is that the clock toggles twice per unit of time, in one cycle time, in one period the clock toggles twice which is true, clock goes high and low in one period, that is why the clock the clock toggle count is same as the duration, toggle rate being doubled since the toggle count is the toggle rate into duration by 2, the toggle rate here is 2, 2 into 1000 divided by 2 is 1000, so clock has a very high toggle rate obviously, all other signals have the default toggle rate of 0.1, now these are these are primary inputs right, these are primary inputs and so see even here the reset also has a toggle rate of 0.1, but you do not want that problem, if you want to work with default values please make sure you some signals which will stay static or between toggle 1, you set the appropriate, you can use set switching activity to set appropriate toggle rates, now these are the values which you see in decimal are the internal nodes, these are internal nodes based on the toggle count value and the static probability values of the inputs DC is able to calculate both of them for the internal nodes, so that is why these numbers now remain for each of the internal nodes right. So, it this is the calculation that DC does, so you can see here all internal nodes have some value from toggle count some T 0 and T 1 values, this is all that is contained in there, when you convert from DCB to test the structure would remain same probably you only have the toggle the values for probability and toggle rates for inputs only because the internal nodes DC will calculate from the input right, so this was about power obviously, if you are able to get a good SAIF, your estimation will be good from the 99.5, so we will see this is all about power, we will see the power number probably we will find some more power number and then we will close the data line. Now, let us look at how to insert the clock data, what I am going to do is I will remove the design, I will insert clock dating on a very simple design to show you the what kind of RTA structures that clock dating, let us look at the what RTA I am I will be targeting, so this is just one file this is a validation file I have just downloaded this code, it has inputs CLK load R let us put some input in and out, now the functionality is that if the load is if you give loaded load in the circuit, out will simply get in out the output will simply get the value whatever that the input the register band will get loaded right. So, out is nothing but a band for register I think it is a good register out is simply out would be an output yes out is an output yes. So, the output is a register and these registers will give will load the value of the point if the load is enabled. If the load is not enabled if the load is 0, if you want to write shift based on the shift number it will write shift the input. So, if the shift number is 0 it will it will not shift if the shift number is 1 it will shift by 100 let us shift sorry write shift again this is a similar functionality for this only the shift direction is different. So, now consider a case where load is 0, so it will come to R shift and either you are in R shift mode or L shift mode one of these two modes, but shift number is 0 what it means is that if the shift number is 0 and you are not in the load mode you get out out is simply getting the data out is simply feedback the data is simply fed back into the register with no change this is the condition that presents this fact shift number is 0 you are in R shift mode and not in the load mode again not in the load mode in the left shift mode out gets the feedback value right. So, this is the kind of structure where DC will add block waiting because it sees a feedback or some case it will see that there is a feedback from the output of this register to the input right. Now, let us see what happens when you synthesize it now first of all what let us what we should do it let us let us read this file read file minus. So, this is there are 8 blocks where and so that there are case statements with the equivalent output. So, now I will do a compile a simple compile without the clock waiting compile I will take the options from here and not doing any clock waiting right. So, I am not bothered about constraints right now because I am more concerned on the structure. So, I have applied any block there would not be any time constraints here. So, it will go on very quickly but whenever you are taking this is I do not need to specify some time constraint this is because I am just showing you simply the anxiety of clock waiting I have not applied any. So, this is so, let us note down the area figure about 300.7 and let us do we have the red lock already written out. So, yeah so, I have already written out the red lock to save time let us open this red lock. So, there is a shifter no clock waiting this first. So, this is the shifter these are the 8 registers below the 7 and the clock comes directly no change in the clock all the logic goes on data the output simply comes out of 2 right. So, these are the outputs that come out of 2 data gets all the combination logic let us see data here in 77 gets all this we all these data inputs get all the combination logic and the clock goes directly right this is simple enough. Now, let me enable clock waiting. So, what I will do I will just do a gate lock that is the only thing I can do I will do I am not specify any clock waiting style for now let us see what default value does we will do what does we will do by default right. So, we do this now we see that the area is a bit higher it is 314.5 earlier it was 300.7 obviously I did not clock wait with this area we also see that there is a message called performing clock waiting on the design. So, DC is telling you that it is doing some clock waiting on the design set up what clock waiting it did let us report clock waiting report clock waiting. So, it is telling us that we use a very simple array to express the fact that we should by looking at the simple array we can know the code exactly this is a big design it is not always possible to look that to understand the concept very clearly. So, it inserted one clock waiting element that means, one integrated clock waiting set it inserted number of gate registers 8. So, there total 8 registers all of them are dated. So, total 100 percent of the registers are dated there total number of registers rate we can also do a minus dated and it will tell us what it did actually. So, it inserted a logic clock wait for clock wait outage and these are the gate registers right. We look at the net list let us also issue this command set clock waiting style. Now, if I do set clock waiting style this is telling me about what are the default values it is doing it is using a sequential send apps minimum register bank size should be 3 here in this case it is dated. There is some something called enhanced clock waiting I will not go into this, but minimum bank size is called it is fixed for here or let us not worry about set up the whole time we will worry about it will be 5. It is clock waiting circuitry is and for positive edge negative edge is 4 and again controls signal is control point is expandable observation logic is also there is no observation point. But even if it is 4 values, but now let us see the net list I have already written out the net list point. Now, see what DG did is it added a clock gate for SNPS clock. So, there is one more design there is an extra design now then we would have if you would have not given what on the probably if you would have unroofed this clock gate. So, there is a clock gate which is added and DC is now using integrated clock gating cell from the library. So, even in the default condition DC sees that your library contains integrated clock gating cell ICG and it has a cell that conforms to the default state. What is the default state? The default state was it used hand gating with latch it has a scan level span. So, it used it found exactly same logic in your library and it used that. So, you can first try the default value is targeting a default value if it works for you go to me. If it does not work for you then you need to work with the hand gating cell. I am not going to do set clock gating cell command in this session, but you can try it if you want, but the result should be similar because your library contains the only thing you would play with probably is the insert bandwidth if you want to target that the default it was 3 which I think is good enough. People increase it in time they do not agree with you can increase it with the 4 of it based on water design or through the design or through the area to be on power. But the default clock gating without even playing with the set clock gating cell command is good enough only if your library contains an integrated clock gating cell which every descent natural library should have. So, how this latch is now inserted? Now, this latch is inserted let us look at the SNPS. So, this latch inserted here is the design simply this latch is. So, this latch contains nothing but a latch it simply contains one module hierarchy, but now this clock is an input the CLK is an output here E n clock is the output let us what is the output T e is type 0. So, T e is here type to S e S e is type to T e because there is no scan inserted here. So, it will not do anything to T e in case of scan session this will go to the test mode whatever the scan test mode scan open whatever controls in the top level with code T code or S e here. Now, the important thing here is that all the registers here are 0 to out 7 the clock here now does not come directly does not come from the code, but comes from the output of the clock gating cell. So, let us go to the figure again. So, now the clock is coming from all the registers are getting clock problem from this way right. Now, so this is that the clock goes as input E n goes as input G C S S the output. So, in one of the conditions B C found that one of the conditions it says that the data will be fed back to itself in the register right and that enable condition B C used to generate the clock. So, this is the E n. So, whenever E n is 0 this net 43 which is the related clock the related clock will be off. So, it will save power right C L K here is very easy of the running clock. Now, let us see the logic of E n what is the enable. So, so enable is generated from some combination logic some NAND, but what we know from RDL that enable will be generated when. So, enable will be off when when the clock will be off to the clock should be off only when the data is being fed back to itself. We saw that the condition when data is being fed back to itself is represented by the case where load is 0. That means, it is not loading any value shift num is 0 all the shift num it was the previous one all of them should be 0 plus it can be either in left shift mode or off shift mode. So, if we look at this logic N 68 we see that it is generated from 2 net N 1 24 N 1 23 we see that N 1 24 in fact is the inverted of load. So, when load is 0 N 1 24 would be 1 when N 24 is 1 and N 1 23 is 1 why would be 0 it will not give right. So, if you if you go back and trace that N 1 23 you would see that you would notice that N 1 23 is generated from shift num or shift analysis right. Again N 1 22 here it is a combination logic would be N 1 22 N 1 22 is nothing, but it is again generated from some 2 wires N 80 and N 79 and this is N 80 shift num 2 and shift num 1 right. So, we would you would see it is we go back draw it on paper you would see that the RTS condition what you are talking about that load being 0 and shift num being 0 and you that the draw in L shift or R shift mode. The same condition DC utilizes to generate VM. So, if the condition is true for the case where feedback is available DC will switch off the slope. So, and dynamic power is saved can we see some power numbers here what I will do is I will again remove all the design I will again read this file what I will do is I will again do some file to see without the clock dating. So, area is the method obviously smaller area and I will do a report power report value let us see what it does. So, here the power numbers let us move this power numbers without clock dating and what I will do is now I will do the shop area has hope area is not increase or not I guess this one cell area and I will do a report power. Now, internal power is 15.27 and here the internal power is 15.9. So, the internal power is definitely reduced next switching power now next switching power is 15.25 because number of nodes will be more now because the clock dating is a, but we see that 19.2 the dynamic power has reduced now from 19.6 to 19.6 without dating this is 19.12 with dating. Please note this is a very very small design just 8 registers that is it right. So, we expand it to a very very big design. Now, I have seen in my experience I have seen designs that are very very big which have like 600 K instances or in the million instances instance now they have like 100 K registers out of those these such designs will have dating percentages of up to 80 percent, all the that means, 80 to 90 percent of all registers are there imagine the power saving there this is why it is the most popular power saving technique. It is not it is not even considered as special saving power saving technique it is it is available as part of compile ectra you do a final gate clock that it is done right. So, it is not something very special that you have to do there is not a lot of effort that that goes into it. So, it is by default it is enabled in all the systems as I am saying in R industry in all the companies in most of the companies this minor gate clock is enabled by the company right. So, this this remains the most popular than with power saving technique right. So, what you could do as an assignment I mean pick up a design a bigger design with probably a few more registers and so again see that we saw that in the earlier example we saw that the sequential power was the sequential power was very much it is very significant when compared to power in the design, but because sequential power there is a lot of difficulty involved on the clock right. So, sequential power is very significant because sequential power depends on clock talking clock talking is a lot 291 years. So, the sequential power becomes very much significant when compared to the power and the clock gating in fact addresses the sequential power. So, if you do not do any any gating here we see that in this case the power is the power number that we will know yeah 29 percent and 52 percent in the clock gating case probably the sequential power you can you can do this experiment in assignment what we can do with pick up a design with a significant number of registers give proper constraints do compile and without gating report the power numbers again then do compile and with clock gating then report the power number in verbose mode. So, that you are able to see the difference in the gating power on the sequential side right on the internal power you can see right. So, that will help you in appreciating the power of power component clock gating right. So, that was all so we saw we saw the how to report power we saw the power compiler clock gating we find some time that did not we got it how the power number is represented there what kind of clock gating cells are available we search a clock gating we saw that in fact yes even for a smaller design the power number best get reduced the volume power number we saw the leakage hours. So, we saw a default state what are the default switching up to the DC users if you do not give me power. So, that concludes unit 4 this one more lecture in unit 4, but this is the only lab in unit 4. So, please spend some time in reporting power in experimenting with power number 4. Thank you.