 What we're going to cover now is something called LP BAM, which is Low Power Background Autonomous Mode. So earlier on today, Jeff introduced you to the concept of using GPDMA with something called LinkList. So you can chain functions together and automate much more functionality without having to wake up the MCU or load the MCU in any way. Anders has just been through the various Low Power Modes that are available in U5, showing that we can essentially remove power and clocks from almost the entire device, but have certain peripherals running in some of the very Low Power Modes like Stop 2, for example. So LP BAM is essentially a combination of those two aspects. It's running in a smart run domain, Low Power Domain, and using DMA. But this time, another new aspect of the DMA block, which is Low Power DMA, in a LinkList manner, so you can chain functionality together whilst the rest of the chip is essentially stopped. So we've got a few theory slides to go through. Some of them will be slight repeats of what has come before, so I'll try not to dwell on those and get us onto the hands on as quick as possible. But as I mentioned, LP BAM is a unique power saving way to use DMA to transfer data from peripherals to memory, but not just from peripherals to memory. We can chain functionality together as you saw with GPDMA so that you can read one peripheral and write to another peripheral, for example. And this can be done with the microcontroller and any of the other peripherals completely turned off. So we're saving a lot of power by running the rest of the chip or having the rest of the chip in a stop mode and just utilizing the bits that we need, which is the Low Power DMA and the individual peripherals we need to talk to. So to give you an idea of how that can be used, there's a, have a selection of examples. This one is essentially interfacing to some form of external component like a MEMS sensor that's operating over I squared C or SPI or even a GPS using conventional UART signals. In this example, we use in LP BAM and Low Power DMA to transfer data from the peripheral into memory. And then when the transfer has completed, we can then at that point wake up the rest of the device, wake up the MCU core to process that data. So this is a fairly straightforward example. But we can also use, as you saw earlier on, we can use the ADC and this will be the basis of the LP BAM workshop that we do this afternoon. We will trigger an ADC on a periodic timer and store the data into memory whilst the rest of the device is sleeping. Slightly differently, we can use the DAC in a similar sort of manner. The rest of the chip can be in stop mode. We can periodically write values to the DAC used in sample and hold mode, so it holds its output and this can essentially drive the DAC in a very low power mode. Something else which is a little bit different is there is, as Chris B mentioned earlier, there's the audio digital filter components and this allows us essentially to detect sound and to do some thresholding on signal to noise ratio. So you can set this up such that the microcontroller is essentially stopped, it's off, it's asleep, but we are still triggering on sound activity. So if there's a detected threshold, so detected sound over a certain threshold, we can trigger and wake up the microcontroller core once we've reached that particular signal. You can use the analog comparator components. So in this way, we're trying to show that we can use essentially simple control loop. We can use the analog comparator to vary the pulse width modulation of a low power timer. And again, all of these components you see here are essentially running in the low power domain whilst the MCU is off. We can drive GPIO or read GPIO. So in this way, we could implement some other form of communication protocol, for example, just we can toggle LEDs or we can implement simple UR transmissions, again in the low power domain, again controlled by a linked list DMA channel that's triggered by a timer, a low power timer. We can cascade peripherals together actually as well, which is where the power really comes. So we can, for example, here, we can take periodic samples via the ADC of internal temperature or some external temperature, for example, or voltage. Once those samples have been transferred into memory, they can be then transferred via reconfiguring the DMA block to then transfer from memory to some external device. It could be external SPI flash or it could be an external host controller, for example. So this is a little bit different to the other UCs cases because we're actually cascading together two peripherals rather than just one. So this really kind of shows you the power of this technique. So I think under Slogilis slide before, so I'll be very quick with it, but just to highlight, there are essentially two separate DMA power domains. So we talked this morning about the GP DMA, the General Purpose DMA, that sits in the same power domain as the CPU and the main buses. And we have the low power DMA block, which is in what we call a smart run domain. So this area in pink here is what we would have running in stop two mode, whereas the rest of the device is essentially turned off. So we have the low power DMA controller. It has access to the AHP bus and the APB bus. And the peripherals that link to those two buses can then be accessed and controlled in this smart run domain. Now, peripherals in this smart run domain can actually request their own clock. So they can essentially have the clocks turned off to them to save power. But when it's required, the peripheral can request the clock so that it's able to transfer data and we'll touch on that again in another slide shortly. So this is zooming in a little bit more on the smart run domain. And so we have the LPDM controller here. And this interfaces to, it has interfaces to the AHP bus here and also the APB three bus. So essentially we have two masters, the AHP bus itself and then the LPDMA. And there are two slaves, which is the APB bus interface and the SRAM four. So this morning, when we were storing our link lists, we were storing them in memory into SRAM four. We weren't using any low power modes at that point. So we could have used any memory, frankly, but in LPBAM mode or using this smart run domain, then if we're using stop two, then we have the option of turning all the other, well, we've turned all the other power off to the other Rams, so we store our link list in SRAM four. And as we go through the workshop this afternoon, you'll see that we use SRAM four exclusively because this is the one that's still kept alive in stop two mode. So some quick summary of differences between GPDMA that we use this morning versus LPDMA. In essence, LPDMA is a subset of the GPDMA features. So LPDMA only has one master port, which is the AHB. GPDMA has two, LPDMA only supports single transfers, not bursted transfers. And more importantly, there are only four LPDMA channels. Okay, doesn't have a FIFO and it doesn't support the 2D addressing feature that we touched on this morning. However, this is a peripheral that you can use in the lowest, pretty much the lowest power stop mode. So that's where it's intended to be used. So some of these extra features from GPDMA are not intended to be used in that type of mode. So how are the various bus matrix as distributed across the chip with related to this two specific power domains we've talked about, the CPU domain and the smart run time, smart run domain. So when you are in run mode, obviously you can access the HPB and the APB, no problem. But when you're in LPBAM mode, you can access down to stop one, the AHB and APB. But when you go to the lowest power setting that LPBAM supports, which is stop two, then you really are, as we showed before, limited to APB3 and AAPB4. So this determines which peripherals we can use in this mode, because some of the peripherals are on different buses. We'll see more about that when we go through the configuration tool. But LPBAM brings its most power saving benefits using stop two, although you can use it in the other mode. So that's where it's intended to be used in this mode. So that's where it's intended to be used in this mode. In the other stop modes, but using GPDMA or LPDMA. So this figure is intended to give you an idea of how the LPBAM functionality is an improvement over a traditional interrupt wake-up-based approach. So using LPBAM, the processor here in blue is running at the initial startup. So it configures the link list and it configures the DMA controller, LPDMA controller, and starts, goes into low power mode and starts to transfer. So we have this pink area here, which is the DMA running in the low power stop two mode. And when you're using LPBAM, you are staying within the low power stop two mode. So you get bursts of power, bursts of activity, which is the DMA controller itself and the peripherals. And then only once the transfer is complete does the microcontroller get woken up to act on the transfers. If you don't use this low power background autonomous mode, then you can send the microcontroller to sleep, run a DMA transfer, but then the micro has to wake back up again to do something with it. And so these gray areas here are highlighting the fact that once a standard DMA transfer happens, you then have to wake up the process to go and do something with the transferred data. In terms of clock distribution for this stop two mode, I think Anders probably mentioned, all of the clocks get turned off in stop two mode except for LSI and LSE. And the MSI, KNHS, I16 can be enabled on request by peripheral. So if they need access to the clock, they can request access to either of those two clocks. And this is fundamental in saving power. So what peripherals are supported by this LPBAM mode? Well, there's two types of peripherals. Autonomous peripherals are the ones that can take part in DMA transfers and they can request to have their clock enabled. Passive peripherals are pretty much dumb in that all they can do is generate a trigger to trigger some other DMA process. So perhaps a timer used to trigger an ADC for example. So the ADC is active because it's actually transferring data across, but the timer is passive because it's in this particular instance because it's just just generating a trigger. And this describes, gives the list of peripherals and what type of peripherals they are and where they are functional down to. So you'll see that running in the lowest power mode that supports LPBAM, which is stop two, that you have a subset of peripherals, okay? And you'll see a bit later on when we get onto the hands-on that the tool only offers you the peripherals that are available in that mode. So you shouldn't be able to try and include a peripheral that's not supported. So as we mentioned earlier, there are essentially two clocks that a peripheral requires. There's the peripheral bus clock, which is what is required for the microcontroller to read and write data from the peripheral. And then there's the kernel clock, which is what actually clocks the peripheral itself. So it enables its activity. So those clocks, whether they're turned on or turned off depends on what stop mode or stop state the smart runtime is in. So if we are in the stop state, then the peripheral clock is off, bus clock is off, sorry, but the peripheral kernel clock, that can be off completely or it can be turned on upon request. So if the peripheral wants to actually function, then it can request its clock. In run mode, they're both on basically. Now, if you remember, when we went through Anders workshop, we turned off a debug support in low power mode. And that's important to remember because the debug block itself takes quite a bit of power. So when you're running in low power mode, you're gonna wanna turn that debug block off. But because you've turned the debug block off, it means you don't have access to the internal states of the core. It's very difficult to debug. So to make life a little bit more simple, there are three configurable signals that can be enabled in a debug mode that doesn't rely on the JTAG connection, which will indicate to you the states of the two power domains, so the CPU domain and the smart run domain. So there's three signals, C-sleep, CD-stop and SRDS-stop. And there's a little truth table there to show you how they are active depending on which particular status we're in, basically. So these can be used for some basic debug. And we have a section in the cheat sheet that gives a little bit more detail on this, but we definitely won't get time to go through that as part of the hands-on. But there is information there, so if you want to play with yourself after the workshop, you can do. So this is intended just to recap what we did this morning for the GPDMA section and linked list section because we've done it, I'm not gonna dwell on it. But just to refresh your memory, we can use the DMA block in the linked list mode, which means chaining together individual configuration nodes. So we can have a configuration to handle the DMA block in a certain way. Then we can reload it to point to a different peripheral or a different area of memory. And we store those configurations as nodes and we link them together using a linked list. And when you have it running in circular mode, you essentially loop from the last node back to the first node and Jeff showed you this morning. So, Silicon vendors want to show their customers how low-power their individual devices are, but it's a very difficult thing to quantify. And the marketing departments of various semiconductor manufacturers have great fun trying to say how wonderfully low-power their devices are. So just like there was for the processor performance in terms of drystone MIPS and other type performance measurements, the ULP mark was developed, the ultra low-power mark. And this comes from the embassy or EMNBC organization and they developed this ULP mark to allow a more quantitative discussion about what the low-power features bring in terms of overall low-power performance. So there are different algorithms that are used. There's the core profile, the peripheral profile and then the core mark, which is the overall published figure which gives you a combination of performance. So the core profile is the most basic and simple. The peripheral profile though, this is useful when you have low-power peripherals specifically designed to help with your low-power performance. So here we're talking about our low-power timers, our low-power URs and the low-power DMA, et cetera. So there's a test called the ULP mark peripheral profile that allows us to test those features more specifically. So this peripheral profile or PP for short examines the power consumption or the energy cost of using four common peripherals which is the real-time clock, PWM counter, ADC and SPI. And the benchmark defines 10 activity slots and each one runs for one second. And each activity slot implements a different set of combinations of peripherals and how they are used. Once the MCU has completed its activities, it can put itself into standby or essentially low-power mode. So it's dependent on how long the peripheral is running using these activities versus how long it's asleep. So these are the 10 tests and essentially what happens is you hit reset, the microcontroller starts the specific test and then once it's finished, it puts itself into low-power mode. In our case, this will be stopped to or standby. And the tests have different combinations of peripherals settings. So we've got the ADC, the PWM, SPI and real-time clock. And each slot has a different number of, essentially a different number of configurations. So if you look at slot four, for example, then we take one sample from the ADC at one hertz because there's only one sample. We are clocking the PWM at 32K with a period of 255, 40% duty cycle and 100 pulses. And then we're sending 128 bytes from the SPI controller. Okay, and that's one slot. And for the rest of the time that the micro is not processing that function, it can put itself to sleep. So the PP benchmark as a whole gives you a measure of all of these 10 individual slots. And you'll look at what some of the figures are for a common SDM32 families. We've got the U5 at the top here. And these are the profiles we're interested in. So we have the profile at three volts and then the profiler are usually defined voltage which is 1.8 volts because that's pretty standard for low power. And it's two lots of profile and user profile. When I previously read it, I read that as core profile and peripheral profile but it's not showing up on the slide. Anyway, if we look at the figures are at 3.3 volts rather than 1.8 volts, we can see there's quite a difference basically. In terms of different features, so we're talking today about U5 and we're highlighting low power DMA and this least linked capability. If you're using an older family like L5 for example, then you would need to use it in an interrupted manner. So you run the DMA, interrupt the process, the process, the information, then go back to low power mode again.