 So, welcome to this lecture on VHDL and the course digital system design with PLDs and FPGAs. In the last lecture we have seen structural model of coding in VHDL. Then we looked at the different kinds of simulation and we have taken looked at how at least in timing simulation the simulator try to resolve the concurrency by looking at the sequentially written state concurrent statement. So let us quickly run through the slide before we get into today's lecture. So this is what we have looked at when you have a structural coding which is used for kind of top down design, you have a top level entity with names and the ports this is composed of some interconnection of components. So you need to declare in the architecture declaration region the various components used that basically a name again the input output port and various internal signal and in the statement region we instantiate distinct components as required and interconnect them. So we somehow show a net list that is what we have seen we have taken the same equality comparator as example though in real life you do not need to do, you do not do a structural coding for such a small circuit one statement is enough, one concurrent statement is enough. So here the components are the two input XOR gate and four input AND gate and there are four internal signals. So we are going to declare these two components this signal and in the statement region describe the net list. So that is what is shown here this is a library entity in the architecture declaration region we are declaring the XOR component with its port and for component with the ports for internal signal and the statement region we are forming this net list by instantiating and forming the real formal to actual pin mapping that means I1 is mapped to A3, I2 is mapped to B3 and O1 is mapped to I1 and so on for all the four components and this is called positional association the formal and actuals are associated in a positional way. And ultimately you have to sometimes somebody has to describe the components maybe it is done before it is in a library it is in a different project or it is the same project in a different file and so on. But this shows the component definition the entity for XOR architecture similarly for the AND gate once this is done the structural coding is complete you can simulate it you can synthesize it. And I said about the positional association which is very difficult in a complex case to remember the order of the ports particularly when you put this into a library it is enough if you like normally people say what are the input and output port what are the data types. So a convenient way of associating is to explicitly give the formal to actual mapping. So one need not kind of keep any order you specify what is the formal parameter which is defined in the component and what is actual signal which it is mapped so that is what is shown here. So it is very convenient way of doing it and we have also seen if you properly define the signal you can get a concise code in this case we have defined the internal signal as a vector which allows one to rewrite the earlier instantiation in a kind of very symmetric way. So a3b3 int of 3 comes and then one proceed to write a generate loop which captures this 4 statement okay so for i in 0 to 3 generate and this port map a5, b5, ind5 and this is not a loop in a conventional sense it is literally replicated 4 times okay. So whenever there is symmetry you think of defining the signal properly writing the instantiation properly so that this can work out it is not that you need to write this way and then rewrite this way but then you put it down then you see the trend and you can write it and you can write a kind of ripple order as an example and this can work not only for the component instantiation you can write concurrent statements like if you have a kind of full adder you can write the equation for the full adder and that can be in a generate loop that will be replicated that is possible. And whenever you instantiate a component a particular output is not used you have to say open and do not leave any inputs hanging so unused input should be tied to the appropriate level for the active kind of to make the input active. In the case of AND gate it has to be 1 and OR gate it is 0 and we have looked at different types of simulation I am assuming that you would have done some kind of SPICE simulation in that case this is the system you are simulating you give an input and you get the output in SPICE you have a waveform and being an analog signal it is divided into intervals and for each interval the computation is done and wherever there is more detail is required there will be you know kind of narrow intervals and nothing can be ignored actually the more the interval the better the accuracy of course depends on the system time constants and so on but and also the input signal it depends on both. But in digital scenario you have say two signals like there is no point in dividing the whole range into minute intervals small intervals because you know that a signal changes here then it remains everything remains steady till the next change. So we need to the simulator need to look do the computation only when the signal change and that is called event-reven simulation a new event will trigger the computation event can be on inputs or internal signal within the circuit. And in specific when you have a sequential circuit this is updated every clock cycle so in principle you can do the simulation the computation on the active clock edge which will definitely kind of ignore some details but this is a very fast way of simulating the sequential circuit. And we have also have discussed the notion of simulation time is not the real time is not the time the simulator takes to do the computation it is the time at which the event happens and as I said normally the events are ordered very sequentially. So there was an event at the input at 100 nanosecond 110 nanosecond 120 nanosecond then the simulation start with 100 nanosecond completes it and then moves to the next simulation time and so on ok. And in between for the computation at a particular simulation time might take any duration of time that is not the concern as far as this terminology is concerned but definitely one would like to speed up the simulation so the algorithms are important the CAD algorithm used for simulation is very important. And also you should know that events are ordered in a sequence suppose there was an event at 100 nanosecond and 110 nanosecond the computation of the event at 100 nanosecond changes an internal signal at 102 nanosecond then that event need to be inserted between 101 nanosecond properly. So as the computation happens new event occurs because of the computation that is appropriately ordered properly in the time sequence so that one by one it is handled that is how the simulation proceeds and you can work out you can think of what happens in real time work yourself out and convince yourself and you know grasp that concept. And simulation cycle is basically resolving the concurrency by sequential computation and there is also a terminology called delta delay we will see that. And this is how the last part of the lecture the last class we have looked at a case of a timing simulation and AB is producing an X through an N gate X and C is producing Y through X nor gate. But the issue was that this is written in the opposite direction that the data flow is from here to here and if the simulator handles this from top to bottom Y will get the old value because X is not yet updated and X will get the new value. So it goes from top to bottom and as I said there could be multiple statement in any order. So systematically handling it is that whenever there is an event on a particular signal the simulator looks at the right hand side of the assignment and you can view this as something like a sensitivity list in the process. So if an event happens on a X is computed and X is assigned after say if it is a is at 100 nanosecond X will get an assignment after at 103 nanosecond. So at 100 nanosecond if all the computations are over the simulation time is moved to the next event that is 103 nanosecond. So look for X on the right hand side then X comes here. So the Y is computed and assigned after at 108 nanosecond. Since there is nothing more to compute at 103 the simulation times moved to 108 nanosecond. At that point there is nothing to compute because Y does not come on the right hand side of any assignment everything becomes stable that is how it proceeds. So it proceeds in two steps here and that is what is shown in the table at 0 nanosecond AB was 11 so X was 1, C was 0 so Y was 0 but then A goes to 0 at 103 at 100 nanosecond and that to get a computation which gets an assignment on X at 103 nanosecond a change which towards a computation on Y that assignment happens at 108 nanosecond and that stabilizes the old business okay. So that is how the simulation cycle happens. Now basically it is resolving the concurrency from the concurrent statement it may be in any order it may not match the flow of the data. The solution is event driven computation looks for event at the right hand side and keep computing and if there is a feedback you might ask a question what happens if there is a feedback no issue you keep computing if you are lucky it will be or if the simulator is lucky it will stabilize otherwise it will go on there is no way simulator can do anything suppose you can think of an inverter its output is connected to the input at least in simulation it can be done and it keeps on if you give a delay of 5 nanosecond it will generate a clock of period 10 nanosecond you know but does not wait to synthesize it is kind of oscillator but you can for simulation you can make a clock by you know connecting the inverter output to the inverter input with a certain delay that will generate a clock waveform and we use that for test benches and so on. So let us move on as I said so there could be oscillation but if there is oscillation it keeps happening and simulator does not know whether it is indented or not indented because when you generate a clock it is indented if there is a mistake it is not indented. So simulator has no way to know whether it is the right one or the wrong one so let us move this is the timing simulation but let us come to the today's part which is the logic simulation or functional simulation the circuit is same a, b through an AND gate produces x, x and c produces y through an x or gate ok but you see here and the y is written fast this is written fast x is written later as I said if you give it to synthesis tool absolutely no problem it will generate the circuit because whichever order you write does not matter because you say y, z nor x yes x is a and b so that is created but for simulator the order is not matching and we said there is no issue look at the right hand side and compute no like if there is an event on a at 100 nanosecond look at the right hand side and compute but in this case the earlier case that delay that delay close helped us to keep the sequence like in this case the 100 there was an event on a at 100 then x changed in response to that at 103 nanosecond so and because of change in x the y change at 108 nanosecond so there was this delay allowed us to kind of derive the sequence properly but in this case there is no delay ok. So a changes at 100 nanosecond but x is also changing at 100 nanosecond and if you look at this y is also changing at 100 nanosecond and that you know if you write you are writing the software for the simulator there is an issue because a changes at 100 nanosecond now simulation time is 100 nanosecond then x is changed at 100 nanosecond and simulator come back to 100 nanosecond you know there is an issue ok because everything is at 100 nanosecond. So the trouble here was that there is no delay so the solution is just add a delay ok at least conceptually there are many ways to handle it but like you just add a delay some delta delay and we say there is an event at 100 nanosecond x is assigned at x plus delta delay so now x plus delta is greater than you know sorry 100 plus delta is greater than so event happens on a at 100 nanosecond x is assigned at 100 plus delta now 100 plus delta is greater than 100 and may be less than even the smallest one 101 nanosecond so that is squeezed in between 100 and the next one. So next simulation time will be 100 plus delta so this is computed and then the y is assigned at 100 plus 2 delta ok. So when everything then you look for the right hand side nothing to do it is stabilised at that point delta is made 0 so you get correctly the x and y there is no issue. So you get 0 delay simulation or the logic simulation function simulation by adding an extra delay everything is solved so that is what is shown here. So in the text book you will see a delta delay for some people it is confusing and it is not a big deal it is very simple so if we have at 0 nanosecond a and b are 1 at 100 nanosecond a is changing from 1 to 0 that trigger a computation on x, x is assigned at 100 plus delta so I have not written instead of going to the equation editor I just put the d but it is like it as delta 100 plus delta and x is moving from 1 to 0. So the simulation time moves from 100 plus 100 to 100 plus delta and this is computed which is assigned at 100 plus 2 delta and the simulation time moves to this there is nothing to compute so everything is stable then delta becomes 0 and at 100 nanosecond you get now a waveform which was 1, 1 like the y was 0 then y moved 1 ok and a moves from 1 to 0 everything happens at 100 nanosecond with no delay neatly. So that is what is shown here you know in the picture a is going from 1 to 0 at 100 nanosecond and under plus delta x is going from 1 to 0, under plus 2 delta y is going from 0 to 1 and ultimately delta is made 0 so you can see a goes at 100 nanosecond and y goes from 0 to 1 at the same time. Now there is one thing you have to keep in mind the delta cycle is you know used by the simulator to kind of keep this the proper sequence in computation ok. So you do not have to worry so you just write the statement it is a simulators way of resolving the sequence by adding the delta delay ok. Delta cycle it is not too much relevant in the synthesis when you write a code I have seen students get caught up in this delta cycle ok. Now delta cycle is not a magic by which you can create different behaviour different circuits and so on. So you do not worry too much about the delta cycle and say this assignment happens after the delta cycle so what circuit you get nothing you know you write the statement which we are going to see what the statement means as far as synthesis is concerned you stick to that rule do not worry about how the simulator you know resolve the concurrency by delta cycle because if you get caught it has some implication in the synthesis definitely we will discuss that but is not a I mean when you write a code the last thing you should be worried about should be something about the delta cycle that is for the simulator to resolve the concurrency and it is a concept I mean the simulator need not stick to this to keep track of the sequence basically you have to keep the sequence of computation in the simulation time sequence. So this is one way of resolving it there could be other way of resolving it. So please do not worry when you write a code think about the circuit think about what a concurrent statement mean and that we are going to handle in the coming lectures I will teach you very clearly how each statement means what it means as far as combinational circuit is concerned as far as sequence circuit is concerned. So do not worry this is for understanding how the simulator resolve the concurrency ok. So let us move on so an intelligent student will ask yes what happens when there is a feedback. So let us look at the feedback scenario just for clarity there is nothing new per say but then let us look at it ok. Now maybe there is one question if you before that feedback thing like really suppose you are a CAD tool is trying to implement this delta delay how small should be the this delta delay because ultimately if you are trying to resolve this concurrency by delta delay you have to give some value how small it should be. So definitely it has to be smaller than any gate delay because suppose you are giving a signal is changed at 100 nanosecond and the output of that gate changes at 101 nanosecond and you cannot have a delta delay which is 2 nanosecond because then when you order this the kind of events it will not be proper. So it has to be smaller than any gate delay any delay in the real circuit if you are working with an FPGA which has 100 second as a basic delay the delta delay has to be specified or internally by the simulator smaller than that. Also you are specifying the input signal to the simulator which has some resolution maybe you are specifying that A H changes at 100 nanosecond then 101 nanosecond and so on. The minimal kind of resolution you specify the input is at order of 1 nanosecond then definitely the delta also has to be smaller than that otherwise again when the events are ordered it will ordering won't be proper because delta is 2 nanosecond then which was supposed to come before 101 nanosecond will not happen that has to be smaller than the smallest change in the input signal so that has to be kept in mind. So let us look at the case with the feedback scenario I have shown a very simple circuit cross coupled nan gate please have a look at it. So you have a cross coupled nan latch and as you know that for the nan latch the input is active low okay and when suppose you want to set this then you make it 0 and this 1 this 0 will force the output to be 1 and this 1 and 1 will make this 0 and it comes and reinforces then it can go to the memory mode 11 it will be memory mode if you force both 0 to 11 there is a raise so it is kind of the when it comes back to memory it is undefined so you do not do that so the set is 0 1 reset is 1 0 and the memory is 11 okay. So let us look at this so here we are writing z does r nan y r nan y and y as s nan z so here there is since there is a feedback there is no order you know there is anything everything is messy whether you write y fast or z fast since there is a cross coupling everything is as bad as anything so let us look at it okay. So assume that at time 0 it is in reset the latch is reset that means s is 1 r is 0 because r is active low so y is 0 this is 0 and z is 1 so let us move from reset to set okay. So you know that this was 1 0 now it is moved to 0 1 so both s and r changes at 100 nanosecond okay. Now 2 signals are changing you know so that is good it adds some complexity so but you see on the right hand side s comes here r comes here so simulator has to compute both z and y at 100 nanosecond but you see let us take the z that r is changing at 100 nanosecond z is nothing but r nan y so it is 1 nan 0 okay which is nothing but 1 so z is 1 so at for this 100 nanosecond change z does not change z was already 1 so this makes no effect but if you look at the s nan z s is 0 nan z is 0 nan 1 which is 1 because any 0 is 1 output y was 0 so there is a change in y so the y is assigned at 100 plus delta but now if the simulator has computed both 100 nanosecond events the simulation times move to 100 plus delta so there is an event on y so this need to be computed which is nothing but r nan y so that is nothing but 1 nan 1 which is 0 so z is change from 1 to 0 which is assigned at 100 plus 2 delta. Now since 100 plus delta computation is over move to 100 plus 2 delta z is going from 1 to 0 again y need to be computed so that is nothing but s nan z so 0 nan 0 which is 1 so y was already 1 there is no need to compute everything is stabilized. Now the delta can be made 0 then you get 100 so s goes from 1 to 0 r goes from 0 to 1 and y goes from 0 to 1 and z goes from 1 to 0 so that is shown in the picture this was 1 0 which is going from 1 0 to 0 1 at 100 nanosecond 100 plus delta y goes to 1 100 plus 2 delta z goes to 0 ultimately when you make it 0 the y goes to 0 to 1 z go to 1 to 0 at 100 nanosecond. So it was in kind of reset mode it goes to set mode at the same time so there is no issue actually absolutely no issue whenever there is a feedback two things can happen one is that it stabilizes it converges or it oscillates in either case this has no issue with the feedback. So this kind of delta cycle concept handle the feedback also feedback scenario also that is what is shown here. So solution is to keep computing till everything becomes stable if at all otherwise it goes on and on and on okay. Now so that is what is we have seen now very quick recapture we have seen how the kind of like even driven simulation even driven computation resolve the concurrency in the case of no delay we add a conceptual very small delay delta delay which keep track of the sequence of computation and if there is a feedback there is no issue depending on the events the computation continues two cases it oscillates or it becomes stable okay. So now let us come back to the process and when I mentioned the process I said that to implement a circuit okay. So look at the slide we have this scenario here AB is driving an AND gate AND gate output is X along with CD and XNOR gate drives Y and along with E and F it drives Z to an AND gate okay. Now I said that to write a process for like assume that this is a block to write a process for you put all the internal signal sorry all the input signal in the sensitivity list and we write the statements okay. Now we could have written everything in single statement but to illustrate this idea I have assigned I have written a statement for X like using some if case or something like that or you just write sequential assignment. So X is written as a function of AB essentially A and B Y is function of CDX XNOR you know and Z is a function of E, F and Y. Now you see that we are writing it in the proper order but you look at it if an event happens on A see how the simulator you know we are talking about the simulation there is an event on A which is in the sensitivity list. So the rule is that it goes from top to bottom once okay. Now you know that there is an event on A so this X is computed but X is assigned suppose event happens at 100 nanosecond X get that value at 100 plus delta nanosecond but when it comes to Y the value of X use this that of 100 nanosecond not 100 plus delta nanosecond because the current simulation time is 100 nanosecond. So Y is computed using the old value of X similarly Z is computed using the old value of Y it does not matter you know as I said we have written it in the proper order but you see that X get the correct value Y and Z does not get it at all. Now that means there was an event on X this process has not responded to it so we know how to make a process respond to an event on a particular signal that has to be in the sensitivity list. So the solution is to write X and Y the internal signal in the sensitivity list then what happens in the first time an event happens on A it goes from top to bottom there is a change in X which is assigned at 100 plus delta once it is completed there is nothing more to do at 100 nanosecond. So the simulation time goes to 100 plus delta so if X is specified this is computed again and Y gets updated. Now in the next iteration there is an 100 plus 2 delta even and that if Y is there it will trigger and Z is updated. So the rule is that when you have internal signal you need not write I mean you could write you could think of writing Z as a function of ABCDF directly you know you could also write Z is nothing but A and B X or C and D like the proper bracket you know and E and F you can write as a single statement then you have no internal signal we need not this works but whenever there is an internal signal for proper simulation to happen you have to put internal signal in the sensitivity list of the process that is what I said please keep that in mind. So earlier we stated that you just write the input signal in the sensitivity list that is not enough you have to write the internal signal but I waited for this delta cycle business to be handled then if I state that that will become clear that is why this is handled later. So basically this is what I am stating in response to an event on any of the inputs the process compute from top to bottom even if the order of the statement match the flow of the data all the values used is of the current simulation time this newly assigned value does not affect the computation in the subsequent step. So you have to put them in the sensitivity list that is what is stated here. So the correct usage is that in this case you have to put ABCDF and X and Y in the sensitivity list and then everything works it writes 3 times and everything is updated properly. Now you see that there is a kind of equivalence as for a simulator is concerned the processes and concurrent statement because whenever there is an event on the sensitivity list signals in the sensitivity list the process computer. If you have a concurrent statement in the earlier case whenever there is an event on the right hand side of the assignment this happens. So basically you can think of you take this concurrent statement you can write it as a process with the R and Y in the sensitivity list and you write a sequential assignment. Similarly it is possible that when you have a process you can write multiple concurrent statement equivalent multiple concurrent statement too. So there is an equivalence between the processes and the concurrent statement that is what I want to say. A concurrent statement is equivalent to a process with signal in the right hand side of the concurrent statement in sensitivity list. So you take a concurrent statement you can write equivalent processes like all the this is stating about the sensitivity list in the signal in the sensitivity list even if the order is kind of met and we could like if you have a process you can break into the equivalent concurrent statement and you should remember this fact in real life you may have say 4 processes and 10 concurrent statement everything is concurrent to each other like processes are sequential bodies but all processes or concurrent statements are concurrent if a particular event happens wherever that signal is on the right hand side of assignment and sensitivity list of a process that gets computed at that same simulation time. So that you should remember that processes and concurrent statement are concurrent to each other and depending on the event everything is computed at the same simulation time lot of computation like if an event happens at 100 nanosecond simulator may have to compute some 10 processes and 15 concurrent statement depending on the complexity of the description or complexity of the circuit so that should be kept in mind. So that was about synthesis sorry simulation now let us come to briefly very briefly we will take it later when we discuss concurrent statement. Look at this statement this is what we have written for equality comparator which say that equal get 1 when a is equal to b l0 now you think how this can be synthesized okay. Think of a mechanism by which anything you write any at least for now think of a combination circuit do not worry about the sequential circuit think of a combination do not worry how the what is the VHDL code for a flip flop and so on that we will handle but for a combination circuit you write some statement what is the like a sure way of synthesizing like we have this statement like you come out with a scheme which will work for any statement okay. So let us come back to the slide think for a while you know I will give you a little time just think how you know efficiently how a sure way of synthesizing this please think about it for a moment so I can give a hint like you think of how did you design a combination circuit like in the basic course you know you have some description like somebody say in words this is the scenario and how do you generate how do you design a combination circuit. And you know that from the description verbal description you would have written a truth table so like 100% sure way of synthesizing from a description is to write a truth table. So in this case at least in our case we had two input signal each of which is 4 bit like we have a of 3 to a of 0 b of 3 to b of 0 these are the two inputs equal is a one bit so make a truth table input versus output. So we have a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 this is a input part the equal is the output part and there are so this is 8 bit so you have you can imagine there are 2 raised to 8 rows and we know that when wherever these a pattern and b pattern match we write 1 rest all places it is it is made 0 ok. And then as you know the tool should synthesis tool should make an equation wherever there is pick the min terms and minimize it and so on ok. It looks very nice it works for all the cases but then you can imagine what happens I say that instead of a 3 down to 0 I suppose I say a 15 down to 0 ok. So the moment I say that 15 down to 0 then you have a 15 to a 0 b 15 to b 0 there are 32 values and the number of rows in this truth table will be 2 raised to 32 which is 4 gig and you can imagine if synthesis tool is trying to make such a truth table in the memory and maybe you have a 2 gigabyte physical memory it has to use the virtual memory properly if there is no virtual memory then the system can crash so maybe I am exaggerating but you see that a very simple solution has does not work here it uses lot of memory and so because of a exponential complexity of the digital case where the min terms it goes exponentially complex so most synthesis tools does not build truth tables ok. So it is as you would have guessed when the synthesis tool this see this operator equal operator this operator is written in a proper way to reflect this circuit of XOR gate or XOR gate ok now. So when the internally the operator is implemented using this XOR gate so it is called operator inferencing synthesis tool try to look at the operator and the operators are returned with XOR gate already so that is how it is synthesized. So similarly if somebody write a plus b is not that a truth table of the adder is written and you end up with a carry look adder or something like that the plus is implemented in a simple way as a ripple adder similarly you have you write x plus 1 then this is replaced by an incrementer. So basically the synthesis works on you know the standard structures of the operators like it heavily depends on to you know catch the operator which is used and the equivalent circuit which is written in the library for that particular operator that is how the synthesis works. So that this kind of impossible situation is not reached but at times when the synthesis tool can resort to this and where things can go wrong when it cannot make sense out of what you have written or it cannot guess the correct operator then things can go wrong ok. So that is how the synthesis happened and as we move along when we come to the statements then we will see how it happens. So that is what I talked about the synthesis. So please keep that in mind then we come to this part which is little bit boring but for completion sake I will run through it and the VHDL is very properly defined the syntax is very what to say very precise and we have 4 classes of 4 classes constants, signals, variables and files and you know that in a normal language you have constant variables and files but we have being hardware we have signals which we extensively use and syntax for all classes are you write what is the class then give a name of the object an instance of a class is an object. So name for an object and what is the data type so you might say constant, width, integer and so on ok. So that is the syntax and if you look at the C code maybe this class is not specified in some cases that is implicit in the case of variable but here it is explicitly stated. So let us look at the signal class signals. Signals are basically declared in the architecture declaration region and it can be used everywhere it can be used in architecture, statement region, processors, functions and procedure. The syntax is signal, a name and the data type. So here I write signal, carry, standard logic vector 7 down to 0. Similarly, constant is used for readability and easy modification. So we can define a keyword is constant a name, width and then what is the data type, integer. Since integer can take any value we have to kind of we are saying what is the value here the 8. So wherever the width is used suppose you are defining a counter then you can define the counter output in terms of the width you can say counter output is width minus 1 down to 0 ok. So you can come and change you know it is an 8 bit counter now you just change this to kind of 16 then you get a 16 bit counter. That is the use of it. So the variables cannot be declared in architecture declaration region. It can be declared only in the sequential bodies like process, functions and procedure. And this is used in simulation extensively. It is used for indexing, temporary storage and all that. For synthesis it is not very well defined in non-trivial cases ok. Now this is it is not that you know sometime people say make statement like variables are not synthesizable. It is not true like you take a symbol you know combinational circuit and you try to reply the signal with variable everything works fine. What I mean in the non-trivial case is that suppose you take an algorithm standard algorithm which is written in C code using variable and try to bring that into VHDL and try to implement it you may not get an equivalent circuit which does that business that is meaning of that is what is supposed to be the meaning of when somebody say the variables are not synthesizable ok. Whether the person who says knows or not I do not know but these are a very blanket statement which sometime people make and there is nothing kind of philosophical about it. Essentially that is the meaning you take an algorithm which is specified in terms of the variable and you write that rewrite that in VHDL using the variable and you hope to get a circuit to implement that function you may not get a touch meaning of it. We will see again synthesis using variables as we go along. So the syntax of the variable declaration is variable that is a keyword count and integer is an internally defined integer because integer can take lot of values we are saying range 0 to 255 because our aim is to synthesize a circuit out of this and since this circuit should have a bus of fixed width we have to say what is the range you cannot like when you say 0 to 255 it is an unsigned bus which is an 8 bit bus. So always you have to specify the range of the variable when you specify it so that the synthesis tool can convert this into a bus of fixed width and let us come to the files. Files are used in test pages to store input vector and also to write output vectors. We will see the syntax when we go to the test bench but maybe quickly we will see how that is used. Say normally you define a data type called type some name is a file of character it is a short form of file of character. So wherever you use logic data it says that it is a file with characters inside then the way to use the file is give the keyword file a logical file name or you can say it is a file handler and you say this logic data that means it is a file of character. Then you can say if you want you can say give file this logical name logic data is like in codes some file name this is a physical file name in the current working directory you know that is the meaning of it or you can even say file this file handler the logic data is this data type open read mode is physical name file name that means that you open this file in the read mode only for reading and what is the physical file name you could when you just write the file name in codes it means that it comes from the current working directory. But if you have to go to a specific location you have to give the full path so that is how the file is used and when we discuss the test bench we will see it in detail. So that you know talked about the four classes basically the signals constants variables and files. So let us look at the data type there are two types of data type one is scalar and the second is composite and the scalar you have three types one is enumerated data type and one is integer one is float okay the real numbers the composite you have array this is very useful record which is not as used as array. So scalar and composite scalar you have enumerated and integer and float in composite you have array and record. So let us look at an enumerated data type say normally for state machine state diagram we can use this kind of thing you can say type anytime you say type it is a new data type some name and in the bracket you give the enumeration like you enumerate the states like init, sample, weight, so on these are the states of the state diagram but internally normally when you say this is for convenience internally it takes a value 0, 1, 2, 3 and 4 and there are 5 states so it will be definitely represented in 2, 3 bits okay that you should not forget internally it will be converted to 3 bits and normally the assignment is sequential like 0, 1, 2, 3, 4 for some reason you want to change the assignment to some other order this can be changed using the VHDL attributes okay. We will see that how to do that maybe when we take the state machine coding the VHDL coding of state machine is handled maybe some kind of assignment will solve some issue in the in the state machine implementation. So at that point we will see how to use attribute to change the this particular assignment state assignment. So let us move on maybe discuss this and wind it up so in the enumerated we have already seen the bit and the standard logic Boolean is also there. So this is defined in the standard library so type Boolean is false or true okay. So you could have something defined as Boolean which takes the value false or true you can have the bit is defined as type bit is you know 0 in quotes, 1 in quotes. So the bit takes only 0 and 1 and this is what we have used type standard U logic okay now standard logic is little different from standard U logic. So this is an enumerated type which takes you know open bracket U this is the command, x, 0, 1, z, W, L, H and dash which is don't care okay. So these are the 9 values the standard U logic can take and let us pick up 1 by 1. So U means uninitialized which has no use in synthesis but maybe when you simulate at the beginning of the simulation if a signal is not initialized then it can be shown as U, 0 is the 0 you know 1 is the 1 you know. And similarly L and H are also 0 and 1 but this is forcing this is weak okay. Essentially it means forcing means it has a high current drive so you can imagine an output driven through an NMOS or a PMOS can be thought of as a low resistance drive. So this represents 0 and 1 but for some reason you have a pull up or a pull down then you are driving a signal with a high resistor then this can be treated as weak 0 and 1. And x is when something is unknown suppose you have a line to which 2 outputs through a tri-state gate is connected. Suppose in simulation somehow it happened that both are driving and 1 is driving 0, 1 is driving 1 then the resultant value is x which is unknown so that is 1. So in simulation can show x is unknown then you can kind of figure out what is going wrong and W is when L and H clashes x is when 0 and 1 happens. So W is a weak equivalent of the x and z is you know the high impedance and dash is do not care which is very useful in synthesis for optimisation. So in principle synthesis use 0, 1, L, H, z and do not care simulation can use everything except do not care like if you assign something do not care it does not make sense simulation can be shown up like that but there is no particular meaning in it. But you should know that these are just the values the standard u logic takes but that does not mean if you specify something as L you will get a pull up resistance or something like that you would not get that. So this is just the meaning of the standard u logic and depending on how you write like whether you write L, H or 0 or 1 everything is treated by synthesis tool as 1. And the standard logic we have used is a subtype of standard u logic which is going through a resolution function called resolved. We will see as we go ahead what is that but for the time being you can treat it as exactly same only thing is that whenever there is multiple drive it goes through another function to resolve the resultant value that is the meaning of it we will see later. So I think with this I will wind up for today. So the last part was the data type we have seen the classes for classes the variables, constants, signals and files then data types scalar and the composite in scalar enumerated integer and float and we have seen scalar. So please go through go back and revise refer to the textbook learn it well. So I stop here and thank you and wishing you all the best.