 Hello all welcome to the second chapter of unit 2, in this chapter we will look into detail about the DC response of an inverter, we look at the noise margins which I have been talking about in the last chapter as well, we look at the transient response, the delay estimation and we look a bit into logical effort, the major part of the logical effort will be in the next chapter in the continuing chapter, this is more like the this chapter is very much like the analysis we do for the RC circuit or the usual RC circuits, we calculate the DC response, we can calculate the current response, we look at how does the output current rises and how much time does that take, okay this is the review of the concept we have studied earlier, so just review in your mind and try to answer these questions, what happens when the width of a transistor increases, what happens to the current, will it increase or decrease or will not increase, what happens to the length, if the length is increased, what happens in case of a supply voltage, let us look at each of these answers, so if you remember if you review the equation of the current, the current depends on the W by W, so if the width of the transistor increases, the current will increase, because current is very proportional to W, if the length of the transistor increases, the current will decrease, because it is inversely proportional to length, if the supply voltage increases it is very straight forward, the maximum current will increase, because it will be proportional to V or the square of V of the I for various power and power. Again if the width is increased, the gate cap, the gate cap depends on the area, so both in case of both 4 and 5, if the width increases or the length increases, in both the cases the gate capacitor will increase, if the supply voltage increases, the gate capacitance will be unchanged, because obviously the capacitance does not depend on the voltage, it is characteristic of the perimeter on the area and the commutivity of the base dielectric material, so the capacitance does not depend on the voltage, I hope we remember the equation, we will see the equation in this chapter also. So, for DC response, we see how does V out, so now V out is V out to voltage, V in is V out to voltage, for inverter let us see that, what is DC response? DC response will simply what happens to V out, when V in is either starting 0 or starting 1, it is very simple when V in 0, V out is V dd, if V in is V dd, V out is 0, this is the functionality of an inverter. Interesting part is what happens in between, what happens when V in is switching, how fast or how slow does the V output and what does that switching the speed at which it is between, the most important thing is how fast does V out, how fast the change on V in gets that will also V out, that is called the delay path, that is actually the delay of a gate, the delay of a gates is very very important in determining the performance of the circuit, which we are designing. Now V out depends on obviously the current, the more the current or the better the rise in current, the faster V out will represent will go to V dd or V, it depends on the transistor size, we saw the slide earlier that the current depends on the V by V and two more factors. Now we try to solve this equation, so by the Pistach current law, simple that the IDSN should be equal to IDST, so as we know V out, since both are in the same direction we say that IDSN is equal to IDST, this way we could solve the equation that is we keep the on one side we keep the equation of the for the current of the T MOS, another side we keep the equation of the N MOS, it is not a simple linear equation, but it can be solved, but we look at the graphical solution which is more inside into what happens during the switching. So let us now we should we will try to answer the question as to what regions we saw that in the project stage in MOS and T MOS, they operate in one of the three regions, cut off linear or saturation. So we will see what happens to what regions do the N MOS and T MOS operating during the switching and during the other voltage we try to answer this question. So let us review the three regions which we studied earlier, let us review that once. So what happens when so the three regions are cut off linear and saturated, so the equations governing this if the gate voltage is less than VT the threshold voltage the transfer will be cut off. If for both linear and saturated the gate voltage should be greater than the threshold voltage, but if the if the voltage between drain and source is less than VPS minus VT, then it is in linear mode if it is greater than and it is in saturated mode. Do you remember that the channel gets pinched off near the drain and this pinch off is what causes the current to get saturated. The saturated current for an ideal case does not depend on VDS, but we saw that the actual transistor the physical transistor the current does increase a bit with VDS. The suffix N here just represents the N MOS, this is differentiated from the T MOS. Here the VIN is nothing but the VDSN and VDSN is nothing but VIN. Let us look at what the author has done here is converted the VGSN into VIN, so that the equations are now in terms of VIN and VOUT. Why is that because VIN is common to both T MOS and N MOS similarly VOUT is common. Similarly exactly same equation for for T MOS just the polarities become different, so VDSC should be greater than VTP. Again similar equation we again convert them into into VIN. Now here the difference is that the gate voltage here at VDSC is VIN minus VDD. This is just to make sure that the voltages value remain positive. So we converted the VDSC to be VOUT minus VDD and the GSP to be VIN minus VDD can be the threshold voltage of T MOS is negative. So these are the equations that are converted here. So since as I mentioned that VTP since it is negative value so VIN should be greater than VTP plus VTP. This is you can put in this equation of VDSC where we can put these equations back into this to get this equation corresponding to this equation and this equation. So this is just to make sure that the voltages are in positive range for analysis. We will see how does that affect the graph. So these are the so on the on the axis on the x-axis we have VDD and then the voltage which is the maximum value going to be on the y-axis we plot the I this is the typical IB curve. If you notice that if you take T MOS into isolation this particular quadrant we have seen earlier this quadrant this quadrant we have seen earlier. This is the IB characteristic of a single transistor it is not different than in earlier. We saw that how how this this is the linear region and this is the insaturated region and we saw the dependence on VDS that which increase in VDS the IDSP increases in insaturated with the problem of constant. Now since the voltages and currents are related to P MOS this quadrant here this quadrant is for T MOS. If you take the linear image they both are they are very similar figures. Now we saw earlier that the mobility of electron electron being higher the electrons move faster than the volts. So to make the inverter balanced that that means to make the T MOS carry the same amount of current as N MOS we have to make beta n is equal to beta p. How do we do that? The beta is nothing but mu 1 W mu 1 C of W by L since mu 1 mu n is greater than mu 2 we make W of P MOS wider than the W of N MOS. So P MOS is wider so that we to make sure that beta n is equal to beta p and the currents are equal in both the directions. Now what is done in this slide and so what what happened in this this equation is that we are converting the P MOS voltages to positive value. What we are doing is that we have in terms of graph what we are doing is we are taking this quadrant here and over tapping it with this quadrant here. In other terms we are solving equations by taking this these values this V in V out equations here and the V out V in V out equation for N MOS which is beta p. We are taking these N MOS and P MOS equations for V in and V out and plotting them on the graph and the equation and the graph looks like this after conversion. This is a very very interesting graph which shows how the how the current how the N MOS current and P MOS current vary this input and output input voltages and what happens to V out. So this is this is the output voltage this is the output current IDSN is the N MOS current absolute value of IDSP is dotted here the ID the P MOS current is represented in blue N MOS current is represented in green. Obviously at any particular input voltage IDSN should be equal to IDSP. So for a given V in V plot now V out must be where currents are equal because the currents have to be equal since whatever is being drawn from the V dv again has to go to ground. So the currents are equal it satisfies KCN. So the V out the output voltage can be calculated from this graph at a point where the currents are equal. Now let us see the different points the different voltages and what happens to the current. Let us look at V in 0 very clear V in is 0 let us go back to this the compound what happens. So if V in is 0 this is V in 0 point V in 0 with 0 voltage V in 1 volt V in 2 V in 3 V in 4 and that is it. So this is in this direction the V in is increasing for P MOS N MOS in this direction V in is increasing. So when V in is 0 the output voltage is V dv the P MOS is turned on the N MOS is turned off. So for this graph you do not see any V in line you only see the blue line which is represented by P MOS it is very clear when V in is 0 V out is V dv this. So this is the curve what happens to what happens to the current. So the current I will come to that later let us first see the effect of voltage. Next what happens when V in starts rising when V in starts rising up to the point that it does not cross the V p of N MOS the N MOS is still be turned off it will be cut off and P MOS again P MOS is the one which is driving. So V dv is again V out is again V dv obviously on this line and the transistor that we will see what stage the P MOS is and what stage the N MOS is in. But the one thing is clear that since the voltage does not cross V 2 the N MOS does not start conducting there is a very pained green line here which we will not see in the graph we will see that in the next form what happens when V in is 0.4 V dv. Now the N MOS has started turning on the N MOS has started turning on the P MOS in is in some region the linearization we will see that and the two curves intersect here. So V out will be now slightly less than V dv now see V in is increasing from 0 to V dv V out will start falling which is the inverter from starting again we see that whenever V in is 0.6 V dv. Now we see that the V in is more closer to V dv than it was closer to V s n. So now the N MOS is turned on P MOS is kind of going into turn off so we will see V out which is very close to V dv right. So V out again we remember is the point where both the curves intersect. So in case of if somebody is confused what happens then so in the in this graph the the IDSN is actually 0 flat along the expected. So this is the right point that presents me the second is V dv. So we again again view this V in 0 these V dv is 0 the IDSC graph is represented by the blue line V in starts increasing V dv starts decreasing N MOS starts turning on V MOS starts turning off and at V in is equal to 0.8 V dv and higher the blue line is now also along the expected because V MOS is almost turned off completely and N MOS is driven driving V out. So so V in so for V in 4 V dv is nothing but 0 the same thing happens it is the process completes and V in is equal to V dv. So when V in is equal to V dv again IDSN presents IDSN is this curve and V out is 0 for V in is equal to V dv. Now let us look at so this is again the same graph the load line summary. So at at any point of V in either you could use the equation or you could use the graph the equation is for more accurate analysis we want to know the current value at each and every point the graph is more intuitive into understanding that what happens during the switch switching of the loader. Now earlier the graph walks on ID curve which means it was showing the current with respect to voltage. Now what is plot here is V in versus V out that V in increases what happens to V out. So all the points what what we described earlier 0 0.2 V dv 0.4 V dv 0.6 V dv 0.5 V dv and V dv are plotted on the input line and we see V out here. So now 5 regions are defined A B C D and A so this is a typical inverter functionality assuming assuming this region this region here is very very narrow around V dv by 2. On the left of this region V in is logic level 1 or V dv and sorry V in is for V in is 0 and V out is logic level 1 or V dv and on the right of this this point V in is V dv and V out is 0 which is the red line typical inverter functionality. Now let us revisit the regions. So in region A region A V in is 0 or close to 0 what happens to NMOS and PMOS. The NMOS is in cutoff PMOS is in linear very important thing to remember is that in in in static state the whenever pull down or the NMOS is in cutoff the PMOS corresponding PMOS will be in linear region region A region V the reverse PMOS is in cutoff in linear NMOS. So either NMOS or PMOS during the switching will go from cutoff to saturation to linear why this happens. Now the train voltage is constant here what is what is changing is the gate voltage the input voltage. So when input voltage the gate voltage is low the train voltage being higher pushes the transistor into the saturation and when the gate input gate input keeps in linear the transistor comes out of the pinch off either and goes into linear. The thing to remember here is that at at the the logic levels of V in being 0 and 1 V P either the PMOS or NMOS one of them is in linear other other one is in the cutoff. Now what we will do is we will play on this curve we will play on this curve we will play on how this curve is useful in understanding the noise margin and understanding the delay and so on. Now this curve this curve can be skewed by making by playing with the beta P versus the time value if it is not equal to 1. Now in the in the previous slide we saw that the switching point is very closely available this this is the switching point and this the voltage the shifting voltage is almost instantaneously here this is for the case where beta n is equal to beta P that means we are made PMOS wider compared to NMOS to make the current equal. But if it this is not the case this curve the middle curve is for beta 1 if we start increasing beta P by beta n that means we start making PMOS wider then this gate becomes skewed in the sense that the cutoff point starts moving away from VGD by 2. If beta P is the PMOS is wider then V out obviously V out it will be difficult to it will take more time into or rather it will take more voltage to make convert PMOS into from a region of fully on or a linear to saturation to cutoff. So, let us consider this curve this curve now this case is the case of beta P by beta n is 10 that means PMOS is very very is compared compared to NMOS is quite wider 10 times as wide the PMOS will remain the for a higher very this net flips if you down the for a majority for a major part of the beam to VGD ratio the PMOS will remain in linear region that is on and NMOS will remain in cutoff for this major part of the curve. So, the minor part obviously the NMOS will become similarly this is the case similarly this is the case where NMOS is quite this is again 10 times as wider as PMOS and so this case is the reverse of this case where for the major part of the curve this is the major part of the curve the NMOS will be turned on and PMOS will be turned on. So, we see that by playing with the beta values or the width of the transistor we can control the time it takes. So, let us see we will be looking to the time parameter, but we can control the this queue the the slew of this this and these gates which are not balanced that is for beta after beta this is the curve this kind of gate is not a balanced gate it is called a skewed gate. How do we analyze other gates other complex gates we do the similar kind of exercises and they these gates also get collapsed into an equivalent inverter. So, when we talk about the skew factor in terms of other gates or the how wide is the NMOS and NMOS should be always compare it with an equivalent unit inverter. I will come to watch what unit inverter is later we will discuss something about unit inverter earlier, but we will see that again. Now, let us talk about noise margins noise margin why is it important for any gate we have to make sure that a small amount of noise should not corrupt the value at the output of the gate. Now, let us let us study two inverters that are connected back to back. So, let us say the the inverter the first inverter. So, the idle voltage VDD and GND these are the idle voltage VDD and GND. Now, let us say the output of the first inverter voltage here is let us say slightly lower than VDD we call this as VOH in case the the value here is low multiple low then it is not actually GND it is somewhere higher than GND let us call it VOH. What it means is that we are introducing some noise here which is eating into the logic level if the let us say if the input input here let us say it goes high the output here goes low, but it does not go low as well as GND it goes only to VOH. If the input here goes low goes low then the output does not necessarily go to VDD it goes to somewhere VOH. Now, let us say we we define two more terms called VIH and VIH what it means is that the inverter here for this inverter to recognize for this inverter the second inverter to recognize this value as one it is sufficient that it should be between VIH and VDD. I will explain that in detail I will explain more in detail, but let us assume that this inverter is given a voltage between VIH and VDD it is able to resolve as logic level one. Similarly, if we give a voltage between DIN and GND it is able to recognize this as logic level 0. So, we say that the logical high input range of this inverter is this one is this one similarly logical low input range is this one. So, for the second inverter the noise margin margin it has the lowest the input can go is VIH, but actually it is going up to VOH. So, the margin it still has for high region is NMH which is the difference between VOH and VIH. Similarly, you open the margin on the lower end is NML it is the difference between VOH and VIH. Now, let us look at logical high input range. In the previous slide we saw this curve now consider consider an input value the VIN to be somewhere here somewhere here right. Now, we see that for this range let us say with two point we need to be for this range of VIN that means, VIN can be higher than VOH and still the inverter will produce an output of VIN this is called the range that means, the inverter is able to take some noise into account. Now, inverter is a digital circuit it operates in either 0 and 1, but this 0 does not mean it always has to be VVD it is always has to be GND it can be some voltage above GND and still the inverter will maximize this as logic level 0. Same thing happens for logic level 1 this range decides the logical high input range and logical low input range ok. Now, the gates should obviously be designed to withstand large levels of noise. So, how to maximize noise margin? Let us say for example, in this case beta p is greater than beta n greater than 1 this is the energy inverter and the the curve slopes here this is these are the two points these are the two points where the curve this the slope is minus 1 right is it is 135 degree slope is there on this on this curve on this on this tangent this will be draw a tangent and we say we define these parameters here VOH is this and this is VIN again VON. So, remember the x axis is being input voltage the y axis is output voltage. So, what we are defining here is that we say that at these slow points the output changes from VVD and immediately goes into a very sharp region this is a very sharp transient region. So, we do not want to go into this we want to restrict the R cell to this this this particular region to this particular region for input voltage 0. The voltage here we define as VOH corresponding input voltage this is this is the output voltage corresponding to this slope this is the output voltage this is the input voltage. So, we call this VOH and VIN obviously when O high because this is closer to VTD I low because the input is closer to this. So, for this input range VIN similarly we have a similar slope here this is VOL and VIN. So, at these two slow points if we design the inverter these level logic levels for a unity gain point it will have the maximum noise margin possible again why is noise margin important noise margin important to make sure that small disturbances in voltages do not cause wrong logic levels. I request all of you to go through this this curve actually the best thing would be to make a unity gain inverter plot the DC transfer characteristics of a inverter which has beta P adjusted. So, that it is equal to beta N or no beta N actually twice of that or let us say 1.7 times of that to make sure the currents are equal you draw this graph this graph is very easy to draw easy to plot we just give VIN and change VIN and calculate V out the spice will do that for you and then you could actually calculate the values of VOH and VOL and VIN and VIN and that would give much more insight into the working of the inverter and the problem also. So, DC analysis told us what happens to V out of VIN as constant the transient analysis is very important that will tell us what happens when VIN changes how fast that how slow that V out thing go back to the RC circuits the RC of the RL circuit is nothing but a first order differential equation. Similarly, we would have a differential equation here input is usually considered to be a step or a ramp a step input is ideal case a ramp input is the most more practical case from 0 to VDD or vice versa. Let us see this inverter here now it is important to we will we look at IDSN V out will see some load which will be represented by P load capacitor load this load is just the drain cap of both load or it could also represent the final load of let us say an inverter or any gate that we saw this earlier during RC model, but whatever load is on V out is represented by C load. So, V in we are we are looking to find the step response when we talk about step response V in will change from V in can be represented by U T minus T 0 VDD U is nothing but the step response input that means, U will rise V in will rise at T 0 it will become 1 before T before time is equal to T 0 it will remain at 0 V out is less than T 0 if V in is 0 V out will be 1 or VDD V out by DT let us look at the equation. So, D V out by DT D V out by DT is nothing but is negative of IDSN by load by C load. So, if the formula is simply I is equal to VDD by DT. So, the V we solve for ID. So, what happens when T is less than T 0 V be look for 3 regions here T is less than T 0 V out is greater than VDD minus V 2 and V out is it is less than VDD minus V 2. So, for T is less than T 0 obviously, V out is VDD it is connected to the pull up network not to pull down network. So, the current will be V 2 and possibly 0 again we look at these 3 now V out is nothing but VD we look at 3 regions here V out and input is nothing but VDD with the gate voltage this. So, this is nothing but this is VD this is VG. So, if VD is greater than VG minus VG these you can write. So, this part is nothing but this is VG and this part is nothing but VD just the arranged. So, VD is greater than VG minus V 2 it is a saturation you remember the saturation equation again this is in the linear region this part we remember the equation of the linear part this is solving for this is the ID values. Now, we have to solve for V out knowing the ID values we could easily plug in the value of ID essence here and calculate the V out this graph here shows what happens to V out V out when V in changes suddenly obviously, V out will go to 0 after some time this is the pull pull down network is being acted now, but VV we are looking to to find the equation for this curve. So, here we will define some some parameters for delay PPD means propagation delay R means rise S means fall TR means how much time it takes this first signal to rise PF means how much time it takes for the signal to fall. PPDR rising propagation delay that means from input to output rising crossing VVV by 2 the rise here the rising here is referring to the rising output for any gate this can be for any gate for an inverter a rising output could be in a falling input or let us say a buffer a rising output would be in a so a rising input. So, PDR is rising propagation delay from input to rising output PPDF is falling propagation delay from input to falling output PPD is nothing, but average of both TR is some output crossing 0.2 VDD to 0.8 VDD this is the transition time for the output this is a 20 80 percent limit. So, 0.2 VDD to 0.8 VDD again all time is from 0.8 VDD to 0.2 VDD these things are arbitrary for a particular technology for a particular design somebody might decide to use the 1090 percent for 0.1 to 0.9 and so on. So, these are the definitions for let us say R for one particular technology for one particular application these can be changed as the as the purpose. Now, PCDR is rising contamination delay from input to rising output causing VDD to VDD by 2 PCDF is the falling contamination delay I will come to what is this contamination delay this contamination delay for example is not applicable for inverter it is only applicable for complexity. So, this is a this is a spice simulation of an inverter I would recommend all of you to do this yourself using a spice tool. Obviously spice will not use your simple chocolate first order model not a simple alpha model it will use a much more complex and accurate IV model. Obviously simulations are not that easy to write but once you are familiar with you can write basic simulation at least you can write you can write a you can simulate as a response or you can even simulate a step response in steps of 20 percent of VDD you can do that easily. So, this is a graph of a spice simulation where the where the time is plotted here. So, we see that the curve here this V in is rising this is nothing but V in and so obviously when when V in is low this part of V in low VDD is high when V is high the VDD is low. So, according to the definition of the propagation delay the time the time here and the time here the difference in time is the propagation delay for fall that means V out is falling similarly this is the propagation delay when V out is falling. So, I will also show you what is the rise time and the fall time. So, so the propagation delay refers to the difference in time between the output and the input when output is falling or output is writing. If you consider the VDD alone to the time it takes from this point let us say 20 percent of VDD to go to this point let us say 80 percent of VDD this difference here this difference here this is nothing but the rise time similarly this difference here is the fall time. So, these two and request you all to again again go through this to revise this such that these concepts are very clear of the propagation delay and the rise and fall time these are very very important factors in determining the quality of the design. Now, we realize that solving equations or doing five every time is not straightforward thing it is not very easy for every game. So, how do we quickly compare different designs or delay? We saw one thing earlier we saw an Archive delay model earlier which is used to estimate delay on paper it is a very good tool. So, the point here says that we will use Archive delay model very useful technique propagation delay is proportional to Archive. We also characterize transistor by finding the effective R. So, the effective R depends on the average current that we take with it. Let us look at Archive delay model again. So, we talked about a unit NMOS transistor and unit NMOS transistor we say that the rule of thumb says that the unit TMOS has a resistance of 2 R is the mobility of poles with solar compared to electron. Capacitance is the same we define the capacitance to be C of each gate, drain and hose. The capacitance is proportional to bit we represent bit by K the resistance is inversely proportional to bit. So, an NMOS of bit K will local something like this you have capacitance KC at each of the three terminals and you have the on resistance to be R by K. Similarly, PMOS will become 2 R by K with the capacitance will remain KC. Let us again give an example of this. Let us see a three input NAND and how do we make sure that it achieve the effective Ryzen for the resistance equal to unit inverter R. So, now what I will do is let us look at the RC model of a three input NAND and try to see how does it compare to unit inverter. Now first thing what we have to do is we have to assign with all these NMOS and PMOSes. Now how do we do that? I will annotate some numbers here and I will try to justify these numbers and justify these numbers by the bit position as 3 3 3 and 2 2 2 and then this technique can be applied to any CMOS a static CMOS gate and bits can be calculated. So, let us see a unit inverter. So, a unit inverter nothing but a PMOS and an NMOS connected in series this is the PMOS here and NMOS here they are connected here. So, the width is 2 and 1. So, if you remember that this unit NMOS here will have the resistance of R the unit PMOS here will also have a resistance of R why because the width is 2. So, if it is 1 here the resistance will be 2 R if it is 2 here the resistance will be R. If it is we go back to the previous slide we see that the so, the if the width is 1. So, NMOS will have R by 2 and if width is for corresponding same PMOS it will have a 2 R. So, by making yeah by making the PMOS to be twice as wide we keep the resistance to be R same now same thing same we will apply here. Now, if you see let us say if you combine 3 NMOS in series these are 3 NMOS in series forget the number 3 here forget the width if let us say each of them was unit. So, the resistance total resistance would be 3 R. Now, if we make each of these transistors wider 3 times wider what happens to the resistance. So, the resistance of each of these become R by 3 which is R by 3 R by 3 R by 3. So, the total resistance seen by the pull down is nothing, but R. Now, compare the resistance by a pull down circuit here is R resistance of a unit inverter is R. Now, we come back here these are parallel PMOS is in parallel, but this is a NAND gate at any given time we assume that only one PMOS would be on other two PMOS would be off it is parallel. So, we assume that only one is on at one time if one is on the resistance of a of a PMOS a single PMOS resistance on the system which is equivalent to the single PMOS resistance of an inverter. So, it should also be R. So, PMOS is nothing, but twice a time. Now, what I would request is that go back and draw a 3 input NOR gate for example, or any gate and try to calculate the width of NMOS and PMOS using the same logic and comparing it with a unit delay inverter. I repeat again the process you go to the the pull down and the total pull down resistance should be R if it is in series the resistance is added and you will have to make the NMOS as wider to make it R then go to the pull up and compare the pull up to the unit resistance pull up if it is in parallel you assume that only one of the PMOS would be active and calculate of it. So, for series you will have to make the PMOS a wider for parallel you might have to make it less wide or depending on how the parallel circuit looks then. So, do this for one complex gate and and compare the widths. Now, we we have we saw the widths of all the PMOS and NMOS now let us annotate the capacitance and resistance over it right. We will convert this to this looks very much, but not that in reality just. So, a width of 3V means 3C at each of the gate inputs 3C cap at each of the gate inputs 3C cap at each drain and each source then again this the PMOS is 2C. So, this the gate cap now see for NMOS the cap will be with respect to ground or PMOS the cap will be with respect to VDD. So, 2C 2C again 2C these are parallel connections please note these are parallel connections the 2C 2C each will have a 2C cap with respect to VDD. Now, let us check out one thing 2C here the gate 2C 2C yeah 2C ok. Now, if you are we are wondering this is this is 3C this is just because it shares the contact. So, we it is because it is not contacted. So, we account only 3C per one of the transistor because because it shares the difficulty there is no contact there as we saw in the layout. Now, we combine this we what we do is we use the so for example, the 2C with this 3C and this 2C is combined to make it a 5C because VDD when 2C then 3C this 2C and 3C are in parallel then add up to become 5C. So, each gate will see 5C and similarly we combine the the grain and source and wherever it can be combined. So, each gate will see 5C let us go back and check the output. So, the output here this this point sees a 3C a 3C 3 plus 2 7 plus 2 yeah 3 plus 2 5 plus 2 7 plus 2 9. So, the output will see 9C right similarly this point will see 3C this point will see 3C and so on. Now, let us see the delay part. So, we have the value of R we have the value of C. Now, this is again an exercise a little into sizing. So, before calculating the delay the first thing we should do is determine the width of the transistors. Second thing we annotate the C values there to calculate the capacitance seen by the output because the right the delay at the output determines on the output capacitance and resistance right. So, this exercise we will try to size this so that this becomes equivalent to unit inverter right. Now, here D is in parallel. So, these two are parallel connections. So, we assume we make sure that D has the same R as the n MOS of a unit inverter. So, that means, the width here will be 1 for example, if the width here is 1 then again these these two are in series. So, there will be twice as wide. So, let us I will put the values here and we just put the width of these one. Next this should be 2 and this should be combined this should be combined this this is by width 1 means this means R this should see R by 2 and this here should see R by 2. So, the width here is 2 again you have parallel. So, V and C would need to be still more wider draw the same current this unit up a bit yeah ok. Since this is this part is parallel yeah. So, this this D is parallel to this circuit we assume only one of them will switch on. So, each one of the branches should have resistance R. So, this does not is width here is 1 again this part in total should be again V and C are parallel. So, we assume that either of them will be turned on. So, when A to B is turned on you see 2 and 2 that is R by 2 the side by 2 again R or if AC path is turned on you see R by 2 and R by 2 again R. So, 1 2 2 and 2 similarly for pull up we see that D is in series now to A, B and C again we I will put in the numbers here. So, when D is in series let us put in number let us come to A, B and C yes when B C in series now usually the PMOS is twice as wide. Now, we assume that either that is a this will work this part will be active either this will be active or this will be active it is 1 and this will be 2. So, when 1 is active B and A being in series PMOS anyway shows that a 2 R you release 2 wide it is twice as wide. If you add 1 more PMOS it should be 4 times as wide. So, that the resistance shown here will be 2 R by this is 2 R nothing, but 2 R by 4 this is A is 2 R by 4 D is also 2 R by 4 or R by 2 when you combine 2 R by 2 together it shows that again B and C here in series. So, this should be again twice as wide as A because the resistance here is again 2 R by 8. So, R by 4 and R by 4 that is R by 2. So, this becomes R. So, this way we decide the weights of each of the parameters I will request all of you to do this exercise on paper on yourself or you can draw any complex circuit and try and do the sizing. The purpose of this sizing is to make sure that the resistance of the pull down in the pull up network is same and it is equivalent to a unit inverter. Now, we define a term for L mode delay. L mode delay assumes that on transistors looks like a resistor the pull up and pull down network are modeled at the R C ladder what we have been doing and the L mode delay of R C ladder is the propagation delay is let us say you have a network like this the submission of R I to source and C I across all the nodes. So, the delay here would be R 1 C 1 plus R 1 plus R 2 C 2 plus R R 1 plus R 2 plus C 3 into C 3. So, this is the formula proposed by L mode this is called L mode delay to give a very quick calculation of a delay the delay the numbers will not be accurate, but using this you can compare two design that analysis would be accurate at me the absolute value of delay does not matter. So, the PD that is why we say that propagation delay can be represented by this this formula this is this is very popular formula to compare multiple design. For example, two input NAND again take pen and paper and see that the bits here are actually correct according to your understanding and the values here are correct according to the R C mode. I am not going to going to go into details of the bit the calculation of bits of a two input NAND or into the how the values of C are calculated here this everybody should be able to do this exercise. So, we say that we try and calculate the delay estimate the delay for a NAND gate driving H NAND gates H identical gates. So, I will break it here the part on the left is this NAND gate the part on the right is this this circuit this is H and each gate input gives 4 C. So, the the capacitance here is 4 at 3 6 C 2 C we saw how this calculation we calculated earlier. So, now, we try and calculate. So, now when one of the PMOS is on ok let us say when when the output is rising when will output rise when will the NAND gate have a one input any of the input is 0. So, we assume only one of the PMOS is active and it connects to pull up network pull down network is not shown here right. So, this this part kind of goes away this part kind of goes away. So, the the capacitance left is 4 at 3 plus 16 and the resistance on R here. So, the T PDR according to L mode delay will be nothing, but R into 6 plus 4 at 3 right. Now, let us look at the fault delay. So, in case of fault delay the circuit will be seen is is the only the pull down part again 6 plus 4 at C and we will see a 2 C this this 2 C at the gate and this 2 C of. So, so this this part is this part and then from y it goes to a from y it goes to a R by 2 and 2 C this one is 2 C and again to B which is nothing, but R by 2. So, T PDR the L mode delay will be so L mode delay will be R by 2 into 6 plus 4 at C R plus R by 2 into 2 C. So, it will be 7 plus 4 at C R 2 this might seem complex at first, but if you go back to the L mode delay formula and apply it here it is a very simple network. So, this R this R by 2 into 2 C then this R by 2 plus this R by 2 into 6 plus 4. So, the T PDR is 7 plus 4 H into R C this is how we estimate. So, first we do the sizing, second we annotate the value of capacitance on to each of the inputs the gates the source of the train. Then we see then to calculate the propagation delay in either the right side or the fault side we first analyze which part is actually the pull up or pull down and then we take only the relevant part and then apply the ELMO formula to estimate the delay right. Now, the delay has two parts we saw earlier either either this 6 R C that means, the one at the left of it another is the right of it. So, one is the parasitic delay that means, the delay which is independent of load. We saw that a NAND gate driving H identical gates at one level it sees a cap which is inherent to it is gate design which is called the parasitic delay. We saw it is either 6 R C or 7 R C this is independent of load and there is the effort delay which is nothing, but the effort the gate requires to drive the fan out. It depends on the load proportional to load capacitor settings we saw it always 4 H R C. It would be this would does not this does not matter when output is rising or falling it just depends on the gate capacitor settings of the fan out gates of the connected gate. The contamination today now we have been assuming all along during the delay calculation that only for example, for a two input NAND gate only one of the inputs will call at one time either A will call and B will remain constant or B will call and A will remain constant. The contamination today refers to the condition where both the both the inputs are falling simultaneously and this can be much much lower than substantially lower than the regular population delay which means that the input will be reduced it will shoot to output quite fast compared to the other two cases. So, for calculation of contamination delay again since we are assuming that both N we are calling. So, we have to we have to assume the we say that both of these are are active. Now, see we have we have determined the widths 2 2 and 2 and 2 of PMOS and NMOS assuming that only one of the input width transition at one time we did not assume a contamination case assuming the widths to be same we calculate the contamination delay. So, the contamination delay is 3 plus 2 HRC these were these this formula out and it could be easy to calculate I will not go into details again. Now, this contamination delay is usually whenever the timing is calculated for the standard cells while preparing the library this contamination delay is usually not taken into account. Why is because the probability of multi of all the inputs of a multi gate multi input gate calling together is very very low, but we know this should be a dangerous state and we tackle this in a ways, but we do not take it take into account the delay part. We are only interested in the delay whenever only one of the input is told you how do we tackle it during digital design is a separate topic all together how do we tackle contamination delay I am not sure this is in scope of the scope, but there might be a mention of it when we do since this is a timing error. Just keep this in mind that contamination delay is one unwanted factor and usually the delay part is not part of a calculation ok. We assume contacted this slide we discussed earlier that wherever possible a good layout will minimize the diffusion area. For example, we saw the Nancy the layout that the region where it says merge in contact with the system we see that since the NAND since this part here shares the it does not need a contact since it does not need a connection outside. So, we do not put a contact here we share the diffusion area that is why we say that this NMOS here and then at this NMOS here there was a contact here and if they do not share the diffusion area this would see 3C this would see 3C this would total would be 6C, but we only say 3C here because they share the diffusion area. So, we are assuming that good layout practices will be followed and the diffusion will be shared and there will not be any contact. So, this will reduce the output capital sentence also. So, that is why good layout practices are mandatory to so this is one example that which layout is better I will leave it up to you to analyze which layout is better. I will I tell you the answer the answer is part A please go and figure out why do I say that way is better than the other left side is better than the right side based on whatever we have discussed in the earlier slide. So, this chapter was I agreed this chapter was a bit more complex in the earlier chapter, but it certainly does not for the coming chapter where we know now that the first chapter concentrated on how do we design how do we stitch and put together different team of NMOS to make a complex date. This chapter concentrated on how do we decide how is the transfer system and plus when we have already decided how why the transfer system how do we calculate the resistance and capital how do we annotate those values how do we calculate the L more delay again please know that L more delay is very very approximate way of calculation. I will not recommend using L more delay in actual scenarios it should only be used when you want to compare two different types for example where when you want to compare the layout of the left and the layout on the right you could actually annotate capacitance and calculate L more delay and decide which of the designs is better. So, L more delay is usually used to compare different design techniques not in the actual value of the delay is not taken in. So, please go please review the the width part where we decide the width of the NMOS and the PMOS from that carefully take the circuit such as the assignment is take the circuit such as the input NAND gate A O I 22 the set to input NOR gate that define the sizes annotate the R and the C values and calculate the rise and fall population base on the NMOS this is the assignment for this thank you.