 Hello and welcome to this presentation of the Embedded Flash Memory which is included in all products of the STM32C0 microcontroller family. The STM32C0 embeds up to 32 kilobytes of single bank flash memory. The flash memory interface manages all memory access, read, programming and erasing as well as memory protection, security and option bytes. Users using this flash memory interface benefit from its high performance together with low power access. It has a small erase granularity and short programming time. It provides various security and protection mechanisms for code and data applicable for read and write access. The main flash memory is split into two kilobytes pages that can be independently erased. A mass erase feature is also supported. Flash memory access may require wait states according to the actual CPU frequency. To reduce the latency, the flash controller embeds both an 8-byte prefetch buffer and 16-byte instruction cache. It also contributes to decrease the consumption because they belong to the V-core power domain. In addition to the 32 kilobytes of the main flash memory, the STM32C0 supports a system memory of 6 kilobytes containing the ST bootloader, an OTP memory that can be used to store user data that cannot be erased, option bytes containing default settings to configure IPs in the system on chip, and they're automatically loaded after a power-up reset. The system memory is reserved and contains the bootloader used to reprogram the flash memory through one of the following interfaces, USART1 and I2C1. The first table details the memory organization based on a main flash memory area and an information block. The second table details the granularity of the flash memory operations, programming is done on 8-byte double words, fast programming is done on a row of 256 bytes, arrays is done either globally or on 2 kilobytes pages, the secureable memory is aligned on pages, write protection is done per page, read protection is global, and proprietary code readout protection is done on 512-byte areas. Fast programming enables the programming of a row of 256 bytes, while normal programming has a granularity of 8 bytes. The main purpose of fast programming is to reduce the page programming time, it's achieved by eliminating the need for verifying the flash memory locations before they're programmed, thus saving the time of high voltage ramping and falling for each double word. By default, access to the flash control register is locked. Executing the unlocking sequence is required prior to raising or programming the flash memory. Fast programming a 2 kilobyte page is 30% faster than standard mode programming. Mass arrays time, meaning a 32 kilobytes arrays operation, approximately takes the same time as a page arrays. Fast programming versus standard programming, 256 consecutive bytes are programmed instead of 8-byte double words located anywhere in the main flash memory, 8-byte programming is more reliable due to the verification step. Note that the maximum time between two consecutive double words is around 20 microseconds. If a second double word arrives after this delay, fast programming is aborted and a flag is set. Consequently, interrupts should be disabled to make sure that this delay is not exceeded. This table summarizes the differences between standard and fast programming. Each program and arrays operation can degrade the flash memory cell. After an accumulation of programmer and array cycles, memory cells can become non-functional causing memory errors. Endurance is the maximum number of erasing and programming sequences that the flash memory can support without affecting its reliability. Their retention is defined as retaining a given data pattern for a given amount of time. The retention depends on the number of program and array cycles and also on the temperature. The flash memory has a fixed access time, while the AHB bus frequency can be dynamically changed. That's why the number of wait states is programmable and has to be set according to the actual AHB frequency called HCLK. When the number of wait states is non-null, the flash memory accelerator should be activated to limit the performance impact. CPU generates 32-bit instruction fetch requests. The 80-bit instruction fetch request can be set according to the HCLK frequency. Increasing the number of wait states must be done prior to increasing the frequency. Decreasing the number of wait states must be done after having decreased the frequency. The eight-byte line containing the requested instruction is read from flash memory and stored into the current buffer, while the requested word is directly transferred to the CPU. The next line is automatically read from flash memory and stored into the prefetch buffer. So, in case of sequential code, back-to-back words will be delivered over the SAHB until a branch is encountered. When the code isn't sequential due to a branch, the instruction may not be present in the currently used instruction line or in the prefetch instruction line. In this case, the penalty in terms of number of cycles is at least equal to the number of wait states. Small loops can be entirely stored in the current and prefetch buffer no flash memory access is needed. The flash memory controller also implements an instruction cache of 16 bytes. Each time the requested instruction isn't in the current and prefetch buffers, the line is copied into the instruction cache. If an instruction contained in the instruction cache memory is requested by the CPU, it's provided without inserting any delay. Once all the instruction cache memory lines are filled, the least recently used, or LRU, policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops. Instructions at the branch target address will be present in the instruction cache. Both the prefetch buffer and instruction cache are enabled, disabled by software because their impact on performance depends on the number of wait states to access the flash memory. The instruction cache can also be reset by software. The performance continues to increase linearly with the frequency when accelerators are enabled, i.e. prefetch buffer and instruction cache. The slope of the curve related to prefetch on and cache on is almost not affected by the transitions from 0 to 1 wait states achieved at 24 MHz, from 0 to 24 MHz. Enabling the prefetch buffer and the instruction cache doesn't improve the performance. This array also shows that enabling the prefetch buffer and the instruction cache contributes to reducing consumption due to flash memory accesses. Readout protection aims to protect the contents of the flash memory, option bytes, internal SRAM, and backup registers, again reads requested by debuggers or software reads caused by programs executed after a boot from SRAM or bootloader. Only a boot from flash memory is permitted to read the contents of these memories. The proprietary code protection is a way to mark parts of the flash memory as execute only. Note that this kind of access permissions is not supported by the memory protection unit present in the Cortex M0+. The user can declare two PC-ROP areas aligned on 512-byte addresses. PC-ROP areas are useful when only a part of the flash memory has to be protected against third-party reads. Write protection prevents part of the flash memory from being erased and reprogrammed. The main purpose of the Securable Memory area is to protect a specific part of flash memory against undesired access. This allows implementing software security services to secure key storage or secure boot in charge of image authentication. Once the processor has exited the Securable Memory, this part of the flash memory is no longer accessible. The Securable Area can only be unsecured by a reset of the device. The size of the Securable Memory area is aligned on 2-kilobyte pages. In addition, the code executed from the Securable Memory can temporarily disable debug accesses. Option bytes are used to early configure the system on chip before starting the Cortex M0+. They represent 128 bytes. They're automatically loaded after a power reset or on request by setting the OBL launch bit in the FlashCR register. This capability is required to apply a new setting without resetting the device. This slide and the two next ones describe the various fields of the option bytes. Bit28 configures the NRST pin, either as a GPIO, as a reset input only, or as a reset input and output. When it's a reset input and output, Bit29 configures the output stage, either a pulse generator or a low-level driver, which drives the pin low until it's seen as low-level. This is useful when the reset line has an important capacitive load. The readout protection level enables the readout protection for the entire Flash memory, level 0 no protection, level 1 read protection, level 2 no debug. The following transitions are supported, level 0 to level 1, level 1 to level 0, which implies a partial or mass arrays, level 0 to level 2, and level 1 to level 2. PCROP ASTRT and PCROP AEND define the proprietary code readout protection address range A aligned on 512 bytes. PCROP BSTRT and PCROP BEND define the proprietary code readout protection address range B aligned on 512 bytes. PCROP RDP allows to select if the PCROP area is erased or not the PCROP protection is changed from level 1 to level 0. SecSize defines the size of the secureable memory. BootLock allows forcing the system to boot from the main Flash memory regardless the other boot options. The boot memory is selected from both option bytes and also from the boot zero pin. This table indicates in which memory the processor will boot according to the combination of parameters. Note that when nboot cell bit is set to 1 the boot zero pin is ignored. Only option bytes select the boot memory. When the boot log bit is set to 1 in option bytes only boot from Flash memory is supported. During the option bytes loading phase after loading all options the Flash memory interface checks whether the first location of the main memory is programmed. The result of this check in conjunction with the boot zero and boot one information is used to determine where the system has to boot from. It prevents the system to boot from main Flash memory area when new user code has been programmed. The Flash memory controller supports many interrupt sources listed in this slide in the next one. An interrupt can be asserted upon successful end of operation. An interrupt can also be asserted when an error occurs during a program or erase operation. Protection violations can also cause interrupts. A size error occurs when the data to be programmed is not word aligned. Programming sequential error occurs when a program operation is attempted without having previously erased the location in Flash memory. A programming alignment error occurs when a complete double word isn't provided before initiating a standard program operation or when a complete row is not written before initiating a fast programming operation. A data miss programming error occurs when data isn't written in time during a fast programming sequence. The Flash memory module can be cloggated when the processor doesn't need to access the Flash memory and also in low power modes. The Flash memory module can also be power gated in stop mode. The Flash memory module supports the following low power capabilities clock gating, flash memory power down mode, power gating of the entire module, flash memory and controller. In run and sleep modes, only clock gating is supported. In stop, the clocks are gated and flash memory can enter power down mode. In standby and shutdown mode, the power of the flash memory module is gated for both the flash memory and controller. The STM32 C0's flash memory interface supports the same features of the flash present in STM32 G0 except that the ECC protection isn't implemented. The cache and prefetch buffer decrease latency and consumption. The one-time programming or OTP area is used to store non-erasable data. Fast programming programs a row of 256 bytes instead of discrete 8-byte double words. PC Rob stands for proprietary code readout protection which protects the code by only allowing the execution from flash memory but not reading or writing. Securable memory cannot be called from non-secure areas. It's typically used to perform a secure boot with image authentication. The flash memory module has relationships with the following other modules. Memories protections, system configuration controller or syscfg reset and clock controller or RCC, power controller or PWR, interrupts or NVIC security memory protections. For more details please refer to application node AN2606 about the STM32 microcontroller system memory boot mode. Thank you for attending this presentation.