 Our write operation is actually even simpler than our read operation. It will still take a whole clock cycle to complete, but this time our master device wants to tell the slave device to write some data to itself. So the master device puts the address and the right signal onto the bus. It also puts the data that it would like to write on the bus. And then both of those just propagate across the bus. Slave device will see that request, take the data and store it into the requested register. So in this case, nothing really interesting is happening in terms of our timing. Everything goes on at the beginning of the clock cycle and stays there until the end of the clock cycle.