 Hello and welcome to this presentation of the STM32 SDMMC controller module. It covers the main features of the controller which is used to connect the CPU to an SD card, MMC card or an SDIO device. The SDMMC controller provides a communication interface for the microcontroller to communicate with multimedia cards, SD memory cards and SDIO devices. This interface is fully configurable, allowing the easy connection of external memories thereby extending mass storage capability when more memory is needed. Applications benefit from the reduced pin count required to interface with memory cards. With the SDMMC interface, applications can easily manage high speed read and write operations in external flash memories. The SDMMC controller supports data bus widths of 1-bit mode, default 4-bit mode and 8-bit mode for enhanced data throughput. The SDMMC interface interconnects with the internal DMA or IDMA to offload the CPU during data read or write transfer periods. The SDMMC clock generator can generate signals up to 400 kHz for the initialization phase and up to 100 MHz for cards supporting SDR50 mode. To enhance power consumption, the SDMMC clock can be disabled when the command and data busses are idle. The controller can interface with SDIO modules with advanced features like read-weight, suspend-resume operations and standard operations like multi-byte transfer and interrupt signaling in 1-bit and 4-bit modes. In MMC mode, it supports stream mode, boot and sleep operations. The SDMMC controller is an SDMMC bus master that provides all SD, SDIO and MMC functions needed to interface with cards. It consists of an SDMMC adapter and an APB interface. The SDMMC adapter provides functions such as clock generation, command and data transfer, while the APB interface manages the control and status registers, FIFO buffers as well as DMA and interrupt requests. Two clocks are available for the SDMMC controller, the APB clock or PCLK for the APB interface, and the SDMMC clock or SDMMC CLK for the SDMMC adapter. The SDMMC adapter includes a control unit that contains a power management module and a clock control module with the clock divider for the card clock, SDMMCCK. The clock control module provides a 10-bit pre-scaler for SDMMCCK clock generation, which allows it to generate a clock ranging from SDMMC CLK down to SDMMC CLK 2046. DDR memory devices are not supported in divide by one mode. The control unit can disable SDMMCCK generation when the bus is idle. The command path circuit is used to program a command response sequence. When enabled, the command path shifts out the command index and argument on the SDMMC CMD pin. After the last payload bit is sent, a CRC7 is computed and sent on the bus before generating the end bit. SDMMC CMD in and SDMMC CMD out are two modes indicating how the SDMMC CMD pin is working. When a response is expected, the command path is configured to SDMMC CMD in and waits for the device response. The transmission and reception of commands is controlled by the command path state machine or CPSM. When no command or response is in progress, the command path is in idle state. When the CPSM is enabled to send a command, the command path moves to send state until the last bit of the command is sent. Then depending on whether a response is expected or not, the CPSM can return to idle state when no response is expected or move to a wait state and wait for a start bit on a command pin. Start of the response transmission. When a response start bit is detected within the allocated time period, the CPSM moves to receive state. After receiving the last bit of the response, the CPSM verifies the response's integrity using the received CRC and then returns to idle state. The CPSM returns to idle state after a timeout if a response start is not detected. The CPSM can be configured to send a command synchronized with the end of data transfer. When this feature is enabled, the CPSM moves to pending state and waits for the end of the MMC stream transfer. When the last data signal is triggered by the data path, the CPSM moves to send state. The CPSM can be configured to initiate the boot normal or alternative boot procedure. To trigger this boot phase, the CPSM moves to boot state. When all data in the normal boot mode has been received, the CPSM terminates the boot phase and returns to the idle state. When all data in the alternative boot mode has been received, the CPSM moves to the send state to terminate the boot phase by sending the CMD0 reset command. The SDMMC controller offers high flexibility for configuring the command indexes and arguments. With a flexible 32-bit register for configuring arguments and an independent 6-bit field for the command index, this architecture ensures that the firmware can address any type of card. The command path state machine is able to generate all command tokens with no restrictions on command index or argument. In addition, the start-bit, transmitter-bit, CRC, and end-bit fields are automatically generated and sent on the bus. Our response is a token that is sent from the card as an answer to the previous command. There are two types of responses, short and long. With 4 32-bit response registers and no response constraints, the SDMMC interface supports both long and short responses to correctly initialize the card and communicate with it. Short responses have a total length of 48 bits and are composed of a mirrored command index, 32-bit command status, start-bit, stop-bit, and CRC7 checksum. When a short response is received, the command status is saved in the SDMMC RESP1 register, and the mirrored command index, when available, is copied to the SDMMC RESP-CMD register. Long responses have a total length of 136 bits and are composed of the 120-bit CID CSD register content with the start-bit, stop-bit, and CRC7 checksum. When received, the CID CSD card register is copied to one of the four SDMMC RESP-X registers. The SDMMC interface also features the automatic detection of a start-bit, command index extraction, 32 or 128-bit response extraction, and automatic CRC7 verification. Once the SDMMC ARG and SDMMC CMD registers are programmed with CMD index, weight RESP equals 01 or 11, and CPS men equals 1, the CPSM moves from idle to send state, and the host starts driving the SDMMC CMD line to send the command to the card. If the CPSM is programmed to wait for a response, weight RESP equals 01, 10, or 11, it enters the wait state and the command timer starts running. If the card doesn't respond within the maximum NCR time, the timeout flag is set, and the CPSM returns to idle state. When no response is programmed, weight RESP equals 00, the CPSM returns to the idle state. Once a start-bit is driven by a device, it is detected on the command line, and the CPSM moves to receive state. When the response is fully received, the received CRC code and the internally generated checksum code are compared, and the appropriate status flags are set in the SDMMC interface status register. Then the CPSM enters the idle state. Note that the CRC fail flag will only be set for responses with a CRC, and when the CRC check failed. After a complete command with a response is received, the CPSM remains in idle state for at least eight SDMMCCK clock periods to meet command-to-command timing or NCC and response-to-command timing or NRC constraints. The data path transfers data both to and from the SD, SDIO, or MMC card. In single data rate, or SDR mode, on each SDMMCCK clock cycle, the data path can send one, four, or eight bits depending on the bus width configuration. In double data rate, or DDR mode, on each SDMMCCK clock cycle, the data path can send two, eight, or sixteen bits depending on the bus width configuration. Transfer logic is clocked by the SDMMCCLK clock. It is divided into two subunits, one for data sent and one for data received with a dedicated control bit and status flags. The data buffer is not part of the data path. Transmit and receive FIFO logic are mapped in the AHB domain. All signals from the different subunits are resynchronized. The CRC calculator guarantees data integrity between the card and host. At the end of the data packet, the CRC is calculated automatically. In single data rate, or SDR mode, depending on the configured data bus width, the data path sends data blocks over one, SDMMCD0, four, SDMMCD0 to SDMMCD3, or eight pins. SDMMCD0 to SDMMCD7. First, a start bit is generated on the bus followed by the data packet with the first to last bytes of the sequence, the fourth byte in our example. Then the CRC16 and end bit are appended to the data packet on the bus line. In a four-bit data width configuration, each line has its own start bit, end bit, and CRC16 check sum. When the data is sent to the card, the card returns a CRC status on the SDMMCD0 pin. In this example, the four bytes are sent over the SDMMC bus in eight-bit mode. For each SDMMCCK clock cycle, a byte is shifted out with a start bit, end bit, and CRC16 check sum on each data line. When the data is sent to the card, the card returns a CRC status on the SDMMCD0 pin. The DatapathStateMachine or DPSM controls the transmission and reception of all data. When the DPSM is in idle state, the first transition is triggered when the DPSM enable bit and transfer direction are set. Note, the DPSM enable bit must not be used to transfer data with SD, SDIO, and MMC cards. For data transmission, when enabled, the DPSM moves from idle to wait-s state and then to send state. While in wait-s state, the DPSM waits until the data-fifo-empty flag is de-asserted. When data is available in the FIFO buffer, the DPSM moves to the send state. In send state, the DPSM starts sending data to a card according to the data rate, the bus mode, and the bus width set in the control register. At the end of each data packet, the DPSM sends an internally generated CRC code and end bit and moves to the busy state. In busy state, the DPSM waits for a CRC status flag. If it receives a positive CRC status, it moves to wait-s state when the card is not busy. From wait-s state, a new packet transmission can start or the DPSM can return to idle state when all the data is transmitted or the transfer is disabled. A negative CRC status from the card or a FIFO under-run error can force the DPSM to return to idle state when the card is not busy. For data reception, the DPSM moves from idle to wait-r state. When a start bit is detected on the bus, the DPSM moves to receive state, where it remains until a full packet is received. As long as the end of data transfer flag and errors are not detected, the DPSM will keep switching between wait-r and receive states. If an error or the end of data transfer flag is detected, the DPSM will return to idle state. If the transfer is to be disabled, the DPSM moves to the idle state. A read-wait state is an SDIO-specific operation to stall the transfer in order to execute other commands or internal operations. It can be reached from receive state while a transmission is ongoing or from idle state. When the firmware requests a read-wait stop operation, the DPSM moves to wait-r state and waits for a start bit from the SDIO device. For boot acknowledgement, the DPSM moves from idle to wait-axe state. When a positive acknowledgement is detected, the DPSM moves to wait-r state to receive the boot data as for data reception. If a boot acknowledgement timeout or a negative boot acknowledgement is received, an abort command has to be sent by the CPSM, whereafter the DPSM moves to the idle state. In double data rate or DDR mode, depending on the configured data bus width, the data path sends data blocks over 4 SDMMC D0 to SDMMC D3 or 8 pins, SDMMC D0 to SDMMC D7. First, a full cycle start bit is generated on the bus, followed by the data packet with the first to last bytes of the sequence with odd byte data on the falling edge of the clock and even byte data on the rising edge. The fourth byte, in our example, then the odd and even CRC16 check sums and full cycle end bit are appended to the data packet on the bus lines. In a 4-bit data width configuration, each line has its own start bit, end bit, and odd and even CRC16 check sums. When data is sent to the card, the card will return a full cycle CRC status on the SDMMC D0 pin. Double data rate mode is not available in 1-bit mode. In this example, the 4 bytes are sent over the SDMMC bus in double data rate 8-bit mode. For each SDMMC CK clock cycle, 2 bits are shifted out with a full block cycle start bit and end bit and odd and even CRC16 check sums on each data line. When data is sent to the card, the card will return a full cycle CRC status on the SDMMC D0 pin. In MMC stream mode, the data path sends a stream over one pin, SDMMC D0. First, a start bit is generated on the bus followed by the data stream with the first to last bytes of the sequence, the fourth byte, in our example. Then the end bit is appended to the stream on the bus line. In stream mode, there is no CRC and the card will not return a CRC status after having received data. A 32-bit wide 16-word deep FIFO is used to buffer data between the slave AHB domain and the IDMA on the master AHB domain. A single data FIFO is the data source for the data path transmit and receive packets. Depending on the DPSM status, the data path FIFO can be disabled, transmit enabled or receive enabled. Dedicated receive and transmit FIFO status flags are available to ease firmware implementation. When enabled, the IDMA transfers data between the FIFO and an external memory offloading the CPU. The integrated DMA inside the SDMMC transfers data between memory and the SDMMC FIFO, allowing reduction of the CPU processing and AHB bus load. Two IDMA operating modes are supported. Single buffer mode, where all transfer data is located in a single linear buffer or double buffer mode used to alternately transfer data located in one of the two buffers or creating a buffer linked list. The IDMA double buffer mode allows firmware to update one buffer while the SDMMC transfers the data of the other buffer. Either transfer data is alternated between two buffers with fixed base address or the buffer base address is altered, allowing creation of a linked list. Every time the IDMA reaches the end of one buffer, an IDMA buffer transfer complete interrupt is generated. The hardware flow control function is used to avoid FIFO underrun when DPSM is in send mode and overrun errors when DPSM is in receive mode. The hardware flow control logic stops the SDMMC CK PIN signals and freezes the DPSM when a risk of underrun overrun is detected. In send state, the SDMMC CK PIN clock signal is stretched and the DPSM is frozen to prevent any FIFO underruns. The clock and DPSM are restarted when the FIFO is half-full or all the last transfer data is available in the FIFO. In receive state, the SDMMC CK clock is stretched and the DPSM is frozen in receive state while the FIFO is full, risk of overrun. The clock and DPSM are restarted when the FIFO becomes half-empty. Concept. The read weight operation is an SDIO specific operation that allows the host to temporarily stall the data transfer between data blocks for better managing the data buffer or for sending commands to other functions of the SDIO device. The SDMMC controller supports two read weight modes either by stopping the SDMMC CK or using SDMMC D2 signaling. The advantage of SDMMC D2 signaling is that you are still able to communicate with the card while in read weight mode. When the RW start bit is set after the data block is fully transferred and the CRC code is correct, the DPSM moves to the read weight state. The DPSM remains in read weight state until terminated by writing 1 to the RW stop bit. The RW stop bit is auto-cleared by hardware once the read weight phase is terminated. If the CRC code fails any further, all data transfers are stopped and the DPSM remains in the receive state. An abort command needs to be sent by the CPSM which moves the DPSM to idle state. In this case, the read weight state will not be entered. With multifunction cards, there are multiple devices that share the access to the SDBuds. When the function supports suspend-resume, the host can temporarily halt data transfers to perform other internal operations or to communicate with other functions and then resume the suspended transaction. If a card supports the suspend-resume feature, the host can temporarily halt a data transfer operation to one function or memory in order to free the bus for a higher priority transfer to a different function or memory. A command with the CMD suspend bit set must be sent to indicate to the SDMMC that the current command is a suspend command. If a suspend request is accepted, the DPSM will wait in weight R state as the function is only suspended after a complete data block. When IDMA mode is used, it empties the reception FIFO. If the application reads the FIFO, it has to empty the reception FIFO before setting the DT hold bit to idle state. When the FIFO is empty and the DT hold bit is set, the DPSM moves to idle state. Only then can the firmware start communication with a higher priority portion of the card. In order to restore a suspended transaction, the firmware needs to reconfigure the DPSM to read the remaining data before requesting a function resume. This function is no longer supported in SDIO version 4 or more recent. The interrupt concept is used to inform the host of changes in the card status using the SDMMC D1 IRQ pin in 1-bit or in 4-bit data bus mode. SDIO interrupts are sent from the card to the SDMMC host when the card detects an external event. Interrupts are only sent outside the data transfer periods. The SDMMC host detects interrupts sent on the SDMMC D1 pin once the SDIO EN configuration bit in the data control register is enabled. While the DPSM remains in idle state and in busy state between data blocks for DS, HS, SDR12 and SDR25 speed or after the last data block in all speed modes, all low levels on the SDMMC D1 pin are detected as interrupts from the card to the host. Here is an overview of the peripheral status at specific low power configuration modes. The device is not able to perform any communication in domain or system stop mode and lower. It is important to ensure that all transmissions are completed before the SDMMC controller is disabled or the domain or system is switched down to stop or standby mode. Note that the AHB bandwidth must be at least three times greater than the SDMMC bandwidth. Performance depends mainly on the SDMMC bus width and clock configuration. The SDMMC interface can generate clock signals up to 100 MHz. But real speed can be decreased by the application and depends on several factors. The SDMMC bus capacitance has to be considered as PCB track and card input capacity can play a significant role. GPIO settings also have an effect. Fast GPIO mode should be applied on command, data and clock signals. Lower power supply voltages and extreme ambient temperatures slow down the edges. And in some cases, the application can't always manage fast data flows, especially due to overly frequent exception servicing or long time spent in interrupt handlers. Note that the AHB bandwidth must be at least three times greater than the SDMMC bandwidth. The SDMMC interface can be used in a wide range of applications where a low pin count is needed to interface with removable or permanent mass storage data memories. The SDMMC controller can be used to extend device connectivity when using external SDIO devices, for example Bluetooth SDIO modules. Here is a list of peripherals related to the SDM32 SDMMC interface. Users should be familiar with all the relationships between these peripherals to correctly configure and use the SDMMC controller.