 Hello friends, welcome you all to the 12th session of the ARM based development class. Today we will be complete we will be covering a few more instructions after having test upon data processing and data transfer instruction. So, the following are the kinds of kind of instruction that we will be looking at today. There is one special instruction called SWAP I will explain you what it is and what where is it used for andwhat are the precautions that we need to take while using them. And then there are set of instructions which are reserved only to operate on the process status registers and then some pseudo instructions I will tell you what exactly they are ok. SWAP instruction so, all of you are aware what do we mean by SWAP right. So, suppose you have one content in a particular place okassume this you know it is a register or memory you know it is having two values a and b ok. Just a read and write will try to read from the contents from here and then write mean it will write the new content over writing the existing value. When you do SWAP what happens is we are interchanging the values in these locations ok. So, a will go here and b will come there. So, in our case in the processor case CPU is here the processor ok ARM processor is there and we have a memory ok. Now we want to SWAP contents between these two that means, what we have some register a specific register in the processor and then some specific location in the memory then we want to swap the contents. Now it is very logical to say when you are swapping the contents the number of bits that we transfer or the number of bits that we swap should be the same right. Suppose if you are swapping 32 bit value means you are this 32 bit value comes here and this 32 bit value will go here. Similarly, we could also do a 8 bit if you are swapping to 8 bit values some 8 bit low LSB of this and LSB of this will get transfer. So, basically SWAP means in a interchanging two values between two locations in our case it is between a register and a memory location. Now you may wonder what do we why do we need one special instruction for this we could do this way right. I will say that ok suppose I want to transfer a register value which is in R 0 to a memory location of a favorite address chosen what we can do we can do it through two instructions. First we say that now move R 0 to this location ok. Now what happens this content is overwritten if you if you transfer it site away you are not preserving this value correct. So, what we should do first we should read this content ok suppose you are interested in transferring the you know swap swapping the contents between 1000 you should read whatever is stored here to some temporary register ok. Let us call it as R 1 another register I am using and then I am interested in swapping between R 0 I said initially. So, I will write R 0 into that location ok. So, what happens now we are overwriting this content with the value in R 0, but we have preserved what was the old content at that location and then we can internally move R 0 from R 1 we can move the content ok because it has already come into the register processor ok. So, we are doing two memory operations one is read memory read ok and then one is memory write and then one register transfer to accomplish this job. You could do this, but swap is not introduced in the processor to save all these three different instruction into one the main purpose is not that. The main purpose is when I am doing this exchange I want to make sure that the content that I am interested in swapping with I do not want any other processor or any other memory operation to change that value in between. You may wonder how can it happen anyway I am doing it you know immediately after one instruction each. So, why should it or how should it happen? In a typical example here even if I am doing it with three consecutive register you know instructions please remember once one instruction is executed in a processor interrupt can happen ok. So, after completing the instruction execution the processor looks at very the interrupt are there or any exceptions are there it will go and then perform go to the handler and do the job whatever is meant in the handler you know mention in the handler and then comes back and execute an x instruction. So, there can be a interruption between two instructions ok it cannot you cannot make sure that two instructions are executed one after the other there is no guarantee that is one point. Another one is this processor may be running it continuously without any interruption, but imagine a case where there is a common bus there are processor here P 1 it is a multiprocessor system ok there is another processor P 2 which is also connected to the same cause no same bus this is bus ok sorry about the lines it is like Indian boards ok this is a memory this is common memory which is being accessed by both the processors. Now what happens the the bus normally if you are aware of all the bus interactions there will be an orbiter in the bus ok which will be allocating the memory cycles for each processor ok. So, suppose I am executing this whole instruction in this P 1 it has executed the first instruction of reading from 1000 after that the bus is given to P 2 because every memory cycle can be broken into multiple things and then the orbiter can come into play and then give the access to any kind of processor. Now you assume an OSTC scenario where P 2 is also updating then same location that you are interested in updating in P 1 this is shared memory. So, what happens what you read between somebody has changed it ok we we do not want this particular scenario to happen I will explain you why it is important not to have any other processor or any interruptions to modify the value before this swapping happens. So, to to make sure that this swapping operation is done without any interruption between the memory cycles we are using a swap instruction ok. So, how does it make that because swap instruction is executed in one particular processor ok you are executing the swap instruction in this processor it does not have any control on what happens with this processor, but the P 1 the processor which is executing the swap instruction make sure that it informs the memory controller ok with a lock signal there is assume there is a more signal going apart from data address and read write all those things. To indicate the memory say I am doing here a swap operation which will involve one read and write. So, I do not want any other memory cycle stealing happening in between these transactions. So, what happens is indirectly the memory prevents from other processors in the same bus accessing the same memory ok getting a control before this transaction happens with this particular scenario with the support of hardware with the support of the memory ok this swap instruction works. So, it is not that only the processor decides, but only based on the swap instruction it it knows that ok it is supposed to generate a lock signal to the memory to say that this transaction involves one read ok one read here and then one write here which should not be broken in between. That means, it should not be interacted with some other memory either write from any other processor or a DMA. See DMA could have been programmed by some other processor to transfer some content may be from a peripheral to the memory ok it may do a read write. So, that may also access the same particular location the thousand that processor is interested in accessing. So, it could be a DMA or it could be a different processor or the same processor may have an ISR or handler which may modify the value. So, we do not want this particular value to be touched by anybody else before this swap operation completes the operation ok. So, I hope this is clear to you why we need it let us see ok. So, I will tell you some more examples. So, that this is a background of this once I explain you this you will be clear about that ok. Now, what is the format of swap instruction? I told you swap could be a word transfer exchange word exchange or a byte exchange ok. So, B could be written before swap in you know in front of swap. So, that to indicate that it is a byte exchange condition code you are all aware if this is a condition code you mentioned if it satisfies only this instruction of the executor and R D, R M and R what are they? R M from the symbol you can make out that this is a base register ok. The value pointed to by R M is the location where you are interested in exchanging the information ok. In our case R M may be having a 1000. So, in the case we will be exchanging the value which is there at the location 1000 with the registers. Now, what are these registers? There are two things mentioned here what it means is I can what you can see thewhat is happening see. Whatever is pointed to by R M is a memory 32 bit operation if it is a swap if it is a swap byte it is a memory 8 ok. So, that address whatever is the content is swapped to a temporary location because it cannot overwrite on the destination register directly because I might have both R D and R M mentioned as the same register. Now, for a moment I have seen that I have this as R 1 ok this as R 2. What does it mean? I am interested in writing the value which is in R 2 into the base register whichever it is pointing at that value I want to transfer it and then what R n was having earlier I am interested in writing into R 1. So, this is alright if these two registers are different, but suppose if I have mentioned both registers same I can do that also this instruction allows it ok. Because main purpose I mentioned that I am interested in exchanging information between a register and a memory. So, though this instruction provides two operands here to be mentioned as two different register values you could also decide to do it with one. In the case what happens the value which is being read then read from R n should be kept somewhere temporarily for for us to change write the value which was there in the R 1 to the memory and then whatever you read from the memory you copy into R n. So, that is why you see that there is a temporary location coming here. What is this temporary location? Is it a memory or a register? It is a register which is insert the processor we do not know how it could be a buffer which is maintained by the processor ok. It copies the value which has been read from the memory temporarily it keeps it here ok and then you have written you said that I am interested in changing the R 1 value. So, it goes back to the same location in the memory ok. So, this is the memory and then what happened this temporary location whatever value was read from the memory goes here. So, finally, what happens these two values are being exchanged that is what we are doing using this instruction. So, we could do either a byte or a word transfer good let us see. Now, it is a special case of load store ok because it involves one load as this one store first what happens first load happens and then store happens. It serves the contents of memory with the contents of a register I explained you already. So, what do we call this operation as? It is a atomic operation where do we say it is atomic because the read and write happen in the same memory cycle. What I mean by same memory cycle means though read cycle happens and write cycle happens there is no other memory cycle in between them it is not broken. So, the preventing any other instruction from reading or writing a this location in between ok. So, swap cannot be interrupted by any other instruction or any other bus activities very important it cannot be interrupted by any other instruction or any other bus activities. So, what I mean by any other instruction mean the swap instruction gets completed only when both read and write are there. So, even if an ISR you know extra interrupt happens or a exception happens it will wait for this particular instruction to be executed only before it can be interrupted. Similarly, the bus also cannot give the control to the some other processor or a DMA before this particular swap instruction gets executed ok. This is what is called the hold the bus ok. The swap instruction holds the bus until the transaction is complete ok. Now I told that it cannot be interrupted and it has to be done in a single cycle all that, but I have not told you why it is required ok. I will tell you for a moment please hold on then let us look at the format and then I will take you to the place where I will explain you why it is required and where it is needed ok. Let us see the instruction format this is very important as we have seen so many formats so far. Now you see here you could see that the off code or the special bit pattern after the conditional flag in this indicator 4 bit value it is increasing. If you saw if you remember the data processing had only 0 0 and the data transfer had 0 1 if I remember correctly. But now it is a 5 bit value why because they have to know somehow encode them into the available 32 bit value and one advantage of relaxed number of bits alerted for this is there are no other address format supported by this instruction. If you remember we had a whole lot of 12 bit reserved for the immediate constant and then we tried you know we did so many kinds of shift and rotate operations on it before the operand was given to the RDR it was used by the instruction. In this case you see only the registered values are mentioned ok. So, it is clearly you can make out that you cannot do any shift operation or any other rotate operation on the operand 2 even if it is you know there are one operand which can go through barrel shifter you cannot mention any of those operations in this swap instruction ok. So, effectively this is the format ok these are all reserved ok some values. Now, I think everything is clear to you from the explanation. So, Rn is the base register which is getting swapped with the value in Rm gets written into and sorry Rm value is written into the ok let me write it again for you to remember recall. So, Rm is written into Rn and what was there in Rn goes into Rg ok and as I mentioned these two can be same registers also. So, there are two locations maintained in the instruction format, but you can hold the same value you can have one and this also can be mentioned as one ok. I am sorrythese two ok Rd and Rm only can be same, but Rn has to be different ok. The base register and these two all you cannot mention everything as same ok only Rd and Rm can be same, but Rn needs to be a different register ok. If it is one it could be two or whatever remaining values very good. So, no offset completion options are available in this as I mentioned to you ok. Let us see where is it used I explained this already multiple processors ok. Thisprocesses I mentioned DNA I mentioned, but within the processor itself no all of you must be aware within the processor itself there can be multiple processors running ok P 1, P 2 they are different processors ok. Now, if you have a basic OS understanding any process ok can be swapped ok. What I mean by swapped is thethis particular process which is running in this processor is swapped out to the memory ok. All the contents of all the registers are copied and then a new process is brought into the CPU. So, what happens? Another process starts running. So, the context switch that is what we call as a context switch andone process may be doing that operation whatever I mentioned and in between it could be interrupted because the time slice may happen if you really call in your OS code time slices are there between two time slices processes the OS schedulers decides to come and then remove this process which has already exhibited so much time in their processor it swaps it out and then brings another process. So, this switching context switching could happen between those three instructions I mentioned to you. So, because I mentioned that the memory whatever it is being accessed cannot be interrupted even this should not happen ok. So, by performingswap operation which is atomic we can avoid all three of them ok very good. Now, let us see I mentioned to you R D and R M may be same register ok and memory values are exchanged between the register and memory, but R N should be distinct from these two I told you that also. One more important point is P C the R 15 cannot be used as any of this operands ok. You cannot mention R 5 at all R 15 at all in the swap instruction because it is a pointed to the program. So, it does not make sense to change that content at all right because when you are using R 15 what are you trying to do suppose you are using here you are trying to modify the content of the program itself because the P C will be pointing at the program 4. So, you cannot go and swap with some other content of R N or R M and then you know it may have a you knowunpredictable results. So, ARM processor does not allow such kind of a transfer and ARM execute separate memory read and write cycles ok. They perform one read cycle and note write cycle, but in that you mean I mentioned to you a lock signal is generated to indicate to the memory that once the read has happened do not break the memory cycle allow another write cycle to happen from the same processor. So, that they to both of them happen simultaneously without any break in the program ok very good. Now, let us see I am giving you an example first and then telling you where it is useful. I hope most of you would have heard CMA 4 in your previous course in the operating system course, but just to refresh your memory I will tell you where exactly it is used and how it is implemented in a particular processor. It could be in there may be different way, but I am taking one sample and then it is telling you how it is done. Take an example suppose this is the data ok is a very critical database ah database means it could be a one single board also or it could be a structure on to which is in the memory ok this is in the memory. Now, this is a CPU ok I am drawing a very big CPU here. ESCPU is the processor with the two processes running P 1 and P 2 ok. Now, both of them are accessing this database ok reading and modifying something, but we do not want both the processors to be in the database in a when I say in the database means when when they are accessing them I call that they are in the product that they are in the middle of doing something. We do not want both the processors to be given access to this ok while other processors is doing something with the database because there will be a inconsistency. It is similar to you know allowing you to log in to your bank account from two web browsers ok. If you are trying to useyour city bank or any bank HGSE or any bank you are trying to access your account with the account. Suppose you open the browser ok you are accessing it with the same user ID password and then maybe you have a mobile or another tablet or maybe on the same PC with another login you are trying to use the same account you are trying to access your account. What is what does it happen normally? It says that it is already open or your account is already being used. So, it does not allow you to access it from two places right. So, it is similar to this that means, it does not allow two people working on the same database at the same time. So, this could happen in a in a railway reservation or anything suppose you know you two people are trying to reserve a a particular a seat in a railway particular you know right train. We do not want two people to access the same seat to be alerted to two people. We do not want the same you know, but alerted to two people. So, it locks two processes from accessing the same location so that it does not happen. How is it done in a typical OS environment? Simo4 is used. So, when a particular database is there suppose assume that this is a DB 1 I will call one Simo4 I will you know as a programmer as a application programmer of this particular database surface I will say S 1 is a database you know Simo4 which is to be acquired before any process does anything with the database. So, this is a discipline that I am insisting on for the processes to adhere to so that they do not do any changes to the database simultaneously. So, it is a kind of a lock ok entry lock it is like key is given only to 1 person at a time. So, S 1 is some entity it is a database ok it is another data variable which is OS specific and database is your own data and then you are trying to tell any process using this should first acquire something what I mean by acquiring I can say that whenever a process comes and access this S 1 ok this is a Simo4 it will look for whether it is free or not whether is it free what I mean by free is suppose this has a variable inside that and then if it is 1 I call it is free then what I do when this process reads this value and it finds that it is 1 it will write back 0 into it to say that it is no longer free ok. Now, assume P 1 has come first and then it was saying that this Simo4 is 1. So, it has taken the Simo4 that means it has taken the value which was there in it copied into its own local register somewhere and then it has written 0 into it. Now, what happens P 2 comes it will ask for the Simo4 and then it is 0 now. So, it will be blocked this process will not continue with the execution it will be blocked waiting for the Simo4 to be free. Now, what happens P 1 comes in it does some operation with the database and then it has to remember to come on release it again ok that means what it will write back 1 and then make sure that it is released then the waiting process will come back and get the Simo4 and then go into the Simo4 database. So, this is the set of operations to be performed for acquiring a Simo4. So, how do we implement it in a processor? So, processor need to support it why because when a process particular process is reading the value Simo4 value it may see that it is 1 and then it may think that ok it is free and then it will say that ok I want to write back 0, but by the time if the processor is interrupted or a memory is access is given to some other process processor or a process what will happen is that will also read this value as 1 and then it will think that ok it is Simo4 is available and it will also write the 0. So, what happens now 2 processors assume that that Simo4 is free and then they get confused or there will be a you know confusion or chaos in the while they enter the database ok. So, to prevent it this swap instruction is done. So, that when any process sees that it is 1 it immediately make sure that it is written with a 0 value before anyone can access it to find out that if they had 1. So, if that is prevented then this kind of a confusion may will never happen right. So, that is what is achieved by using this instruction because it needs some help from the Simo memory also as well as from the processor. So, this is what is back with a swap instruction ok. So, assume that this is a precondition 1000 is the address and then R 1 has having a 0 0 value. Now, initially it is exchange R 0 is having what happened 1000 is at 1000 1 is having a 1 is stored. So, when the swap instruction is executed R 1 becomes 1 because that 1 has come to these 2 have been swapped ok 0 has come here and 1 has come there. Now, this is acquiring a Simo4 and releasing a Simo4 is doing the reverse of that ok again you do the same thing what happens is if they get exchange and then the reverse of whatever happened is. So, 1 comes back to this memory and then 0 is gone back to 0 R 1. So, this is what is the use of the swap instruction ok. So, this is what I am explaining Simo4 is acquired by swapping the value and then memory is made 0 and the value which was there inside was stored into a register and then it is released back by setting it 1 ok. So, the critical region what I call is it could be a part of a code or it could be a part of memory which only one process can access at a time ok. So, I hope swap is understood and the Simo4 and where it is used is understood ok. So, let us go into next one one small quiz ok. Take a small break read through this and then find out which one of the options are correct only one option is correct please choose the one ok welcome back. So, all of you made our thought over it let us see what is the correct option. So, option B is the correct one. So, as I explained to you it is not the single load or store happens it is a multiple load and multiple not multiple load one load and one store happens. So, the number of ah cycles spent on load and store will be there in this instruction also only thing is there happening together. So, it will take more cycles than a single load store the single load is only a one load operation or a single load store operation, but here we do both load and store. So, it will be a two cycles involved in it. So, let us see now what is the timing involved in this ok this we are all already familiar with this. So, I will a little bit rush to it. So, you know that this is only a sequential access because of instruction gets getting access. Here there is a what happens there value which is in R n base register is loaded into the address register for memory cycle to start. So, that takes an internal cycle here, but at the same time on instruction also getting fetched. So, this is the I S instruction. So, this is the place where the swap is getting executed. So, initially I told you read happens ok how many cycles it will take is it non sequential sequential by now you should be very clear it is non sequential and then what happens here? Here R m is getting written into data out register and here write cycle happens here ok. So, though it is a same address one is read and one is write. So, memory takes the same non sequential cycle time and then once the value is written out the value which was in data in after this memory read gets copied into R d because it assumes that R d R m could be the same register. So, it delays over writing the value I will mention the temporary register if you recall that is nothing, but data in register it could be ok. So, the value which comes in sits in data in it does not go to the register directly until this data write happens after that it is copied into R d. So, this is a something to do with the internal operation the internal cycle happens. So, total time taken will be one sequential cycle and two non sequential cycles and one internal cycle this is what a swap instruction takes ok. So, if it happens to be same register also the same thing happens the data in register holds the value in between before the transfer happens. So, this is what you will be writing in case if it is a same register ok I hope you understand this very pretty well. Let us go into a another concept which is something to do with the status register related operations. So, by now all of you are aware what are mean by status register is nothing, but our CPSR ok. So, why is it treated separately? If you recall status register is something different from the internal data general purpose register because it is meant for maintaining conditional codes and more processor mode and then interrupt flags and all those things right. So, to perform any operation with that that means, to transfer the content to any other memory location or something you need to first bring that status register into a register a general purpose register and then transfer it to memory. So, these instructions are meant for that operation. So, how do I differentiate MRS with MSR? It is very simple it is like ARM processor typical convention ok move MS move ok MS nothing, but move R equal to s that means, status register is moved into register if you use MRS ok MSR is a reverse of that. What happens a register the status register is the general purpose register is moved into status register ok. So, here R and S means what this is CPSR or SPSR ok you know what they they are this is current processor register and this is a saved processes status register this happens in a privileged mode and this is in a user mode right and R means any other general any general purpose register ok. What you have from R 0 to R 15 they are all called general purpose register. So, so this is basically this instruction helps you in exchanging that information. Now, only for MSR there is one more option available that means, when you are copying ok a register content into status you can do or on immediate constant and 8 bit immediate constant can also be copied into a status register ok. So, these two formats are only meant for MSR that is not true with the MRS ok this is only is either register to status register could come from register to status register or it could come from immediate constant to a status register. Though the instruction is called MSR the value may come from immediate constant based on the usage of the instruction ok ok good. So, let us see when it is necessary to save or modify the contents of either CPSR or SPSR of the current mode those contents need to be first transferred to a general purpose register ok. After that you can decide to either operate on that or you could save into a memory. The selected bits ok modified and then you can written back write back the value into a status register. Suppose you are interested in changing the particular bit positions in the CPSR you cannot do some and CPSR ok you cannot use CPSR as one of the operands in your register you might have noticed in any of the register any of the instruction format there are 4 bits reserved for R 0 R R D ok R N R M 4 bits are only used with 4 bits in the instruction how many registers you can represent from R 0 to R 15 only you can represent. So, where is the space in this 4 bit to indicate that I am interested in doing a CPSR transfer. So, you cannot use CPSR in any of the data processing instruction please remember. So, that is the reason why they have a separate instruction to mention the CPSR. So, that you transfer that into one of the general purpose register and then you can use any of the data general purpose and data processing instructions to operate on the content and then write back that value into again the status register ok good. So, MRS MRS are used for exchanging the status register with the general purpose ok. Let us see what you do you have the saving is done by using an MRS followed by a store what I mean by say suppose you are interested in saving the content of the CPSR into memory ok you cannot do it using a data transfer instruction for the same condition that I mentioned to you ok. So, CPSR should be brought into one of the registers and then that should be brought into memory. So, you should do a MRS why MRS because status to register MRS and then the store similarly if you want to restore some value which is stored in memory into CPSR what you do you bring into a general purpose register and then take it to CPSR. So, this is a two steps process similarly when you are saving you bring into general purpose register and then that then general purpose register you put it in memory this is memory this is our CPSR yes this is our general registers understood very good. So, sorry ok. So, it cannot be directly saved into memory or active. Now all of you must be familiar with this by now. So, if you recall the CPSR register is written to 4 keys 8 bits each they are called flag spot this is called flag this spot is called status and this is extension and this is control. As far as ARM 7 TDMA is concerned this is unused and this is reserved also please remember the grade portion is reserved that means you are not supposed to write anything into this. If you do so, you are doing it at a risk of you know preventing a your program made to run on future processors ok. The future processors may and this not may it is already future processors have used lots of bit positions in this location and in ARM 7 TDMA if you try to do something into this location as far as you are running your core in this processor there is no issue because there is absolutely nothing is important is there, but if suppose you have trans you know compiling the same assembling your same code for ARM 9 or ARM 10 or ARM 11 they are core compatible. So, it may you know get assembled properly your assembly written, but if you are writing something into that it may be reserved for some particular purpose in those processors and you may have a problem. So, actually you are you are supposed to take care that you do not use the reserved location of any registers all this it is a it is not true with only this particular place all this ok please pay attention to that it will you have to be cautious about that. So, now now you know this bit position this is the mode whether which mode user mode system mode or comparison mode this is term mode which we will cover later and this is the if it is set it means that they are intercept disabled. So, this is the condition flag which you are all familiar. So, if you want to access any of this part of this 8 bit you can do it using these kinds of special constants ok strings special strings. So, what does it mean c means control field which corresponds to this tau you know lower 8 bits of the CPSR or SPSR whatever I say is true for CPSR and SPSR because basically this particular content only is stored in the SPSR right then you are doing a mode change. So, those saved processor status register also can be updated upon using thiscommands. So, the MSR and MRS instructions you can give mention this 8 bit values like this. So, why they have done this kind of 8 bit value it is again the same reason that I have told you for constants the 32 bit instruction if you want to save some 32 bit value you need another 32 bit of constant to be mentioned which is not possible with one this single instruction which is of 32 bit wide. So, if you recall I mentioned that you can mention an 8 bit constant along with the MSR or MRR MSR or MRS. So, this 8 bit constant can only maximum change the value of a 8 bit value in the CPSR or SPSR. So, that is the reason you are given an option to choose one of this field to write it from a register or it could be from a immediate constant ok this is proved with immediate constant also you could use any of them to change the particular field of a status register understood very well. So, MSR is used to transfer contents of general purpose register to various fields in the CPSR which is a same statement I am telling, but you can access these individual fields using these strings which are this is strings are understood by the assembler please remember it could be a small word or a capital letter no problem, but it should be followed by a underscore and a letter one of this ok. Now, this format could be with the immediate constant or you can mention a register and this is the format of this instruction where field mask is derived from what you have given as a CPSR fields ok. So, I am not going to detail of how the processor is maintaining it, but only remember that based on the field you have chosen the processor understands which are the particular fields you are interested in modifying the value ok. What I mean by that let me explain you assume that you are usingMSR what does it mean you are changing the you are loading the particular register value into your status register ok. So, a register may have a 32 bit value correct may it is not may it is actually. So, the register is having a 32 bit value which is r m. So, it is split into 4 8 bits and your CPSR also has 4 fields I mentioned what are they this is conditional field ok,this is flags ok this is control C extension and what are the other fields ok. So, you know the 4 fields which are there in this you can mention any of this fields in your instruction. So, you could even combine those fields into one instruction ok I will explain that in the subsequent with an example. So, you can change any one of them you can choose I am interested in changing this and this or I am interested in changing only this and this. So, based on that you can decide to put one of these fields C X or S or F ok. So, you can say CPSR ok and then say I am interested in C and X ok. That means, it will only modify the C is control fields. So, this field it will change and then you can mention X also underscore C X that means, it will change the extension bit also. That means, given a register it will choose those particular 8 bit value and then copy it into the status register ok. So, you can in fact, say that I am interested in changing all of them that is also allowed. So, that is why they have provided, but only ok you can mention a unique value in those register and then transfer it, but please remember in ARM 7 TDMA you are not allowed to change this contents. This status and extension fields are not used in the 7 TDMA processor ok. So, I hope this is clear to you. Let us see and take an example so, that you understand exactly how it happens. So, should only write those fields that I can potentially change ok. Again you please remember some of the mode registers are not modified by a particular mode. So, in a user mode you cannot change the mode register mode field of the register that is to be precise I will go back please remember this mode bit cannot be modified in the user mode. You can change these bits and even this term mode you cannot change it using this instruction. So, you have to make sure that whenever you are changing the bits only those bits are modified in the values and put in R0 and then you are storing them into CPSR. Otherwise you are likely to get unexpected results ok that is why I am trying to say here. Let us see one small example I prefer you take a break now and then try to look at this instruction and then come back and see what the explanation whether you are able to make sense out of this ok. So, welcome back. So, I hope you already understood what is happening here. These instructions are all executed one after the other. What happened here we are loading the CPSR into R0 please remember when you are using the MRS instruction to access the CPSR you are not mentioning the field it is only when you are writing into them. So, here you can say I am interested in reading a CPSR or a SPSR based on which mode you are running this instruction from and it will copy that value into one of the general purposes you mentioned here. It now CPSR value has come here what are you trying to do here not you I am trying to do I am sorry. So, what I am doing I am trying to and the value in the lower LS byte ok. So, I am interested in only the lower byte. So, F of I am doing and in it with that that means, all the values which I read from R0 is maintained here all this value whatever was earlier there in copied from CPSR is made 0. So, R0 is holding that value now ok. Now, I am using R1 here and then trying to do a m v n with the 1 F by now you are familiar with m v n what happens whatever is given here is inverted and then copied into R1 that means, the lower 5 bits 1 F ok lower 5 bits are set to 1 or rest of it is all 0 ok. So, only lower 5 bits that means, which corresponds to the mode bits of the CPSR. Now, what are I trying to do here mean I am trying to and R0 with the R1 ok and then getting it here into R0. So, effectively I have I am extracting only the 1 F portion ok because 1 Fthe what has happened is 1 F is 0 and then if you and it with the rest of it is 1. So, the rest of it is preserved only this is forced to 0. So, what you see in R0 will be ok earlier you had this content which you read from this assume that suppose you have read this value ok this 8 bits were preserved suppose ok this 8 bits were read from CPSR and after this operation this is what you are having it in R0. Now, I am doing a anding it with all once here and then only this 5 bits I am anding it with the 0 ok. So, what I am exactly doing is I am making sure that the top whatever 5 bits were there whatever was the previous content I am making in them all 0 and then I am preserving this value. So, this happens to be 0 0 1 and then top 5 bits are made all 0s ok this is what is the RF content or 0 content. Now, after that I am oring it with 1 3 that means, I am interested in 1 3 is what 1 0 0 1 1. So, this 5 bit 1 3 is corresponding to this value which I am oring it with that means, now I am changing the value for only this 5 bits keeping this content same ok. Now, I have got a new content for the lower byte which the top 3 bits are the same ok what was there originally and then this bottom 5 bits have been modified to represent a maybe another mode and then which happens to be a supervisor mode and then I am writing R 0 C here C I am mentioning here CPSR C that means, I am interested in only modifying the lower byte of the CPSR and I am using MSR. So, now what happens is the mode is changed from originally whatever was the mode assume that you are in a privileged mode. So, that you are able to change the mode bit it will go back to a supervisor mode now because I am changing the value to 1 3 understood what I am trying to do is I am getting the value into R 0 making sure only I am interested in top that byte and then in that I am only changing the lower 5 bits with a new content and then writing it back I am making sure that the top 3 bits of the lower byte are not modified suppose in interrupt flag or thumb mode or whatever was the status I am maintaining the same thing and getting it back ok writing into the CPSR this is what is done by this particular code and I want you to write such a code it will become similar with this ok. So, what are the usages as a part of the read modify write read it modify it and write back CPSR is it could be a CPSR or a CPSR. So, one more thing you should remember you know in this little bit I will explain you later the when you are changing the exception mode it could land it into multiple exceptions happening from the same ok one exception calling the same exception again come inside. So, in those kind of situation you may have to save it in the stack ok I do not want to go into the detail now because it is out of context let us talk about that when exception happen right now take it from me that when nested exceptions happen you need to save the value in SPSR into stack and then that is what that for that also you will be using the MRS and MRR instructions ok and even to save process states context is I mentioned even for that operation you will be doing this ok with this we are coming to the end of that ok. In the immediate form of MRR can be used to modify the PSR, but make sure that you do not disturb the previous contents or other contents and if you are modifying all the bits which are caught up as it analogated you are likely to get into trouble. So, do not do that do not modify with the bits which are not supposed to be touched by you failure to observe this rule you will get a unanticipated side effects when you are moving to future versions of ARM. When I say future version if your code is compiled or assembled in this case assembled for a future versions you may land into trouble the the program will not work properly. So, portability will be an issue if you do not take care of this and then other instruction other restrictions you have to modify one small thing I just thought I will make a note of that the flag register if you recall the only top 4 bits are having CZNB right the top nibble of lower byte is a all I mean reserve even though they are reserved you will be allowed to change them by using this instruction ok. You are mentioning a 8 bit value though you are modifying only the bottom nibble ok in this case CPSR bottom 4 nibbles are CZNB ok. So, you are interested in only changing them, but the when you mention F the F field will indicate all the 8 bits right. So, you are allowed to change this contents also though it is part of the reserve field ok that they have given a freedom because you cannot transfer minimum you can transfer is 8 bits right. So, how will you make sure that you do not change this if there is no guarantee no you cannot do that. So, they have given a freedom to you that you modify we will make sure that it does not impact the future versions of the ARM ok that I thought I will make a note of it. So, you remember this ok you may have this question later. So, ARM will take care of not to get disturbed when you write something into this ok other than that no other reserve value should be changed. And mode also you can change only when you are allowed to change at the same time you also have to do only the reserve value. If you are using undefined values ok more bits you can remember 5 bit values are fixed you cannot write any other numbers that you wish. If you use some reserve value you will have a problem ok. And one more thing if you recall there is no S bit option here because we are doing something with MSR and MRR which is a CPSR and SPSR there is no S bit or you cannot say MRS ok there is no special word the S you cannot mention it here ok. Additional information you have to do any operation with SPSR only when that mode particular mode supports it ok you cannot do it in user mode or a system mode which does not have a SPSR register. Similarly, only privileged modes you can modify the SPSR we cannot do that with the user mode ok. And SPSR register which is accessed depends on the mode at the time of execution. Suppose you are in a fast interrupt and you are accessing SPSR it will access the particular bank of that particular exception ok. So, you you do not have to mention this underscore FI2 when you are writing the code you will be writing SPSR, but based on the mode in which that code is executed it will access the relevant bank register which is active at that moment. Similarly, a very important point is this thumb mode I will be explaining you later in the section, but you cannot modify the thumb bit using this MRFM of R instruction. So, please remember that you preserve those values because you may not know whether it is already in thumb mode or not. So, you should not change this bit ok and one more condition is R 15 cannot be used with this instruction ok. So, I want you to spend some time on this and then understand how this instruction will execute. You can take a small break 2 minutes break and then try to see how this instruction is run assume that ARM is in a system mode ok. What I mean by system mode is you are allowed to modify the mode bits ok because in the user mode you cannot allow that is why I am saying that ARM is in system mode. And then if this instructions are executed what happens you can take a break now ok. Welcome back let me run through that you by now you should be familiar with this if you are done yes here and then you are moving a 0 here could have been set and it will be true ok it will execute this instruction. So, CPSR comes into R 1 here you are moving a 1. So, this would not be true. So, this will not happen and here what are you trying to do you are trying to write the conditional flags with all values. So, you can forcibly write all 1's into C that can be. So, you can do that ok and one more thing what you are doing here is I am not mentioning only the condition flag here I am mentioning the please remember I am mentioning f ok. Let me reexam I will write so that you recall this is condition spot this is a flag spot of the CPSR. So, I am trying to modify this as well as this with a a byte value ok. So, what happens is this D 0 gets written into this and then all 0's will be written into this because this D 0 will be you know 0 extended and then it will this constant is read as a cut it a bit value and then it uses the lower byte value to copy into C bit though you have mentioned C f or f c does not matter that you are interested in changing these two flags these two fields of the CPSR. So, it does modify whichever this is the lower byte. So, it changes the mode width first and then it fills the only top CZMV flags 4 4 flags are meant R set clear to 0 ok that is what happens with this instruction ok. I want you to spend some time on this what this D 0 means this is 1 0 0 0 correspond to which mode we are changing the mode ok user mode ok corresponds to user mode. If condition field as well as mode fields need to be changed together then you can do this ok very good. So, I am done with the flags. So, I thought as a continuity we will take some more time to finish of this this set of instructions also. So, we will let us carry forward I have taken little more time than expected ok. Now, a loading constants you remember we could load some constant value into some register I told you that 32 bit value cannot be moved because of the instruction description. So, but you could use move or in the end for this if you are mentioning any constant if you recall I mentioned some instructions are there where the constant value can be rotated by some bit and then that can be reserved values can be used. So, processor does the assembler does some choosing a particular register you know instructions to based on the value that you are mentioning which constant value you are trying to copy it picks up the right instruction to do that ok because of the restriction that arm instructions are 32 bit inside you cannot mention a 32 bit constant, but it does it chooses a particular type of instruction to do the job or it could also do one more thing it can save the 32 bit constant in the memory ok 32 bit values are interested in copying suppose you are interested in copying 0 x 1 2 3 4 5 then if you say move it cannot be mentioned as a move. So, it will reserve some location in the memory and put that value there and then do a load register load a LDR means it will copy from this memory location to the register. So, it can do a memory transfer to both upon the same job ok. So, I am trying to explain you what are the things that assembler the processor support. So, there are two instructions are called pseudo instructions ok. What I mean by pseudo is this instructions are not executed as is by the processor it is understood by the assembler and then it will modify this instruction it will only know the intent of the programmer and then it will modify it to suit a particular thing that you are interested in doing ok. I will explain you what I mean by intent to do only thing is this instructions are modified by the assembler to perform the job. So, effectively you are communicating to the assembler that I want I am interested in doing this and the assembler generates multiple instruction or single instruction internally to achieve the job ok. So, let us see LDR is to load a particular 32 bit constant and load address means you are interested in loading a particular label. The label could be a part of an instruction where you are interested in loading the you know suppose there is a code ok. There is a label you have mentioned in your assembly code that means, it is referring to the particular part of the code. So, this this code can be anywhere in your code memory and then you are interested in getting the address where the code is there. So, you may say that I am interested in getting that address of the label into this register then the processor will do something to do with the PC maybe it will do perform some operation with respect to PC to get this value or it could save this constant somewhere and then load that into the register directly ok. It can perform any of those operations based on the particular usage and where you are calling that instruction from ok. It is aiding in programming. So, the process rule instruction right that means, constant to a register with whatever instructions are available. So, it can use any instructions to achieve your job it could be a PC relative it could do with respect to the PC or it cando a memory read operation. One example I will show you suppose you are declared you know you are trying to say that I am interested in copying you know I have declared two values 1 2 3 4 5 6 on this in your code and then you are saying that I want this constant to be loaded into R 0. From this you can make out that 32 bit value cannot be given in this instruction. So, what exactly the processor does it actually changes to a load register into R 3 with respect to PC. So, it generates some offset with respect to the current PC and then tries to access this constant which is there in the memory. Assume that this code is given in the assembly code in the same sequence it is as it is mentioned here this is two these two are two instructions ok. Assume this is at the location 1000 ok for a change 104 this instruction is there 108 this instruction SWI is there and 100 and C or not C this word is told. Please remember code and data they can reside in the same memory because we are one home in architecture we are having and this code and data memory can be same they can be together. Only thing you have to make sure that you do not give R 15 the PC to point to the data area which you have reserved. So, 103 and then this will be 110 ok. Now, the processor when it is you know the assembler when it looks at this instruction it is generating a particular instruction with respect to PC it computing the offset. So, you might you may remember I have mentioned the instructions which refer with respect to PC ok LDR instructions where you can mention R 15 as one of the operands. So, you have to now think ok where the PC will be when this instruction is executed bring in the pipeline into your mind where the PC will be pointing at and then how much of offset it should mention with respect to PC to access this value which is there in the memory to be brought into R 0 ok. I want you to just think it over rather than me telling you to bring. So, here offset of the PC offset with respect to PC is computed and that constant PC is going to be constant because when the assembler is assembling this particular set of instruction it knows that this instruction for one after the other. So, it it will be placed together in the memory. So, it can always compute the offset with respect to PC where this constants are residing in the memory and then it will be copying that into R 0. Please remember this dot word is a you know notation used for loading this particular constant in that particular address after this SWI this is stored in the memory ok. If you look at the memory if I show the code memory you will see the instruction for LDR R 0 here and then R 1 LDR is there and SWI is there and this constants are stored in this location ok in the memory just for a clarity I am saying and all of them are 22 bit wide. So, the memory. So, if this is 100 you can know that where these constants are residing in the memory and then with respect to PC can you compute the offset ok. So, what is the offset value ok you can even take a small break and then find out what is this offset is going to be ok. Welcome back if you have thought over and if you remember the pipeline if when you are executing this instruction where the PC will be PC would have accessed already this instruction and then it would be would have address access this also. So, it will be actually wherever this instruction is ok plus 8 will be the PC value ok then this instruction is getting executed please remember the pipeline again ok 3 stages when it is in execute stage this particular instruction already PC has fetched the instruction to down the line that means, the address would be 108. So, any offset that is then performed with respect to PC should accommodate or account for this particular change in the PC value. So, it is just from this location it is plus 4 is not it this particular word is stored. So, the offset here will be 4 plus 4 or minus 4 it is a plus 4 because it is in the increasing order. So, wherever PC is plus 4 is what this address is stored. Now, tell me what is the offset for this instruction once the PC moves here ok when it is executed executing this instruction this PC also would have moved one ahead right please remember it is accessing this memory, but it will not be executed ok. Now, PC will be pointing at this location ok and again this word will be plus 4 from there. So, here also the offset will be 4, but why I have put this word just below this SWI because SWI make sure that the control goes back to the simulator this is very specific to our ARM simulator that we are using for our course. So, there is no harm in declaring some data elements here. So, you would not have any problem ok. So, 4 will be the answer ok remember that code and data can decide together because of one I am an architecture ok. So, ADR example ADR is it is copying the address of the variable I am declaring a num 1 using this particular simulator various simulators or assembler may have different convention. So, you have to remember that accordingly. Suppose if you are interested in doing this what exactly this ADR instruction does is it shows the address of the variable where it is declared please remember it is not accessing the content of the variable it is declared here whatever is the address here that is getting stored into R 2 whatever is the address of num 2 it is stored into R 3 again this will be with respect to PC again because it is coming one after the other. So, the assembler when it when it looks at this particular instruction it actually generates some PC relative accessing in fact it is it will generate an add instruction to say that whatever the PC value here add 4 and then get that value into R 2 ok. So, that is what it does why because this addresses are in the PC related to PC PC is the program counter I am referring to. So, this instruction has an access to PC at this moment. So, it can do compute the address add to the address with respect to PC and then comfortably load into R 2 ok. So, to get the address of a variable the assembler might change the pseudo instruction at address load with the PC relative instruction. So, I want you to try this out exactly the same way in a in our simulator that try a sim ARM sim char you know simulator and see decode the code up code and then understand what the exactly the instruction being generated ok that will give you a better clarity. So, I hope all of this is very clear to you I I want you to try out all these things in your lab session to understand the concepts ok. So, there are pseudo instruction it will check if the given constant can be represented by a operand to immediately otherwise it will use different instructions. So, move instruction will be faster see assembler is deciding what to do. So, it could do a move instruction or add instruction rather than doing a LDR instruction. So, based on the constant that you have mentioned as a part of the LDR or ADR instruction the assembler is free to choose whatever instruction it wants to perform the job. So, that is what is mentioned here ok. So, some of these constants are 12 bit constants which can be represented using the instruction that I mentioned in the session 7 ok. If you do not remember please go back to that and read that material and to understand how this instruction can be executed. So, with this we have come to the end of the session. So, I hope you are clear with both these instructions and all the ways of different ways of using them and only when you try out try this out in your simulator and understand it you would not have the hang of this please do so and happy to copy you wish you all the very best take care.