 Welcome to the session on Earth Synchronous Counter in Digital Design. At the end of this session, students will be able to design an Earth Synchronous Counter. Let us see what is counter. Counter are circuits that cycle through a specified number of states. A counter is a device which can count any particular event on the basis of how many times the particular event is occurred. In a digital logic system or computer, the counter can count and store the number of times any particular event or process have occurred, depending on clock signal. For example, in up counter, counter increases count value as per the rising edge of the clock pulse. Counter can follow the certain sequence based on our design like 0, 1, 2, 3, etc. They can also be designed with the help of flip-flops. The types of counters are synchronous counters and Earth Synchronous counters. Now Earth Synchronous counters, whereas the flip-flops do not change state at exactly the same time as they do not have a common clock pulse. Earth Synchronous stands for the absence of synchronization, something that is not existing or occurring at the same time. In computing string, Earth Synchronous stands for controlling the operation timing by sending a pulse only when the previous operation is completed rather than sending it in regular interval. It is also known as a ripple counter as the input clock pulse ripples through the counter and cumulative delay is a drawback. Those flip-flops are serially connected together and the clock pulse ripples through the counter and Earth Synchronous counter can count 2 to the power n minus 1 possible counting states. For example, 2-bit ripple binary counter, a ripple counter is an Earth Synchronous counter where only the first flip-flop is clocked by an external clock and the circuit shown here 2 jk flip-flops to implement a 2-bit ripple binary counter and it counts towards up and the number of states are 2 to the power 2 is 4. Now the operation of Earth Synchronous counter here, the clock input is only connected for the first stage or we can say the first flip-flop. The clock is applied to the clock input of only first flip-flop which is always the least significant bit. The second stage is triggered by the output of the first stage because the propagation delay of flip-flop. The second flip-flop is triggered by the output of the first flip-flop because of the inherent propagation delay time through a flip-flop and the transition of the input clock pulse and the transition of the output of first flip-flop can never occur exactly the same time. In next step, the transition of input clock pulse and given output will never occur simultaneously. Therefore, the 2 flip-flops are never simultaneously triggered. So the counter operation is Earth Synchronous. Now here we will check it out the state table of 2-bit Earth Synchronous counter and it will count from minimum that is 0 to maximum 3 that is it adds as a up counter. Note that for simplicity the transition of Q1, Q2 and clock in the timing diagram which we will see in the next slide this is an Earth Synchronous counter. Actually there is some small delay between the clock, Q1 and Q2 transition. Usually all clear inputs are connected together so that a single pulse can clear all the flip-flops before counting starts. The clock pulse fed into flip-flop 1 is rippled through the other counters after propagation delay and the 2-bit ripple counter circuits above has 4 different states each one corresponds to a count value. Similarly a counter with n flip-flops can have 2 to the power of n states and the number of states in a counter is known as its mod number thus a 2-bit counter is a mod 4 counter. Here in the waveform diagram or from the timing diagram we can observe that Q1 changes state only during the negative edge of the applied clock initially the flip-flop is at state 0, flip-flop stays in the state until the applied clock goes from 1 to 0. As the jk value r1 the flip-flop should toggle so it changes state from 0 to 1. The process continues for all pulses of the clock. Coming to the second flip-flop here the waveform generated by flip-flop 1 is given as a clock pulse. As we can see the timing diagram when Q1 goes transition from 1 to 0 the state Q2 changes. Now in the applications of counters very first one is digital clock the digital circuit which is used to count the number of pulses are formally called the counter or we can say the timer counting means incrementing or decrementing the values of an operator with respect to its previous state value. Second frequency counter digital counter function as frequency divider since the divide the input control clock frequency by the modulus of the counter the binary counter ok the next one is binary counter the number of output bits of a particular binary counter is equal to the flip-flop stages of the counter a mod 2 n counter requires n stages or flip-flops in order to produce a count sequence of the desired length and the first stage of counter is the LSB that is least significant bit and the last stage of the counter is the most significant bit design of 3 bit of asynchronous counter so please pause the video and write your answer here in answer in the 3 bit triple counter 3 flip-flops are used in the circuit as n values is 3 the counter can count up to 2 to the power 3 is equals to 8 values and the circuit diagram is shown here and the 3 bit mod 8 or synchronous counter consist of 3 jk flip-flops or all propagation delay time is the sum of individual delays initially all flip-flops are reset to produce 0 and the output condition is q 3 q 2 q 1 equals to 0 0 0 when the first clock pulse is applied the ff 1 changes state on its negative edge therefore q 3 q 2 q 1 equals to 0 0 1 on the negative edge of the second clock pulse flip-flop ff 1 toggles its output changes from 1 to 0 this being negative change ff 2 changes state therefore q 2 q 3 q 2 q 1 equals to 0 1 0 similarly the output of the flip-flop 3 changes only when there is a negative transition as its input when 4th clock pulse is applied count sequence is the output of the flip-flop is a binary number equivalent to the number of clock pulses received here and the output conditions are as shown in the truth table also in the waveform diagram here the output waveform of q 1 is given as clock pulse to the flip-flop of first jk when q 1 goes from 1 to 0 transition the state of q 2 is changed also when q 2 goes from 1 to 0 transition the state of q 2 is changed and the output of q 3 is the MSB note that output value of q 1 are considered as LSB and q 3 are considered as MSB counter is a device which stores the number of times a particular event or process has occurred a ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock all subsequent flip-flops are clocked by the output of the preceding flip-flop asynchronous counters are also called ripple counters because of the way the clock pulse ripples it way through the flip-flops these are my references which I used thank you.