 Hello, Myself Sunil Kalshati, Assistant Professor, Department of Electronics Engineering, Walchan Institute of Technology, Sallapur. Today, I am going to discuss Programmable Unijunction Transistor, PUT, Learning Outcome. At the end of this session, students can describe construction, characteristics and operation of Programmable Unijunction Transistor, PUT is four layer PNPN solid set device. It is also called as a Complementary Silicone Controlled Rectifier CSR. In PUT, gate is directly connected to the sandwiched N type layer. Its name Programmable UJT, just because its characteristics and parameter have much similarity to that of Unijunction Transistor. The PUT is an improved version of UJT, figure one is the internal diagram of PUT. Here the gate is connected to the N region and figure two is the PUT circuit symbol, why PUT is called as Complementary Silicone Controlled Rectifier. Generally, in SCR the gate is generally connected to the P region that is near to the cathode. But in PUT the gate is connected to the N region that is why the PUT is called as a Complementary Silicone Controlled Rectifier, PUT biasing circuit. Here the resistive divider network R1 and R2 access a voltage divider network. This is used to set ETA and standoff voltage and set the specific gate voltage. PUT is called Programmable because the parameters like intrinsic standoff ratio ETA, peak voltage VP can be programmed with help of two external registers RB1 and RB2. In UJT the parameters like peak voltage ETA are fixed and we cannot change it. The PUT is similar to SCR except that its anode 2 gate voltage can be used to turn on and turn off the device. In PUT gate is connected to N region adjacent to the anode but in SCR gate is connected to the P region adjacent to cathode. Anode gate PN junction controls on and off state of the device. PUT is useful in various industrial circuits like time delay logic circuits, oscillators, gate control circuits for SCRs. 6027 and 2N6028 are the most common type number of PUT. Now specification of these two maximum rating 200V 1A, On-State voltage 1V, High-peak output voltage 11V. The gate terminal of PUT can be biased through the voltage divider network as shown in figure 3. The R1 and R2 acts as a voltage divider network, apply the voltage divider rule so VG is equal to R1 upon R1 plus R2 into VBB. Here R1 upon R1 plus R2 is the ETA, ETA is the intrinsic standoff ratio so VG is equal to ETA into VBB. Then anode voltage exceeds the gate voltage by approximately 0.7. The PN junction is followed by a strip and PUT turns on. The PUT stays on until the anode voltage fall back below this level then PUT turns off. The characteristics of PUT. The characteristics is divided in three regions, 0 to VP, this region is the cutoff region. In this region PUT remains in cutoff region, VP to value point voltage this region is represented by the negative resistance region. In this region the PUT is in conducting state and here the current encourages rapidly and the device operates in negative resistance region. And here after value point the region is the saturation region. The characteristics curve for the programmable unijunction transistor is similar to UZT. This is plot of anode current IA versus anode voltage VA. The gate lead voltage sets programs the peak anode voltage VP. As anode current increases the voltage increases up to peak point. Thereafter increasing current results in decreasing voltage down to the value point here. PUT as a relaxation oscillator this is the one of the important application of the PUT. Initially assume that PUT is in off state apply the VBB. When VBB is applied the capacitor starts charges through the VBB RC and at the same time the PUT remains in off state because the voltage across capacitor is less than peak voltage and capacitor charges exponentially. These are the voltage across capacitor waveforms. As long as capacitor voltage is less than peak voltage the PUT remains in off state. When the voltage across capacitor crosses the peak voltage the PUT conducts and once the PUT conducts the current flows through the capacitor PUT and RK and the pulse is produced across RK and at the same time the capacitor starts discharges through the PUT. As long as capacitor discharges PUT the PUT remains in on state. When the voltage across capacitor becomes less than value point voltage PUT turns off and again the capacitor starts charges through the supply voltage RC and the process repeats. These are the voltage across capacitor voltage across this is VK and this is the gate voltage. At the instant of triggering PUT the anode voltage is greater than gate voltage. The peak voltage VP is equal to VC is equal to voltage across capacitor. Here the capacitor charges exponentially therefore the equation of voltage across capacitor VC is equal to VBB into bracket 1 minus e raise to minus T upon RC this is nothing but peak voltage. After solving this VBB minus VP is equal to VBB into e raise to minus T upon RC therefore e raise to minus T upon RC is equal to VBB upon VBB minus VP take the natural log of both side and solve the equation T upon RC is equal to log to the base e VBB upon VBB minus VP the FUT is equal to RC into log of to the base e VBB minus VP the term VBB minus VP is voltage across R2 is given by VBB minus VP is equal to VBB into bracket RB2 upon RB1 plus RB2 FUT is equal to RC log to the base e into bracket 1 plus RB1 upon RB2 advantages of PUT over UGT in case of UGT eta is fixed 0.42 0.8 in PUT eta is depends upon RB1 and RB2 therefore PUT offers better choice for eta PUT has high forward conductance so it can provide high peak current pulse even with low value of capacitor in relaxation oscillator PUT has fast rise time which allows faster rise current provides healthy output pulse as compared with UGT why PUT is used to trigger high current SCR as we know as compared with UGT the forward conductance of PUT is high so effect of this it produce high peak current pulse because of this reason PUT is used to trigger high current SCR how to trigger SCR using PUT this is the circuit diagram to trigger SCR using PUT here in this circuit when VBB is applied the current flows through the VBB RTCC as long as voltage across capacitor is less than peak voltage the PUT remains in offset and pulse is absent when the voltage across capacitor crosses peak voltage PUT conducts and once the PUT conducts the capacitor C discharges through the PUT and it produces the current and that current acts as a gate ring current for the SCR in this way the circuit is used to trigger the high current SCR these are references thank you.