 Welcome to the presentation of the STM32H7 Basic Direct Memory Access Controller, or BDMA. It covers the main features of this module, used to provide high-speed data transfer between peripherals and memory, as well as from memory to memory. The Basic Direct Memory Access Controller is designed to efficiently support data transfers from peripherals and memories when the CPU enters C stop mode with D1 domain or D2 domain in D standby mode. The DMA controllers are fully configurable and manage hardware and software priorities between channels, as well as data transfer modes. The BDMA controller has seven channels in total, each dedicated to managing memory access requests from one or more peripherals. Each channel has flexible hardware requests or software triggers. The channel software priority is programmable and a hardware priority is used in case of equality. Channels are independently configurable. Each channel has its own data format, increment type and data address for both source and destination. Independent channel interrupt flags allow triggering of half-transfer, transfer complete and transfer error events. A global flag is also available to facilitate the software efficiency. In case of an error, the faulty channel is automatically disabled without any impact on the other active DMA channels. For each channel, the source and destination data size format is independently configurable for 8, 16 or 32-bit packets. The source and destination addresses and pointer increment are also independently configurable. The transfer data size can be pre-programmed up to 65, 5, 35. Circular buffer mode is available to support a continuous flow of data. The source and the destination addresses and the number of data to be transferred are automatically reloaded after the complete transfer. Memory to memory mode allows transfers from one address location to another without a hardware request. Once the channel is configured and enabled, the transfer starts immediately. When data is transferred from or to a peripheral, the hardware request coming from the selected peripheral is used to trigger the data transfer. Once the transfer is completed, the request is acknowledged. BDMA peripheral requests are connected to the DMA MUX2 request router. It enables a flexible request mapping for each channel. Each BDMA channel is designed with this group of interrupt events. The half-transfer interrupt flag is set when half the data has been transferred. The transfer complete flag is set when the transfer is complete. The transfer error flag is set when an error occurs during the data transfer. The global interrupt flag is set whenever a half-transfer or a transfer complete or full-transfer event occurs. The BDMA is active in run and sleep modes. DMA interrupts will wake the STM32H7 from sleep mode. In stop mode, the BDMA is stopped and the contents of the DMA registers are retained. The BDMA is powered down in standby mode and the BDMA registers must be reinitialized after exiting standby mode.