 So, till now in this course we have been looking at combination circuits before how the combination circuits are a great use in CMOB, how the delay is estimated, now let us look at another platform circuit, sequential circuit with a very individual part of individual design. So in this lecture we will see how sequential elements are used in sequencing, we will see two major types of sequential elements latch and flip flop, we will see how they are designed using CMOB, we will look at the delay of the delay parameters of a latch and flip flop course, now latch and flip flop both have the concept of match delay and win delay, we will look into that, now wherever there are sequential elements there is a clock, the clock comes into picture, so we will look at the clocks queue, how important it is during the analysis of the delay, we will touch upon time borrowing and we will see a bit about two phase stopping, the time borrowing the delay concepts are just touched upon in this lecture, they will be explained and used in detail will be needed 4 and 5 that is during synthesis and timing analysis, but here we will lay down the basis of these concepts. And then let us look at what is sequencing, why do we need it in circuits, now the major difference between combination and sequential logic is that for a combination logic the output, current output depends only upon the input state at that moment, so if you change the inputs after some delay in an end delay of the CMOS, the output will reflect that change, for example for an AND gate it will go the input from 1, the output is 1, if you change one input to 0, the output will go to 0 after some time with amount of delay. A sequential logic on the other hand the output depends not only on the previous inputs but also not only on the current input state but also on the what the input was before, so this that is why sequential logic is used to separate the previous current and future elements, these the outputs of sequential elements are called states or tokens, there there are two very famous examples here, one is often of a finite state machine and there is a pipeline, so if you go back to your basic digital design remember what an FSM was, an FSM is a set of sequential circuits representing a particular state, now when the these sequential circuits move for one state to other depending on what input we apply, so a finite FSM circuit something like this you have a bank of flip flop bank of resistors and the output of these resistors depends on inputs and also on what are what all outputs are going, so it depends not only on the input state with the input state but also on what input was what what the state of this bank of resistors was previously, as compared to FSM there is a circuit like pipelining where the data will just skip through different stages, so let us say this is state 1, some processing happens during this phase with combination of it, this is state 2, this is state 3 and so on, now the question arises why do we need sequencing at all, so let us say if the tokens or if the states of the terminal circuit move at constant speed, so all the parts in your design then there is no need of sequencing, because the sequencing is inherently being taken care of, for example in cyber optics the line pulses which are equivalent to tokens there are sent down in optical cable, the design itself guarantees that the next pulse is sent before the first peak is at the end of the cable, it will not happen that the input pulses will not reach the end of the cable out of order, so this is guaranteed by the nature of the design itself, there is no need of a separate hardware to separate these pulses, although the physical limitation posed by the desets of light dispersion, so it is a minimum time between pulses but otherwise no extra hardware is required, you can say this is equivalent of the 5-minutes circuit, in case of digital design this type of internet capability is not there, that is why we need extra hardware to make sure that the tokens transfer from input to output right in order, so what this means is that we delay the fast open, so that we do not have to slow down, this is this might be a bit confusing in theory but we see a few of practical of this and there is one more course of computer architecture which deals very extensively to this, the pipelining inside a CPU design, so that is what will help in making this story very clear why sequencing is required. Otherwise as we go on and see examples and synthesize them we will start appreciating this convention, now obviously when we use any sequential element like a clip top or latch to delay fast open, so that they move to exactly one stage cycle it will add some delay, some delay to the slow ones also because they have to be also the clip top also they have to be added to slow open, now this compare, if you compare two circuits one is only comprised of combination delay and other is comprised of combination plus sequence delay, so one where combination of sequential elements are used will be a bit slower than the earlier one, this type of overhead is called sequencing overhead, some people also call this stalking overhead because when we have sequential elements to design we also have to add the drop but it also applies to asynchronous circuits too, we might encounter one of the examples later, this is the inevitable side effect of mentoring sequence, when you want to maintain sequence you have to make sure that the faster tokens do not overtake with over token alcohol, this is the essence of sequence, now let us look at the two basic sequence elements latch and a clip top, so a latch is a level synthesizer device on the other hand a clip top is an h clip top device, the most famous example of a latch is a delatch, what a delatch means is that the data we are going to whenever clock is active, a clip top is usually made from two latches which are a mine and a master slave configuration, we call this a dig clip top or a delay register, now going back to basic digital design we have studied if you remember we studied a JK type or a T type register also but in today's design world the delatch and the clip top are the two most extensively used in the mine, let us look at the timing diagrams of a latch, the latch is on the left hand side, the clip top is on the right hand side, a clip top can be the similar for clip top has a triangle attached to the clock, wherever the clock connects to the triangle this differentiate between a latch and a clip top, so let us look at clocks usually a clock in a design is mostly a free running clock that means it has a certain frequency and there is a high pulse and there is a high pulse and there is a low pulse, now whenever clock goes high let us assume data to be like this, data to be changing like this, what happens to the output of a latch and what happens to the output of a clock, okay now the latch functionality is such that whenever the clock is active that is we are assuming that the clock is active during the high phase during the high pulse, now in this phase a latch is transferring that means whatever happens on D will appear on few after something, so we see here that D is going to 1 and then again going to D is going to 1 again going to 0, so this is this is propagated to Q, so Q goes to 1 and to 0 after some time, now when the clock goes to 0 the closing edge of the clock that is whenever clock is going from high to low, this will close the latch, what it means is that whatever data is there on Q will be held, so any change on D during this period during the clock low period does not appear on Q, let us revise again during clock high high period in the clock high pulse a latch is transferring to latch there is like a combination element or a buffer anything on D gets transferred on to Q whenever this clock goes to an active state whatever is the state of Q is held, on the other hand a flip clock whenever there is a clock whenever clock goes from 0 to 1 that is during a positive edge in a positive edge period flip clock whatever is on D passes on to Q, so now at the at this moment D is 0, so Q goes down to 0 with this arrow the blue arrow shows the effect the time the logic in the timing that is whenever clock goes to 1 whatever is D is transferred on to Q, so Q goes to 0 after some time and then nothing happens on Q irrespective of whatever is happening on D during the during the high pulse or the low pulse. The next trigger will only come as the next positive edge clock when again the D is 1, so Q goes to 1 after 2, so the difference is the latch is a level sensitive device and the flip clock is an extra trigger device. Let us look at how these two Taylor circuits are built using CMOS, this is a very very basic latch nothing but the clock is connected to it, D is D and Q are connected to source and drain effectively this is to go back to the period section it is nothing but a pass transfer latch obviously because the smallest latch possible using CMOS or CMOS, what are the advantages obviously it is very very small and low clock load we will look at what it is meant by low clock load just note that the clock that is 5 has only one load that is the gate drop with 1 is 2, these are advantages once many pass since it is a pass it will have a VT drop it will be non restoring because the output is not driven by VT directly output is in fact driven by D, it will be back driving because D is connected to Q to the decision layer, the effect of this is that whatever noise appears on Q can be back driven to D, it is dynamic we will look into the what is dynamic what does dynamic mean here and the input is not connected to the D input is not connected to gate rather it is connected to decision which is not designed most of the time. Now let us look at in next few slides we will look at the different improvement that I have done over that what have been done over this basic design. So improvement number one we replace a pass transistor by a decision gate, so what we solve we solve the case of VT drop here since now we are using both 3 more and more so there is no VT drop. Now here note that the clock 5 earlier it was connected to just one gate input now it is connected to 2 gate input so the node is increasing on clock and further it requires an inverted clock, next improvement we do is that we try to we added one inverter on D to Q we can add the inverter at the Q side or the D side of the transition gate. Advantages now D in the second case in this case D is now connected to the gate and not to the decision in this case Q, Q bar is not connected to is now connected to the the drain that is it has been driven by VDD here in this case it is restoring Q does not drive anything back to gate by back to D. So one of the two these two designs fixes for example design number one fixes the output noise sensitivity since Q is directly driven by VDD or ground. The second circuit saw the decision input here obviously in both these cases we have the output is not available directly it is available as an inverter, output is an inverter right. Let us see one more improvement go about this for what we do ok. Let us go back to previous circuit and see the state of X. Now these two the X will have some the node X will have some capacitance with respect to ground or VDD depending on the logic level of X. Let us say the clock is 0 whenever the clock is 0 this transition gate is switched off that means D is not connected to X. So the voltage given on X will start degrading over time. Let us say you keep clock off for some some big amount of time the voltage value on X will start degrading across the capacitance with respect to ground or with respect to VDD. This is the case where we say that this circuit is dynamic in nature that is X the node X is dynamic in nature it may show some deepening of the logic. Now in this circuit what we do is we take the feedback from Q we take the feedback from Q and feed it back into X when does this happen? So there can be one one case at a time whenever D is dragging this does not exist this feedback part does not exist because the connection of transmission gate is complementary. So whenever clock is 1 this this transmission gate is active this is an active if you see the clock is connected to the complement here. So D drives X in the other case where the clock is off so this this gate is off and this is off. So now the Q is driving X so at all times X is being driven so that means that we try to restore the value on X on all times. So this circuit is static in nature that means it is not dynamic it is static the back driving risk negative is back driving this because Q is Q being ahead in the circuit is driving back X but still it is in 2 minutes over to ODS. Static LACTA now attention we must make sure that the voltage levels do not fade if the voltage levels are degraded it is very very disadvantageous that means any small noise it will be transmitted. Next improvement the buffer the input buffering the input will obviously fix the diffusion input it is and it is non-involving we do one more tiny improvement is that what we do is instead of compared to the previous circuit instead of taking Q from now Q is feeding back into X here instead of taking Q output here the next improvement we take Q from X what does this do now is that it learns the case of back driving. So Q is Q itself the output itself is not driving back anything into the circuit this is very very desirable from the noise point of view again so this is the most widely used large design this is very very robust obviously since we added about 4 inverters to the basic point in the design it is pretty large it is slow FO4 here means fan out of 4 it has a clock loading now note here that clock here goes to this goes to 4 codes 4 pins so the loading is about 4 here plus we need to invert it but considering all the disadvantages also this circuit is very very robust it is the most important thing. So this is one example of more or less a reputation where we remove the motor from the so to reduce the this can be one if you are we desire that we feel that a diffusion input will not cause lot of problems in smaller designs or in older technology we could remove the motor and make it a bit small obviously this KVD is not the problem. Now let us look at the clock again going back to Morissano basic critical design the clock is made using two latches connected back to back together this clock been inverted to the the first one this is called a master stage configuration so there is an example that so in the first circuit in this circuit we what we do is we connect so this is a this is one latch this D to X this is the Q of first charge and this is again this this part is the second lap they are both connected together the thing to note here is that clock this clock here and this clock here they are both are inverted so the first the first latch gets a complementary clock when compared to the second latch. Now let us try to analyze the functionality of this then we are comfortable with the understanding of the functionality of the first circuit the second circuit is not much different from the first circuit the whatever conceptions applied earlier that is how to make a robust latch we have just converted the two latches here to the more more robust forms otherwise first and second circuits are exactly same in terms of performance. Now let us see whenever clock is low what happens when clock is low or what happens when a clock is stable low or stable high so when clock is stable low stable 0 that means this this particular transmission gate so when when let us let us see ok let us see the first case from D to X what happens from D to X so when pi that is clock is low this part becomes active D to X D to X is connected but complementary X to Q is not connected so whenever clock is low there is no direct connection from D to Q this is in part if the top on sanity when clock is 1 X to Q is connected or Q bar is connected and D to X is not connected so whenever the clock is either active low or active high that is able to there is no direct pass from D to Q now what happens when clock goes from 0 to 1 so whenever clock goes from 0 to 1 so when when when it was 0 this was active this particular part was active so D was connected to X so whatever is on D is on X now when it goes to 1 this latch closes and this latch starts turning on so during the closure of this latch whatever the value of was an X is retained and since this latch is turned on X is transferred to Q so we go back and compare with the timing diagram whenever clock goes from 0 to 1 whatever is on D appears on Q which is what happens in this case so whenever it goes to 1 whatever is on D was transferred to X when clock goes to 1 the value of X is held when clock goes to 1 this part turns on and X is transferred on to Q exactly same thing happens in the second circuit the only difference being we added a couple of feedbacks here to restore the value we took the Q bar from from the intermediate stage we took to here we made sure that there is no Q or Q bar does not write anything back into this process to the second circuit is a more robust more practical but to understand the functionality the process it is now there is one more from now we we saw basic latch basic this block what we do is we will start adding different things to this block and see what happens so one of the more most famous thing is a clock enabled or a data enabled thing so what enable means is that whenever enable is 0 we ignore the clock that means we ignore what ignoring the clock means we ignore what is on D that two ways of implementing enable in a in a latch or a flip flop we add a MUX so this is the MUX where enable is 0 the latch or a flip flop the Q will hold it so whenever enable is 0 the flop input will get whatever is on Q so few will maintain its value whenever enable is 1 it behaves like a normal flip flop that is we will we will write Q on a clock trigger same thing will last this latch the second implementation is adding the gating the enabled with clock so when we get the enable with clock and enable is 0 this is the NAND gate enable is 0 the clock is always be on a latch and a flip flop so nothing happens with the path from D to Q dot whenever clock is 1 it behaves like a normal latch on a flip flop advanced advantage of a MUX design or let us say disadvantage MUX will so this MUX is adding delay in the data path so it will in case of a latch in case of a latch the D to Q delay is increased however for a clock gating case the D to Q path remain same but for a flip flop case the setup time will increase what for enable it is enable will be one more pin we will see what are setup old times in case of flip flop on a latch but just remember for now that the addition of enable pin on the clock will increase the setup time and it will increase the clock's Q because we are adding one more gate into the clock however the instrumentation that is the clock gating we will see lot more of this it is clock gating is the most famous way to save power we will see how now we add something called as reset to clock on a latch reset means that we want to reset the value on the output value we want to reset all the clocks and all the matches in the design then what do we do so there are two types of reset reset synchronous or asynchronous synchronous means that a reset will remain exactly like this in the sense that reset will only affect the output whenever clock gets triggered in case of flip flop however an asynchronous will remain as the name to this whenever we assert reset the Q will go to 0 with respect to of the state of the clock. So, let us see how do we implement a reset for a latch and a flip flop so synchronous case is very very simple since reset behaves exactly like this we just get D with reset so whenever reset becomes 1 this node here becomes 0 and Q becomes 0 whenever the latch is transferred. So, we see that similarly for flip flop we just add reset we get it between that is it so whenever the clock trigger happens this node will get transferred on the Q and if you will become 0 Q bar will become more for asynchronous case is a bit complex bit more complex as far as implementation goes so we will have to reset D and we will also have to reset the intermediate mode why because we want to make sure that this Q goes to 0 in respect to of the state of the clock and whenever the clock the latch is transparent this also this node also should not affect Q. So, we add reset here also let us see what happens when reset goes to 1 reset goes to 1 this node becomes 0 and this node becomes 0 so Q becomes 0 even when the effect of reset goes and the clock is 1 we need D to become 1 to make Q 1. So, if let us say this node was not reset then what would have happened is that whenever clock comes so this intermediate value it can get transferred to Q so to prevent this we make this node so to make to make sure that reset works properly asynchronously we have to make sure that this node here and this node here these two nodes have to be reset. So, we have we get these two points with the reason same thing happens in a clock clock is nothing but master state configuration. So, exactly same thing happens there is one more signal very famous signal called set. So, now we want to make sure that Q is 1 we should have view exactly same concept as reset only the meeting will change. So, this design is implement both reset you left this clock I would urge all of you to go to spice implement this and see the functionality for yourself. So, this is an asynchronous case so you have to verify the functionality that whenever set or reset one of the set or reset is asserted Q goes to the correct value irrespective of the state of the clock please note that it is invalid for both set and reset to be asserted together it is not a valid case since you would want only one to happen and you can also verify what happens in this what happens to Q. So, now we saw the design of a clock we saw the design of the latch of the build now let us look at the sequencing method that is how are these elements connected together to make sure that sequencing is correct that is what happens to the clock. Now, there are three methods first is flip blocks second is using two-field latches third is using pulse latches now design also design wise latches are simpler in the sense of construction wise they are smaller, but when they when we want to use such an element in in our design the blocks are much more simpler to handle the timing relationships are much more clear the clock network is much more simpler compared to that is that is why the first method that is using flip blocks using this type of design is the most popular way of sequencing two and three from this course point of view are the academic nature we will never use two-field latches or pulse latches in our design in this course maybe maybe some of the design people maybe some product companies use this kind of design very very specific cases, but otherwise almost almost 100 percent of the industry uses the first case. So, I will focus a lot on first case compared to cases two and three. Now, let us look at a few things here let us look at the timing diagrams what all timing we will consider then we will go into the sequencing. So, combination logic has only has two types of delays one is the max delay other is the min delay that is how much time so the time it takes from input to these the output this is delay value can be of two types one is the propagation delay as there is a contamination delay when we go back we have to go back a few lectures and see what has contamination delay I will just quickly tell contamination delay is the case where the delay of the combination circuits is less compared to the usual case this is the case where let us say for two input NAND gate both A and B are transitioning. So, the the effect is that we output it gets the value much more sooner than the case where only one of them is from. Of course, for this for this course what I would request is that this assume the logic propagation delay to be a type of a max delay that means, it is the maximum delay this combination logic can have consider T 3D the condemnation delay to be the to be the minimum delay that is it is the minimum delay this combination logic can have apart from the clock. So, for a flip clock case a flip clock says the trigger point is the clock. So, the the propagation delay of the clock is calculated from whenever the clock rises to whenever the Q gets affected. So, for a flip clock the the delay reference point is also the clock. So, this so you have a flop propagation delay clock to Q and you have. So, this is max delay again and you have clock to Q contamination delay which is the limit for latch apart from the clock affecting Q the data also affects Q whenever latches transferred. So, you have four types of delays to our same as a flops that is clock to Q propagation and clock to Q contamination apart from there there are two extra delays which are D to Q propagation and D to Q contamination these two. So, but flops and latches have few extra delay values these are not exactly delay these are restriction. So, a flop let us say a flop is guaranteed to work only if data does not change in a window around this lock. So, let us say the clock transitions here. So, there is a window on both sides during which data should not change only when it is guaranteed that Q will get correct Q. So, this window is called a set up hold window data should be stable at least some time before the clock edge this minimum time constraint is called set up time that is data should be set up before the clock period before the clock trigger edge comes and this restricted time is called set up time. Similarly, data should be held for some time after the clock has passed this restriction is called the hold time. So, for a case of a flop the hold time and set up time are calculated from the the trigger edge that is the clock edge that trigger given for latch it is always a closing that means the edge that closes the edge that latches D to Q the D has to meet a set up and a hold window from that edge. So, a combination logic does not have such a concept a combination logic is purely identical set whatever happens on inputs appears sometime sometime after on the output for a sequential experiment. However, the input should be stable before the trigger edge or a flip flop it is always D for a positive S trigger flip flop it is always a clock positive edge for a level sensitive latch that means which is transferred into high edge it is always a negative. Now, let us see how do we use these these these these delay numbers these delay variables to estimate the frequency of a design or in other words to see what is what will be the sequencing overhead. Now, let us look at a flip flop case the max related now this type of diagram and these equations you encounter a lot of time in the next next units because this is the basis of calculating the frequency of a design. Now, let us say there were there was no sequence element here. So, this combination logic is the only thing present here. So, the delay we say that the delay of this combination of it let us call it let us call it a call it TPD. So, without any so this without any some sequential elements present the delay would have been TPD right. Now, we add we added one stop here one stop here we added some sequential elements now what happens. So, whenever let us say the the frequency that the time period of clock PC the PC the time between the first step will be second end of the clock. Now, everything should happen within this period everything should happen within this period. So, now now let us say whenever the clocks per stage comes it takes some time that is the since we are talking about max delay we will take all the max delays in the previous one the max delays are always the propagation delay the mean delay the contamination delays. So, for max delay case we will take for the maximum delay this clock will have is TPC Q. So, after let us say clock arrives on 0 time Q 1 changes at TPC Q D 2 changes at TPD plus TPC Q and since this this change here at D 2 should be at least before the setup time here. So, what I would say is the total delay of this circuit is TPC Q plus TPD plus T setup and this total delay should obviously be less than the the time period of the clock this condition will make sure that a circuit works. Now, let us see what the equation is. So, take take T setup plus TPC Q to this side and confirm that what whatever we have understood is in fact this equation. So, T setup plus TPC Q plus TPD all these three combined together should be less than TQ. Now, TPD was the original combination of the delay. So, we say that we realize is the equation to and take T setup and TPC Q to this side. Now, we see that the TPD we have added these two the T setup and TPC Q are only there because we added sequential element here this clock 2. So, we say that we are adding a sequencing overhead of T setup plus TPC Q this equation is very very important we will revisit this many many time we will revisit this when we start synthesis and static timing analysis. So, please take some time in understanding this even if it is not clear here I am I am sure that it will be clear in unit 4 and 5. Now, let us look at what happens on during two phase latches I will not spend too much time here on this latch case synthesis model it is just a critical case. So, what you could do is you could go back and write the equation on paper and understand how it works. So, the two phases that it latches the concept is something like this the clock of latch 1 and latch 2. So, you have latch 1 and latch 3 are connected by same clock latch 2 clock is does not overlap with latch 1 clock. So, there are two clock you have 5 1 and 5 2 now what happens now let us say 5 1 goes after. So, L 1 becomes transparent. So, data add Q 1 changes after PDQ this PDQ data add D 2 changes after TPD 1 now latch 2 again latch 2 becomes active here. So, there is TPD 2 again for latch 2 and again you have TPD 2 of this combination of the two. So, data after D 3 data D 3 changes after TPD 1 plus TPD 2 1 plus TPD 1 plus TPD 2 2 plus TPD 2 without the latches the delay would have been TPD 1 plus TPD 2. So, whatever we add here good. So, what is the extra here nothing, but the propagation delay of latch 1 and latch 2. In fact, this is the sequencing overhead which is 2 we add 2 times the delay of a latch. Now, please note here that there is no set of time constraint here why because the set of time for a latch is calculated from the closing edge here this closing edge is not important at all why again because we made 5 1 and 5 2 non overlap. We have made sure that the data add D 2 changes before 5 2 opens. So, we are not changing data on the only closing edge. So, there is no point of there is no concept of set of time here in this in this case right. So, let us go to again this type of design is very very there using all the latches the clocks are more preferred since sequencing is much more in control there as you see that we use 2 clocks here in a big design. Let us say have a design has a 100,000 sequential element the 100,000 sequential element which are let us say are driven by a single clock this is a very very common case where a single clock drive a 1000s of clocks in a design. So, there is a lot of clock overhead now compared this 2 let us a flip clock will have a flip clock based design will just have 1 clock. So, 1 clock goes to let us say multiple 1000 clock if we replace that by latches and this scheme we will have to make we have to have 2 clocks. So, adding 1 more clock adds again multiple 1000 of overhead right plus you have to make sure that 5 2 and 5 1 are normal non overlapping and that is not very easy in a big design. Oil to like clock goes with so many buffers there is lot of you. So, it is not easy to make sure that 5 2 and 5 1 are always non overlapping this is why this scheme is not very very popular at a big level. This is the third case which is pulse latches. So, let us just note that we are looking at the max delay K to 0. So, all we are looking at is the propagation delays and not the contamination. Let us look at pulse latches again we have 2 pulses here. So, there will be a pulse here and there will be a pulse here. So, there are 2 cases where pulse is greater than the set of time or pulse is less than the set of time. Now, here the closing edge becomes important because this closing edge becomes important because it is not it is just a pulse. So, now let us say the pulse it is more than the set of time. So, you will have D to Q you have TPD Q that is clock to Q sorry data to Q plus you have the TPD and this should be this should be before happened before the TPD and the next edge in the next pulse happens. So, combine these 2 cases here we say that the the sequencing overhead is maxed of TPD or TTCQ that is either contamination of the propagation delay plus T setup the set of time of this comes into picture the closing edge comes into picture here and minus the pulse width of 1 because here the pulse width is this pulse width this pulse width is actually eating into the cycle time. So, everything should happen before that I do not worry too much about the pulse status case it is really used it will you will never see this again after in this course. Now, let us let us look at the main delay that is what happens. So, when a so a cloth has a maxed delay and a main delay we saw the maxed delay case we saw let us go back to the maxed delay. So, now let us spend some time here. So, let us look at this equation here this equation here now what this does is the equation does is it places a maximum timing constraint on this whole design this. So, what it says here is that the combination the iteration of the propagation delay of the cloth plus the combination logic plus the set of time set of time is kind of a delay in this case this cannot be greater than the period or the frequency of the cloth. What it means is that let us say you have a big combination logic and plus you have some delay of the cloth what this does is it places the design it tells us that there is a maximum frequency at which a design can operate. You cannot decrease TC without any limits the maximum limit of TC the maximum frequency at which you can operate a design is 1 divided by TPD plus T set up plus TPD. So, we call this as a max delay case since it applies a maximum constraint on your frequency. Now, keeping that in mind let us look at the mid delay. So, now the minimum delay of a cloth now in this case we will take TCQ. So, the Q 1 changes after TCQ, D 2 changes after the minimum delay of combination logic which is the TCD in this case. So, now TCD plus TCQ should be such that they do. So, this cloth is actually the cloth you can flip up to F 2. The delay change at D 2 should happen in such that it means the whole time requirement of this cloth. So, you have so what it means is that TCQ plus CCD should be greater than the T hole. So, data should be held kept held after T hole when does data change data changes at TC T contamination delay of the cloth plus TCD of the combination logic. So, TCD plus TCQ should be greater than T hole which is actually again we arrange the equation and come up with this. So, TCD plus TCQ is greater than T hole or greater than or equal to T T hole we rearrange the equation and get this. Again the sequencing overhead is nothing but this TCQ this is actually on a sequencing overhead but what it does it places a min timing requirement on the on the total delay. So, what is the total delay here the total delay is TCD plus TCQ and it should at every time all the times it should be greater than the T hole. So, now we see that the total delay that is the delay is actually nothing but the combination delay for the sequencing delay should be at all times greater than the T hole or and less than the time period of the cloth adjusted by the set of time. So, in fact, now the delay of the circuit is limited by two cases one is the max case as well as the min case. Also note that there is no the cloth frequency does not come into picture here we will go into depth in in unit 5 on on this equation this equation is very very important again same as set of time equation. Similarly, we have the min delay case for two phase arches and we have the min delay case for the pulse. So, there is two phase arches of two phase arches again it is very similar to the earlier case where we say that the delay here TCD1 TCD1 plus TC2 and plus TC2 plus T non overlap should be greater than the T hole requirement. The paradox here is that the whole time is reduced by the non overlap the whole time applies twice each cycle. But only one for cloths but again inside the cloth is made up of two latches you can verify this no need to go deep into this paradox it might be bit confusing, but we clear that the one thing is clear that the equation of cloths are similar compared to that is the clocking scheme again is similar you have known this is not there you do not have to worry about overlapping or not overlapping of cloths. So, that is why a flip top based design is much more complicated. So, this is a case of pulse latches I will not go deep into this there is no need for it now. Now let us touch upon a concept called time borrowers now in a cloth based system the data imagine imagine a design like this. So, a design like this the data is drawn onto the rising edge from the cloth 1 it gets captured D2 gets captured at F2 on this edge this places a constraint here that everything that has to happen has to happen between these 2 edges. So, data launches on 1 rising edge my setup that is it should become stable before setup time before the next rising edge. If the data arrives late system fail obviously, you need to capture the new data, but it is delayed you could not capture it if it arrives early that means if it arrives even earlier than the whole time requirement of the next stop then again the system fails or second case it arrives somewhere in the middle that is it needs both the whole time requirement and the setup time requirement. So, the time you have the remaining time you have is actually wasted it in the sense that what it again tells us that the fast tokens you use load them, but then you have some margin available that margin is wasted. So, what it what it compares it it compares the flop based system with the latch based system and tells us that if the data arrives early, but it still needs whole time requirement time is wasted. Flops have hard edges this is very important thing you will notice and the earlier design that since the flop works on edges nothing happens between the edges on the flop so flop has hard edges. Now compared to this in a latch based system a data can pass through latch when transferring what it means is that by playing with the clock overlapping or non-overlapping of the clocks we can actually make sure that time is not wasted this is called time volume that is we take the time from a fast circuit and give the time back to a slower circuit only if the only condition is that each loop should complete in one cycle. Let us look at one example this is again a very this is now a common design feature where so some what happens is that you have phi 1 and phi 2 again same case. Now in this case phi 1 and phi 2 are complementary of each other. So there is actually only one clock phi 1 and it is complementary and it is inverted and given to latch in the menu. So this latch will launch data there will be this there will be a combination delay and then we could borrow time from this circuit to this side why because let us say this is a slow circuit this part is a slow circuit. So it takes a lot of time and it if the data becomes stable somewhere here somewhere here but now the latch is transferring. So there is no data does not stop here data directly goes to this third latch and let us say this when it wants to capture this the data should remain stable should come let us say somewhere around here. So even if the circuit this part of circuit is slow and this part of circuit is fast we made sure that the data the time is not wasted and in fact this is perfectly utilized the only requirement the only constraint here is that the only constraint being that the combined delay of combination logic 1 and combination logic 2 should at all cost be less than this this time period this time period we will again look more into detail we will look at a case where actually this is a clock this is a clock and this part is a latch this very famous time warranty we will look into this into more detail in unit time. This is again one more example of a circuit connected in loop so see this this length is more here for a combination logic so this means it is a true logic this is a fast logic again this is the case is same as the casing. Now all the in all the previous examples we were assuming that clock 2 is 0 what it means is that the clock arrives on the clock 1 and the clock 2 at the same time but this is not exactly true the clock since the clocks go to thousands of clocks in the design not all the clocks will get the clock at the same time there will be some uncertainty in the arrival time what it does then certainly it does to design is that it decreases the maximum propagation delay it increases the minimum termination delay it decreases time borrowing so it affects negatively in all the cases. Let us see one case for flip tops so what so now there is you see this this figure here now the clock arrival at each of the flip tops is actually uncertain in some limit it is uncertain in this limit so what it does is that it reduces the amount of margin you have so what it does is that it adds to the propagation delay so we saw that so TPD plus TPC2 plus Tsetup now we add T skew in this T skew adds to the sequencing overhead similarly this skew however it is shown positive here but this skew can also be negative that means it can also affect whole time negatively so what happens let us say if the clock edge arrives early here it is not good for set of case if the if the clock edge arrives later here it is not good for the whole case let us there is a skew case for lattice you can go through the equation again since it is not a very popular design you can you can skip it so let us look at what happens if set of time is valid if set of time is valid if we saw that the set of time imposes a maximum performance limitation on a design so set of time is violated on a managed actual you can actually reduce the frequency and still set if it is working but in the whole time valid you can do nothing just will fail at any frequency since whole time requirement is not the whole time constraint the middle time constraint is not dependent on the frequency so in fact this is the reason we will keep changing this is the reason why people are designers are more alert more varied of the whole time cases so you have to make sure that hold needs in all cases what all cases needs needs at all the voltage the voltage range for the typical specifies it means at all the corners of the temperature range it means in the slow process as well as fast process we will be on the case of data so this is the end of this let us summarize what we saw what we learned in the session we saw the design of the two basic things the matches on the flip-flops the flop are very very easy to use they are supported by all tools these are the three sequencing scheme which are flip-flops two-phase transferring latches and twelfth latches two-phase transferring latches have a problem of skew tolerance you have to have non-overlap of mapping and time-borrowing both latches are I in my experience I have a few twelfth latches ever because it involves a completely different clock scheme so I just found this case all together this table gives the sequencing overhead the sequencing overhead of the match today the minimum logic today and the time-borrowing case so you see for the flip-flops there is no such concept as time-borrowing there are some time-borrowing equations for two-phase transferring latches and twelfth latches you can skip to this so that is all for this lecture thank you