 So let me now continue with the amplifiers. Please remember one of the main feature of analog design is an amplifier design. That is our major workhorse. So we want to understand everything what an amplifier can do or how to get to that spec okay. So we have looked into common source, common gate, source followers, normal single stage amplifier. We looked into cascodes. We also have some interesting features about the how analog circuits are important in the current scenario. My first few lectures on PPT. So this is all that we have so far covered. Today we start with more details on that. The first thing we will like to know what kind of loads one should use. All this time I was using a resistive load which is essentially a actual resistor. The problem with actual resistor in a circuit, not that we will never put that but essentially we avoid it as I discussed earlier sometime that the sheet resistance available for normal CMOS design, CMOS technology is not very high. So we said that the load resistance of typically 40 K will be required and for that values 10 to 40 K, the aspect ratio is so high that it will be very very difficult to put more than few transistors on chip. That means it will take more area for resistor than the transistors. So we said okay we will not like to use resistors as made out of normal semiconductor. Please do not think I will never use it. I will have to use somewhere I will okay. But normally I will avoid. So replacing a resistor by a transistor itself is called active load and therefore we are saying resistor is now replaced by the device which acts like a resistor. These are called active loads because transistor is an active device. So one of the most commonly used load in almost all analog and also in digital is called diode connected load. Now what is this diode connection is I think we are done many times earlier. So I will not explain why name diode but think of it there must be something in it to call diode. In this case for N channel the gate is or for P channel gate is connected to the drain okay permanently. And then if you evaluate the resistance seen you can see from your IDS, VDS characteristics if the device remains in saturation throughout in that case for a given VGS which is what is VGS here VDD-VS. VGS is how much because VG is connected to drain. So VGS is VDD-VS. And if that remains always smaller than VDS or equal to VDS the device will permanently remain in saturation. And if it remains this resistance of the characteristics shown here which has a very large R because of the slope is very low. This will can act like a resistor okay. The example whatever I said is given in the formulation VDS is VGS plus VDS VGD. Since VGD is made 0 VDS is always equal to VGS and therefore VGS minus VT is always less than VDS and therefore device is permanently in saturation. And the characteristics current characteristics can be written as beta by 2 VGS minus VT square assuming lambda small. You wish put lambda you can though you may say if the lambda is 0 then that should show infinite but assume the value is whatever desirable. And this acts therefore acts like a constant current source. So sometimes it is also called current source loads. The diode connected loads are also sometimes called current source loads okay because this is a current source. It is only a function of given VGS and therefore it is constant current source. Now I will show you what is important for us a good current source that it should have a large resistance parallel resistance to the current source as phi is that is the beta 1. So we will evaluate for this case what is the impedance seen by this device as a load and if that is essentially is the feature how good is diode connected load will be okay. Is that okay for those who are written on now. So if I wish to figure out R0 I put an equivalent circuit as I did earlier please remember we say VG and VD are connected gate to drain. So drain to gate to drain is connected okay. You have V1 across gate to source GMV1 is the current source GMVVBS is the current source due to the body back buyers are the resistance and this drain is also grounded now for AC for VD design. Now if you see and then I apply a source VX and find a current there and VX by X will be R0. Essentially we if we rewrite the current now IX which is shown here in this direction you can choose any direction do not worry sign should be taken care otherwise this is why the VX source are applied current leaving the source I used as plus IX going up okay. So essentially this current and this current must balance because at this node the net voltage net current must sum to 0 okay at source node this current and sum of these current must equal to 0. So if I rewrite IX equal to GM plus GMVVX plus VX by R0 and then I write IX is GM1 upon R0 VX I get and if I say R0 is very very large compared to one upon GMs or RO which is the resistance seen here for the device M top device that becomes one upon GM plus GMV. In case GMV is also not given to you many times I may say there is no back gate bias and in that case it is only one upon GM please remember there is R0 is sitting there essentially R0 is across one upon GM and whichever is smaller will take care since one upon GM will be smaller compared to R0 so one can say typically diode connected loads gives you a resistance of one upon GM and not R0 as we thought that is the issue which I wanted to raise okay is that point here the resistance seen by the lower device as a load is just one upon GM under diode connections is that correct is that clear. Now this is an issue whether this is good enough or not is what designers should know if your GMs are very very low yes this RO can be as high as possible alternately when GMs are low when GMs will be low when is the GM low for a normal device either the current is flowing is low which may be good in at time for what purpose low power current is reduced or the W by L is smaller so the smallest size transistors if you use your resistance can be built please remember normally the channel length which you can create is normally a technology parameter okay to reduce W by L all that you say do not use the minimum channels use multiple channel lengths that is if you are working on 90 nanometers typical channel length is around 60 nanometers so you put 120 nanometers at length instead of L put 9 instead of 60 put 120 there that you can always you cannot go below 60 you can always so W cannot be go below 60 so do not increase decrease W but increase the lengths whenever you need this this is also true in the case of lambda when we say if you reduce lambda is lambda dash by L and you want to reduce lambda that is the bias parameter then what do you do increase lengths as much as possible so larger the length smaller is lambda and better is the current source you get so that is similar feature is also appearing in this analysis is that correct so longer length device is good for good analog blocks okay however what is the problem larger the length you put the size of transistor will enhance W into 12 which means area penalty you are paying something else I did not say you will also figure it out the capacitance will vary because of the area variation so somewhere bandwidth may also get affected okay how much you will see when we go to frequencies so there are issues so it is not that you just push it or just reduce it for a given design you must choose what else you should use what is possibility available so otherwise do not use diode connected loads if that is hurting you so much okay is that clear okay if you look at the gain of an amplifier which has this diode connected same thing which I stated is given here do not rewrite I already said GM is proportioned W by L and ideas root of ideas and that is what I say the increase lengths okay the gain is GM 1 RO if RO is the risk of course it is also shunted by RO 1 of the driver okay since if RO 2 is smaller than RO 1 then it is only RO 2 if not then you have to figure it out how much it should be parallel so put parallel and whichever turns is smaller will take care okay so if I substitute this GM 1 into this into this figure I get on and roughly I will say AV 0 is W by L by 1 by W by L 2 divided by 1 plus eta if eta you do not want to keep put it 0 you may also use eta 0 if many cases so what is this kind of amplifier is suggesting that but just make a ratio of W by L of the load transistor to the W by L of the driver transistor and you can adjust your gain without any other parameter in question so if you are looking for something constant or variable which should not affect your AV 0 then this is an ideal situation just sizing so I and please remember individual size is not relevant the ratio is relevant so you can adjust individual sizes to suit something else but still make a ratio of required current gain voltage gains that is the strength of diode connected amplifiers a load diode connected loads for an amplifier so choice is not that you should use or you should not use choice is what when to use you should be aware is that point clear why I showed you that connected loads because one wants to know that just by adjusting the ratio I have a control on the gain itself is that am I clear of what I am saying so this is something very interesting and designs because if I do not have to worry too much about VT is I do not worry about VDD if everything is as long as device in saturation thank you very much the ratio will take care of my gains and remember ratio is independent of what temperature environment any other things and therefore we say just by design parameter I am controlling the gain and which is the design parameter which is on the plan of the wafer or which is the surface area which I am controlling nothing to do with in the wafer inside that something great happens so this is inaccurate because we assume few things but to a great extent this is reasonable assumptions so what is the way I will say when I say I want to design an amplifier of a gain of 1000 I will never say 1000 I will say the minimum gain expected is 1000 so this adjustment is still within your hand you say okay as long as it is not lower than 1000 in other parameters you wish to control you have right to control normally gains are never specified 976 kind of there is nothing such things okay. So as I say we can also use amplifiers other loads also okay the other loads could be what I said other day just by putting an internal transistor and biasing it that means if this transistor is biased heavily by me such that VGS is – VT is always greater than VDS so transistor will remain in non-saturations so linear mode is a smaller resistance and the value how will I adjust that value by W by L so again by using a W by L and keeping VGS – VT larger than VDS for the load device I can control my smaller value of resistances okay so next we move to the most important amplifier which is almost used I would not say excluding to other three but most times we will use this amplifier for all amplification purpose in analog is a differential amplifier now this word is slightly worrisome to me there are words in the books called difference amplifier there are words is called fully differential amplifiers okay so we should be slightly worried about these statements right now the difference amplifier and differential amplifier here is the same so if I say defam or difference amplifier a differential amplifier I mean the same but later on in some design and say it is a fully differential system so I will define what I meant then till then assume that difference amplifier differential amplifier or a defam is same now what is the problem in common source common gate or common drain amplifier one of the major issue of which we did not discuss very often in earlier designs is we know that the their properties strongly depend on the Q point where do you put your biasing okay now biasing seems to be trivial to many just apply bias and you get it okay it does not happen so easily for example if I put a V bias in series to the signal yeah it is going to bias this transistor keep it wherever you wish series are in non-nonsaturated which ever way and this should work but this is not working the way we thought it should okay since gain of an amplifier is constant only and only if gm and r0 are constant however the value of V bias and the signal over reading on that bias this amplitude of this where do you bias and how much is the signal sitting on this on a real characteristics may push you device from different r0 values and therefore sometimes different gm values which essentially means both the parameters of gm and r0 are strong functions of not only V bias but what is the amplitude of the signal and where it is biased okay so our assumption that the gain is constant is not very true because it is now a function of input which is never be wanted because that happens the gains will be different at different input sides particularly if this may happen when the gains are extremely high swings are too high and that time these assumptions are not very good and therefore we may worry about how to get good biasing what is the condition I am saying that biasing should not influence the outputs is that clear that is what I ideally have like so that I get good current voltage gains yes if we use constant current biasing may be this issue can be addressed a typical biasing system can be something like this this is say I bias which is flowing through this transistor and its drain is connected to the gate like a diode essentially but the same gate is connected to the actual amplifier which you want to bias okay this is the precursor of the mirror okay that is the idea behind mirrors. Now what we do is the way we kept these two transistors are identical okay their gates are common their sources are common so what is equal for both of them VGS is equal to VGS M call it say M1 so VGS for M1 is same as VGS for M2. Now you want to put input signal so you must put through V in now you have to put this value why you have to put this C because you have to isolate AC from DC so I put a series resistance to the source a series capacitance to the source which is CS however if this capacitance is only left there it is like an impedance at certain frequencies what is my idea is that for a DC at least it should pass everything all frequencies should it pass so instead of just CS I must create convert it into some kind of a high pass filter whose cutoff is very close to 0 higher than DC but so where should I put a resistor and since there is no gate currents what does that mean any resistance will not change any drops across because there is no current in the gate side is that clear because gate isolated from by insulations. So if I use this circuit and convert it slightly modified V so what is so what he said and I agreed with him that yeah I can use current biasing and I can have independent of my actual transistor I put left side my bias circuit that is what every analog designers will find there will be biasing block of course that should learn separately how to create references both for current references as well as voltage references which will make this constant so that is another part which will look like so with that circuit then this whole circuit will be called biasing circuit now I am showing you very carefully all this is now required in what we call in normal digital hardware which is called DC to DC converters using constant biasing sources or constant current sources this is called biasing module now you have to create to create 1 volt 1.2 volt 1.535 mini voltages you need on the digital these days this is one of the way this can be created change the sizes and you have different values so I said okay I have put a larger resistance this then this is essentially high pass filter and this has a cutoff frequency upon 2 pi R L R C S and we want this to be as low as possible good high pass filter this means R and C should be very high now what is the problem with R and C high both are functions of lengths and widths okay when you make on a silicon they will be functions of W and L whatever size you keep there for them larger means larger area you are picking up anyway so if you can do this is a good way of doing it but it has the feature that it actually increases the adage it requires additional areas implement this will do your job guarantee please remember this is the scheme which we do employ in an RF Ampli course is not going to talk of RF systems but if it does if I had to then I say okay this is one of the very common biasing techniques in the case of RF so if you are designing a power amplifier or a low noise amplifier in RF range probably you may look back and see this was one method I use there in those designs okay so please remember in this scheme I bias is going to decide the GM of M2 or whatever name I M1 and therefore it is independent of the bias whatever comes here I am not worried it is only I which is going to decide the GM so I have avoided that we bias dependence by making a constant current source okay even if variations occur and if it does not still change anything then why should we money so much about it okay and that is what exactly the differential amplifier does okay why this was a precursor sheets to show you why differential amplifiers became apart from many other advantages of different which is making so important one of the reason was that the biasing became very trivial in the case of difference because even if it is not constant it takes care of it okay and that is some fun part in that the differential amplifier gains are normally very stable gains okay and that is why we prefer differential amplifiers apart from many other features which we shall now discuss that differential amplifier is far superior in many characteristics over single stage amplifiers but then why this single stage amplifiers are sitting at all okay this is an issue we should answer so you I just want to tell you very clearly a differential amplifier is a better solution to this biasing problem compared to what I showed for single stage let us say I have an input VI okay what is the differential amplifier you have two transistors M1 and M2 which sources are connected and given a common bias current source okay now there is also case the same different by loads kind of current sources I create I can use one of them to create this right now right now my assumption is I bias is ideal but in real life I bias may not be ideal source so what it may give some resistance so what it will affect us okay but as of now for simplicity we start with thing it is good thing then we have a load RD they can be RD1 and RD2 and they can be same so it is not a compulsion that they should have same loads okay so we say the GM of both these transistors are decided but this is sometimes called bias current or tail currents some book call it tail some book will call bias whichever books or book or none whichever way you are take it either is called tail current or it is called bias current so since this only decides the GM in this an interesting outcome of this difference is that the difference of output voltage is now only proportional to the difference of input voltage I repeat the AC part as if I show you VO1-VO2 is only decided by VI1-VI2 and nothing else so there is no way if this changes still it will give the difference of that okay what will happen if there is this both will get affected and in difference they may not be available because difference will get cancelled out this is the idea so the first problem of bias variations or bias dependent variations at the output can be eliminated if you have if variation occurs it should occur together and the difference will cancel it out so this was the one reason as I repeatedly saying this is not the only reason this was one such reason why Defam was preferred because they say okay this bias issues are partly taken care so even if this is not constant does not matter I am not very much worried on that of course if it changes so much that device goes from saturation to not then I am worried otherwise swings are not of my interest okay. Another part which all of you are aware for this Defam of course is since I said so difference anything which assuming that the any noise is universal and whatever additional noise voltage appears here will also appear here then VI1 plus V noise VI2 plus V noise and if I take a difference I do I leave the noise part anyway so anything the word now which will later come is common mode which is common to both will get anyway eliminated so the major reason why Defam was used that it allows you to remove noise common mode noise from the any circuit the assumption of course is in a small area Defam's the noise pickups are similar okay before we go maybe I have another few things of the another interesting feature as a first was the bias the second was the noise common mode noise as we called there was something third which common mode systems which rejection it occurs the word is that is why there is a famous term we use for Defam's as common mode rejection ratio okay CMRR that exactly is the measure for that how much rejection it will do ideally it should benefit it should common mode gain should be zeroes preferable but it will not be there will be some large ratio may come which is good enough to say effect of that is very small okay so the third and the very important feature which is that okay which is not I think I did not think earlier but just now I remembered particularly this is for the people who are working on digital or mixed signals there is a huge issue right now right now going on where is your digital course right now there is a design there are issues or maybe system design courses in next semester okay so one of the issue there we figured out you have one interconnect okay and a signal is entering from here this is your out through it interconnect this is a signaling problem which is very trivial which very important and let us say there is another interconnect which is across which is called and this in our terminology there is called aggressive cell or aggressive cell interconnect now if you are two such interconnect lines close by not necessarily orthogonal but even parallel there is a capacitance which is associated between the two lines okay now since there is a capacitance associated with two lines so if whatever signal you are going to put depending on this coupling it goes the voltage here may actually be something like this or sometimes like your data transmission will be actually impaired heavily and if there are more than two aggressive lines it may actually hit you worst further there is also an issue if the data is flowing in this direction or flowing in this direction in aggressive that may also change the output patterns ideally I do not want this to influence so what I say it okay if you have an aggressive here I have another interconnect line I have same signals going to both this and the output I will take the difference of the output as well is that clear so now whatever change is occurring between these two lines it will get eliminated because of the difference outputs with the difference inputs so in a aggressive cell effects can be nullified equivalently by putting another parallel another line for it okay penalty is huge area you put it actually but signal system people will tell you it is better to have larger area chip than not working chip so this is an issue which there we solve by different way this is a crosstalk issue there are number of ways we tried and this also increases the power dissipation so far low power this is one of the issue how to reduce the power actually so there are issues which digital people are looking into and there also we will prefer difference outputs or difference inputs to be in different input so defam it is not really connected to defam word but trying to show you that where this difference schemes actually are useful is that point clear so please take it these are the issues which are cross connected to digital okay so as I said defam has advantage that it will you common mode rejections possible and it will solve much of the biasing issue okay in addition to that if it does something more okay that is a bonus for me if it does not do it at least gives gain of a common one single stage is fair enough but if it does even better which I think I will then I have got much more value out of the same system okay that is why defam are most popular amplifiers before we go to the small signal analysis it is intuitively proper it is intuitively one must think about the last signal behavior last signal means only DC values are used there ACs are small you can add to that if you wish basically we are looking for DC analysis okay so let us say you have a differential amplifier with two transistor M1 and M2 which is biased by ISS this word I changed from I biased to ISS because this is what Razavi says so I thought at least if you go and read Razavi once at least you should not feel very differently different okay so I first I wrote bias then I realize I open the book of the he say what I tell current he says ISS so I changed to ISS does not matter you can use any way in one and way in two are the inputs and the most important worry and most important point which we want to discuss through this is this point P which is common point for sources of both M1 and M2 now figure it out this if per say this voltage at P changes VJS of this and VJS of this may not be same is that correct but does that really affects you if it does not or does it change at all we like to see by this system whether the P point is stable that is why this large signal analysis what is the VO1 will be VDD minus IDS1 times RD1 VO2 will be VDD minus drop across RD2 I subtract VO1 minus this is difference output voltage VO1 minus VO2 and if I subtract here it is IDS2 minus IDS1 RD1 or IDS2 minus ID1 into RD assuming RDs are same further if you look at the input side this is VJS so we say V in 1 minus V in 2 what is essentially the value V in 1 is equal to VJS plus drop across current source if any is that correct but that is common for both sides I do not take care otherwise say V in 1 minus V in 2 is subtraction of VJS1 minus VJS2 for the simplicity lambda is taken 0 for all analysis till stated otherwise is that okay please remember lambda can be taken care all that will happen is you know nonlinear terms will start occurring in under roots and squares and then analytical solutions will not be very easy to understand we are not really designing on them what we are using it to explain something and since lambda is anyway 0.01 or 0.04 or 5 kind of thing it will not drastically change the physics anyway however physically please do not leave lambda as 0 if you are calculating R0 because otherwise that R0 may become gains will impact so do not think that I am leaving lambda but for explanation of voltages I do not believe it is very much important is that okay okay is that okay expressions we wrote V in 1 minus V in 2 is VJS1 minus VJS2 and V1 minus V2 is IDS2 minus IDS1 times RD if RD1 equal to RD2 equal to RD is that okay everyone so now we have we write the drain current as beta by 2 VJS minus VT so we can also write VJS as under root of 2 IDS by beta also we are use alpha equal to 1 in all this analysis as I say unless stated otherwise use alpha 1 lambda 0 otherwise if given or even eta equal to 0 unless stated otherwise so VJS is for the last signal these were these do not matter so we do not add that much small signal yes I may add all those term because small signal they will actually affect it so VJS is 2 IDS by beta plus VT so if I want to write V in 1 minus V in 2 that is VJS plus VT my VJS VT minus this which is essentially I write 2 terms for IDS V in 1 and V in 2 which is equal to 2 IDS 1 beta minus 2 IDS 2 by beta to get the point IDS 1 and IDS 2 appeared in output so I now replaced input also in terms of IDS 1 and IDS 2 is that point clear why I did this the output was a function of IDS 1 IDS 2 I say okay input is also in a way expandable through IDS 1 and IDS 2 okay. One important feature of FAM is which is very important if you write down you first write down only up to this and then I will come back and show figure and come back to this is that okay is that this much you are written above okay so if we see the figure here the drain current of M1 and drain current of M2 can only sink through the current source okay which means whatever value of IDS 1 and IDS 2 they some should be always equal to the ISS so this is the major feature of a different it may happen this may be larger this may be smaller or this may be larger this may be follow or they may be equal any case the sum total will be always equal to ISS and that is the feature of a different okay. So since for all cases IDS 1 equal to IDS 1 plus IDS says we now rewrite VN 1 minus V into square is square of this square of this minus 2 times this multiply if you take it 4 by beta IDS 1 IDS 2 then we say IDS 1 plus IDS 2 is ISS so 2 by beta ISS minus 4 by beta under root of IDS 1 into IDS 2 it is a mathematics sub joke only but just we want to show at the end of the day what should be the limit of V in 1 minus V in 2 corresponding to which IDS 1, IDS 2 should be available to us before I go ahead may be I physically still I may tell you what I am trying to tell you so that this whole expression which I derive will be aware is that okay you are written down these two three lines okay what I am trying to say you is the difference of these two currents IDS 1 and IDS 2 is a function of difference in V in 1, V in 2 but if say V in 1 is equal to V in 2 then we believe that IDS 1 minus IDS 2 must be 0 it must be equal okay and if that occurs we can say each current is half half because IDS 1 must be equal to IDS 2 equal to ISS means each arm must flow so if the inputs are same we want to see our difference of input is 0 then the each arm will get 50% of IS that is what we want to prove which is anyway visible from here but mathematically maybe I will show you yeah it does come finally after huge equation solving so we say expressing that beta by 2 V in 1 minus V 2 minus ISS is minus 2 IDS 1, IDS 2 under root of that however mathematically IDS 1 plus IDS 2 square minus IDS 1 minus IDS 2 square if you don't know to expand karenge so you have 4 IDS 1, IDS 2 atai is ke doh minus us ke doh to char okay so 4 IDS 1, IDS 2 is nothing but subtraction of these two but what is this term ISS square okay so we write ISS square minus IDS 1 minus IDS 2 square is 2 under root IDS 2 whole square therefore this term IDS 1 minus IDS 2 square is ISS square minus 2 IDS 2 square but this term is how much from here beta by 2 V in 1 minus V into square minus ISS square is okay I use this term in substituting here 2 IDS 1, IDS 2 beta minus V in 1 expand karenge yeah that is what I was also thinking why I am doing this I want to show that V in 1 minus V in 2 plus minus us atai so up to what value of V in 1 minus V in 2 which currents both will flow or one of them will flow from onwards where the other current will down so I say if IDS 2 start going down or IDS 1 start going down or IDS 1 becomes maximum that figure I have to draw is that okay so I want to plot IDS 2 IDS 1 against delta V in which can be plus why minus because if V in 1 is higher or lower than V in 2 it can be plus minus basically I already said if V in 1 minus okay you are written down this expression you write down I will come back to Maths or Physics again very trivial things I am rewriting but I want to show mathematically derivable things which you can otherwise also understand okay so what I was saying you is this figure if you see again basically what I am saying VGS 1 is or V in 1 is much larger than V in 2 this will draw larger current is that correct larger this current means smaller this current because ISS is fixed so if this draws more current the other will go down if this is larger that is delta V in is minus now difference if this is larger this will draw larger current this will draw smaller current after a while when this transistor does not have enough PT support all the current will either flow here or flow here is that correct so at certain value of delta V in beyond that only one of the transistor will remain turn on and because of that all of ISS will flow through M1 or M2 is that clear to you this is what physically visible so okay after all that equation you can rewrite this becomes IDS 1 minus IDS 2 is beta by 2 V in 1 minus V into square B4 ISS by beta minus V in 1 minus V into square and V in 1 minus V into the essentially delta V in difference of the two so if difference of the two V in 1 is equal to V in 2 IDS 1 minus IDS 2 is 0 is that you first write the expression which I said physically is visible now if V in 1 is equal to V in 2 that is delta V in is 0 IDS 1 is equal to IDS 2 but IDS 1 plus IDS 2 is ISS each arm will take 50% of the ISS they both inputs are same then 50% current in case this is larger delta V in is positive this term will subtract from this and if you keep increasing plus delta V in after a while this term will start mathematically reducing and you can say or rather different so IDS 1 will almost become ISS this value is typically ISS this was there for ISS by 2 so as V in starts increase delta V in starts increasing IDS 2 start falling and IDS 1 start increasing because that is the expression is asking me as I increase bit beyond the other turns turns off and all of the current goes to IDS 1 by same logic if I do the opposite side symmetry being tells IDS 2 will reach ISS and IDS 1 will become 0 this fact that difference amplifier essentially allows current switching from one arm to the other when the input changes beyond delta V in of this value 2 ISS by beta then we may say it is either drawn current here or drawn current so as long as you remain between these ranges you have some sort of IDS 1 and IDS 2 available which is where defam should work is that clear to you so what is the signal available to you to move out is only 2 delta V in is that correct but the catch word there is if you have an input V in between 2 V in 1- V in 2 if I increase 1 by the same amount if I decrease the second then the change is double is that point clear if I say V in 1 plus delta V in so the V in 2- delta V in is that clear so the difference is now essentially to delta V in so you can switch over from one to the other is that point clear that essentially the feature of a different is that point clear so why I showed you all the mass which is as I did is to prove this point that device switches over from and in these 2 ranges device is operating for as a both device are operating and therefore certain amount of difference outputs can be obtained is that clear now this interesting understanding is only to make point clear this is not solution from anything this is just to say what happens in defam so this is called principle of defam operation this only tells this that switch over occurs from one to the other so now we will like to prove later that if this VP point shifts or does it shift if shift does it can troubles us and if it does not why it does not shift if it does not shift all this analysis will be valid because VGS VGS I will say same all the time this ISS by it was 2 equal both side will go only if VGS 1 is equal to VGS 2 is that clear now this fact S remaining same will ideas 1 ideas 2 will also remain same if not then I have to figure out because VGS changes ideas 1 ideas 2 but I feel I do not think ideas 1 I because we have one we have to remain constant we observe it so I want to say VP does not change now to prove this point and to do a one method of analyzing in opam sorry defam why we are looking so much in defam please remember differential amplifier is not independently used for all application most of the time it will be part of first input stage of opam okay that is the input stage of an opam okay so we will see that that is the opam part so we will see output amplifiers separately we will see shifter I already said it can be done and if I see defam then I know now I have I can control my opam character so I know all three of them that is the trick I am using to at the end of the day my interest is in designing a opam if I can design an opam for a given spec I have done almost 90 percent of analog outputs 90 percent of analog systems will use at least opam or variant of opam what is variant they are low noise opams low swing opams high swing opams or OTAs they are all basically opams okay so we will see that if I understand my defam well and the other two stages then I have control my opam design and if I can do opam for requirements like comparator it is also an opam switch capacitor filter also requires an opam so name any analog system basic component is the biasing of defam is auto we will take care which is useful for everywhere so we will also look into biasing circuits using constant current sources constant current mirrors or constant reference voltages how to do them so these are some things which we are looking for there is very interesting method which one can one gives little interesting thought and therefore this has been shown is called half circuit method it essentially says that if your system is differential what does differential definition is I repeat what is the differential definition I have that if one input changes by plus value the other input must go minus of that by same value is that clear that is called differential system is that clear to you vn plus delta vn vn to minus delta vn is that correct the swing has to be same plus and the other should correspondingly decrease okay so that vn1 minus vn2 should remain similar okay now this fact is called differential circuit so if you have a differential circuit okay which is driven by a constant current source as shown here and it shows along this vertical line symmetry on left and right okay symmetry the word is symmetry for the two inputs okay then we can treat each arm independently and if you can treat this independently then it becomes single stage amplifier okay and then we can see the net effect together and figure out what is voltage here what is voltage here and then subtract and the ratio of v o1 minus v o2 by v1 minus v2 always can be found so this is the technique which is called half so what is the criteria I said each the system has to be differential biased by a common source common current source or common bias technique whichever you do in and it is symmetric for both inputs then the half circuit method is valid is that correct is valid this is only names for left side is identical to right side as far as the circuit sees vn2 rd2 may be different but on the right circuit is identical to that you may put values but they are still symmetric if I mirror of this this will come the same so that is it is symmetric to the source bias do not side case are of may was same deck side so it is symmetric ideal symmetry will be when these are equal and these are also equal but then that is ISS by 2 so that we already checked but we like to see if even if they are not equal as long as that any signal goes higher the other must correspondingly reduce by same amount at the input then system will remain symmetric and we may say this is half circuit method is valid this is of course we have a this is called half circuit lemma which is given in a book maybe if time permitting will be true today in that case we say VP will remain constant for any input combinations this remains constant and if this remains constant VGS always remains constant for both VGS 1 may be not be same as VGS 2 but VGS 1 and VGS 2 S is always same potential that occurs all our earlier theory is valid and therefore we will prove this using this technique that VP is independent please remember any input combination V in 1 V into essentially still is differential in nature change in V in 1 is opposite change in V into that differential part is most important in having half circuit technique valid if it is not a differential system this all concept is not valid majority of differential systems will be always differential if I I can always go from single stage or single input stage to a differential convertors if you see an open okay the way it is done is one of the reference you create independent of that okay like you put something else and then outputs are picked up at the both ends correct but that is essentially equivalent saying half here and half here minus if I have here just anyway that will come if total is something this I can say half is ascribed plus and minus half is ascribed here which is difference is same that this is all automatically will become difference okay few few sheets and then we will stop maybe today for M1 please have your figure in front of you I repeat this figure you should have it because you have a sheet so you do you look at that V in 1 minus VP that is a VGS is defined as VS V1 and V2 sorry so V in 1 minus VP is V1 which is nothing but VGS 1 and therefore V in 1 minus VN is VP is that correct VGS this is VGS which is V1 which is V in 1 minus VP is last clear V in 1 minus VP is VGS for the transistor sorry I say okay V in 1 minus V1 is VP for the second transistor by same argument I say V in 2 minus V2 is VP so we say both are VP is V in 1 minus V1 is V in 2 minus V2 now let us assume that VA is the equilibrium value of V1 and V2 that differential word now coming and each change by delta V1 and delta V2 delta V1 of this must be equal to minus delta V2 down is that clear this is an average value so if V1 changes like this V2 must change in opposite sense by same value opposite sign essentially saying delta V1 must be equal to minus delta V2 so if I say small signal analysis for this delta means small signal change is always equivalent of a small signal so IDS 1 is GM delta 1 IDS 2 is GM delta V2 assuming M1 M2 are identical however the sum total of this current is always ISS or GM delta V1 plus GM delta V2 0 for delta ISS is 0 that is no change in the bias current so these two current must sum to 0 which essentially trying to say that delta V1 is equal to minus delta V2 so if VA is the average one goes above the other must go by same amount opposite directions from the average value so V in 1 plus delta V in so V into must go by V into minus delta V that is essentially the feature of differential that is what I said so any change in V1 opposite change must come to V2 by same amount opposite in therefore the signs is that okay trivials but that is the concept since we already said that V in 1 minus V1 is V into minus V2 we now define another term V in as the instead of VA for the other side we say now V in is an equilibrium value of V in 1 and V in 2 and if V in changes by delta V in then V in 1 is V in plus delta V in and V into will be differential stage means V in minus delta V in substituting this here V in plus delta V in minus V1 is equal to V in minus delta V in minus V2 collect the terms and you get 2 delta V in V in 1 minus V in 2 is delta V1 minus delta V2 but we already said delta V1 is minus delta V2 or so it is 2 delta V1 so delta V in is delta V1 or equal to minus delta V2 so change in input is essentially absorbed in delta V1 or delta V2 so VP still remains constant so any change is taken clear in the VGS value and not in the VP value is that correct delta V1 absorbs change in V in okay see average value of V in 1 is let us say something so if V in increases beyond this or goes beyond below that so some value from where I am assuming like a DC level plus AC so we say any change in V in from a given value it always get absorbed in that V1 V2 value delta V1 delta V2 and does not affect VP anytime is that correct because we say it is a differential system we already said any change the first earlier one we say change here is same as change here that is the definition we give for differential any change here opposite change must occur the other end which essentially telling by maths also that any change in the input is taken care by change in V1 or V2 science taken care correctly and it does not therefore any time changes VP value is that correct and therefore the half circuit concept which assumes VP is constant okay this is only to prove that my statement I said I am assuming VP constant this is only a proof of saying that VP will always remain constant independent what you do based on this once I now declared that defam I can always assume that change in V in one is compensated or opposite change will occur in V in 2 for a differential stage in that case I will now solve a defam using two separate parts of the symmetry one left one left one right solve independently outputs and subtract and figure it out whether I get the actual defam value which people say this is the value will solve otherwise also defam okay other technique which is the most standard technique but this technique also is valid in defam so why did I show you all this because this gives you a concept of differential modes okay and that is why whole this lemma was proved what is lemma lemma is not a theorem so what is lemma correct so it is the already I used it to prove something but I assumed it and proved it that is what lemma decisions are you assume it is correct or obviously you assume it now so it will be correct okay I start with an assumption which I says correct obviously I already started and proved around everything on that saying oh I came to same point yes you will but that is what all lemmas and theorems prove they start with something and then prove the same thing which they said QED so we will stop here