 Welcome to lecture series on advanced VLSI design. So, continuing with my last lecture on VLSI test, where we discussed about the fault modeling and test generation using algebraic method. And we discussed that algebraic method is a complete method it gives you the test vector if it exist otherwise it tells you that that fault is redundant fault and complexity of both of the processes remain same. The problem that we discussed about algebraic method was that it is not scalable. So, that means, if you have design of multimillion gates you may not be able to generate test using algebraic method. So, then we have to look for the alternate method which are scalable. And so, the algorithmic method is an alternate solution. Algorithmic methods are based on path sensitization which follows three steps a fault sensitization or activation, fault propagation and line justification. There are couple of algorithms given in the literature and some of them I have listed here like D algorithm which was the first complete algorithm given by Roth in 1966 from IBM. Then there was further improvement on that in 1981 by Goyle from IBM and which is called as Podem. Then again the some new concepts were introduced by professor Fujiwara from Osaka University and in 1984 and that is known as FAN. And then so, these in almost in all the automatic test pattern generators we they use either Podem or FAN as the base test generation engine. Then over the years people started to put some more concepts which are more or less based on the learning from the circuits. And two of the examples I have listed here so crates given by Solz and Spirit given by Emil. So, in this course I will briefly describe about D algorithm and then means you can follow Podem and FAN. So, as I mentioned that all these algorithms are based on path sensitization. What does it mean? What is path sensitization? So, let us look at this circuit which has four input and one output it is pretty simple circuit. And now let us say we have stuck at zero fault at line E. So, I have to have find out a input vector that can give me the distinguishable fault T and fault free output at G. So, if I assign 0 at E in that case it can never give me the distinguishable behavior. So, that means here I have to assign opposite value to the fault T value at fault site this is known as fault site. So, now here I have to assign opposite value and that is known as fault sensitization or fault activation. Now I need to assign value 1 at some intermediate point here at the fault site. So, now and I do not have any control over here. So, what I have to do is I have to go back to the primary input and try to find out some input which can justify value 1 here at E and we know that here if I have 1 and 1 at A and B I can get E equal to 1. So, this can activate the fault. So, that means here I in order to activate I need to have opposite value here and in order to do that I have to go back all the way to the primary input and assign this value at the primary input and this is known as line justification because you are justifying that at the primary input line. Now the next thing is I cannot observe the fault effect right at this point because I do not have any observability from this point. So, now what I have to do I have to transfer this fault effect to the primary outputs. So, now in order to do that what I need to do is I have to assign the known controlling value to the other input of this gate right and now known controlling value of this gate is 1. So, that is the requirement for the fault propagation. Now here again I cannot just if I cannot assign any value at the intermediate point. So, in order to do that I have to go all the way to the primary input and I have to assign 1 1 at C and D. Now here if I assign 1 1 1 1 at primary input in that case here this will give me 1 as if circuit is fault free and it will give me 0 if I have to assign 1 1 1 1 at the primary input. So, now here it has 3 components one is the fault activation another is the fault propagation to the primary output and then I have to justify some of the unjustified intermediate values and for that I have to go all the way to the primary input. So, that means primary input means here if you levelize your circuit you go all the way to the input line that is level 0. So, and that is referred as line justification. So, these are the three steps all the ADPG algorithms have to follow fault sensitization, fault propagation and line justification. Now here so, the then basic structure of the any of the ADPG tool would be like this you have to set all the values at primary input as x initially then you justify some value say V at the fault site which is L and then so, this will activate the fault and then after that you have to propagate the fault effect to the primary one of the primary output. So, now here if your V is 0 in that case you propagate means L as D these are symbols I will discuss in a minute what D and D bar mean. So, you propagate this one otherwise if V is 1 in that case you propagate D bar and so, this is the basic skeleton. For example, here in this circuit here say your D is stuck at 0. So, in that case here I assign a symbol D here and now here in order to do that what I need I need to have opposite value assigned to D. So, that means, I have to create a function justify D line as 1. So, in order to do that I cannot do anything here. So, I have to go all the way to the primary inputs and that means, here I have to justify A as 1 and I have to justify B as 1 and since these two are the primary input. So, always you can justify these values. So, your fault is activated. So, now after that you have to propagate this fault to the one of the primary outputs here we have only one primary output. So, now you propagate D to F now here because this is inverting gate. So, D would be propagated as D bar. So, now if D is propagated as D bar at the output. So, in that and in order to do that you need to have known controlling value at E which is 0. So, in order to assign 0 here what you need? So, you have to justify value 0 at E and in order to do that you need to justify B as 1 and C as 1. B is already 1. So, now when you justify C as 1 in that case you are done. So, now here your 1 1 1 is your test vector. Now, if you look at this process in that case here as I said that there are three steps one is fault activation and then fault propagation and line justification. Look at the complexity of the these fault activation for line justification and fault propagation. So, first is fault activation or fault sensitization. So, now in order to means what do we need to do in fault activation or sensitization? I have to assign the opposite value of the fault side. So, now here you need to justify 1. So, and how you can justify? You can justify that by assignment at primary input. So, that means here this problem converts into line justification problem. So, your fault activation is a problem is like a line justification problem. If you look at the fault propagation in this example which we have seen we have only one primary output. It may possible that there would be a fine out point here and then this can propagate this may potentially be propagate to multiple outputs. In that case you have to select one. So, that means here you may need to you need to select a fault propagation path to one of the primary outputs at least and that is a decision making process. So, now here this is a decision making process. It is like you want to go from the institute to the hostel and then if you are not aware about the all the ways you start to follow the sign and then you reach to some cross point and then at some cross point you if sign is not there you have to make a decision which way you should go and then you keep on moving until the next decision point and you make another decision and keep on going hoping that you would reach to the destination or hostel. If your decision is wrong you end up in a forest then you have to come back to the previous decision point and then take the different decision. So, means the fault propagation is a decision making process always you have to make a decision at the fine out point. Once you make a decision after that say once you make a decision here in this case there is no decision there is only one path. So, you propagate it and then you need to assign known controlling value to all the inputs of that gate. So, now here and then you cannot assign any value at the intermediate point. So, you have to go all the way again to the primary input and then this problem converts into line justification problem. So, now here fault propagation problem is either decision making. So, this is decision making as well as the line justification problem. If you look at the line justification problem in again in this small example here when you are you want to justify say 0 here you need to have both 1 1. So, there is no choice this may possible that you may need to assign 1 here in that case here you can have anyone as 0 that satisfies your requirement. So, now your line justification problem is either decision making process or implication. What is implication say if in this gate here if you want to justify output C as 1 in that case always you need to have A and B as 1 there is no choice. So, that is implication. So, if you want 1 here in that case here A and B are 1 this is typically referred as backward implication. If you have say A as 0 and B can be anything in that case output C is always 0 that is forward implication. So, this is the implication, but if you want to assign C as 0 in that case you have choice you can have either A as 0 or you can have B as 0. So, that is decision making process. Now, say you make a decision that A is 0 and then here again A may be intermediate point and then you may want to go back to the primary input and then there may be conflict in between and your decision may be wrong and then you may need to come back again and take assign the alternate value. So, alternate assignment could be like here B as 0 and C can be any value x. So, this is decision making process and so now in the fault propagation you are making a decision in line justification you are making a decision. So, there are couple of decisions you are making and your decision may be right may not be right. In other words your decision may be wrong. If your decision is wrong in that case here you have to backtrack like I told you when you are exploring a new path you if you end up say in forest you may need to come back and then where you will come back you will come back to the previous decision making point and then you have to explore the alternate path. So, that is backtracking. So, now here if you backtrack multiple times it will take more time to reach to the destination. So, in case of incorrect decision you backtrack and then make another decision and then if you reach to the primary output here you say that you are done and then that gives you the test vector. So, as I mentioned you earlier that the algorithm was the first complete algorithm given by Roth from IBM in 1966 it was the complete algorithm complete algorithm means it gives you the test vector if it if exist otherwise it tells you that that particular fault is the redundant fault. So, that means here having that fault in the circuit would not result into malfunctioning of the circuit. This is based on 5 valued logic or 5 valued algebra that 5 valued because here what you want is you want to have distinguishable faulty and fault free behavior. So, that means here when you propagate your signal you have to propagate both of the values faulty value as well as fault free value. So, that means here your logic must have composite value that has fault free value and faulty value and so now here. So, we can have 3 kind of values 0, 1 and x and how many combinations we may have your fault free value and faulty value if you look at fault free value is 0, faulty value may be 0, fault free value is 0, faulty may be 1 this is 0 and this is x. Then your fault free value may be 1, fault is 0 this is 1, fault is 1 and 1 and x and your fault free may be x and fault is 0, x fault is 1, x and both are x's. Now if you look at this in this case both values are indistinguishable always stay to 0 I assign one symbol say that symbol is 0. In this case both values are 1. So, these are again indistinguishable and I assign another symbol say that symbol is 1. This condition when fault free value is 1 and faulty value is 0 I assign another symbol and say that symbol is d. What it represent? This represent your stuck at 0 fault at fault side because here in case of fault it gives you 0 value. In case of fault free signal it is 1 because that you want to assign. This value when fault free is 1 and fault is 0 this is another they just opposite to this and hence here we assign another symbol d bar and all other values where in one value is x. So, that means here we cannot determine what would be that value that may be 1. So, in that case it may be indistinguishable or it may be distinguishable, but we cannot reason about that. So, we club all these values who has access in one symbol that is x. So, now here we have 5 values 0, 1, d, d bar and x. So, now here this is the value this method works on 5 valued algebra wherein the 5 symbols that we use are 0, 1, d, d bar and x. And it heavily uses implications in the forward direction as well as in the backward direction because keep in mind that when you are making a decision there are chances that you may make incorrect decision and you need to backtrack. And so now here when you are making backtrack you are losing time and you need to search more space. In order to backtrack here what we need to do is we have to maintain a stack of all the decision. So, that here when you backtrack you will come back to the previous decision point and then you will freshly start to explore the search space right from that the previous decision making point. So, now here let us look at little bit more in this. So, as I discussed here your it follows all those 3 steps fault sensitization, fault propagation and line justification. So, when you are propagating the fault effect you are making a decision and if your decision is wrong you have to backtrack right. So, now here how do you how do you do? Let us assume that you have this circuit and there is a stuck at 1 fault present at this point at the point where we have arrow. So, now here what I want here I want to assign value 1 here 0 here and in case of fault here this produce 1 always 1 here right in case of. So, whether I assign here 0 or I assign 1 here always it will produce 1. So, now here that I can capture by a symbol d bar. In order to have d bar here after this fault aside here I need to have 0. In order to have 0 what I need I need a must be 1, b must be 1, c must be 1 and this is line justification problem. So, once I have this I will get it. Once you have 1 here in that case here this will imply 0 here right and. So, now here I have choice that. So, from this point this is by implication from this point now there are 2 finite branches one goes to get g 5 another goes to get g 6. So, now I have to make a decision here. So, let us say I want to first I make a decision in favor of g 5. So, that means, here I want to propagate fault effect to f 1 through g 5. If I propagate this and this is non inverting here. So, now here d bar should propagate here as d bar. In order to have propagate this as d bar here what I want this should have non controlling value, non controlling value must is here 1 and now if it is 1 in that case here what I want both of the input must be 0 in order to have 1 here right and because now here you have already assigned 1 here. So, there is a conflict you cannot assign 2 values at single input. So, now here and that arises because of reconversion fan outs. So, now here your fault propagation failed if it is failed then you have to come back to the previous decision making point and make an alternate decision. So, your previous decision making point is here right. Now you have to you already explored propagation through g 5 now you left with only one choice through g 6. So, try to explore through g 6 if you explore through g 6 in that case here this d bar will propagate as d bar here provided that you assign value 1 at the of input of g 6. Now in order to assign 1 here what you need you need this value is already 0. So, if you assign 0 here another input of e in that case here you will get 1 as output of get g 5 and without any conflict hence you are done. So, now your test vector would be a is 1 b is 1 c is 1 d a can be anything x because it does not depend on that and e must be 0. So, now here 1 1 1 x 0 is the test vector which can detect stuck at 1 fault at the output of get g 1. So, this explains the decision making process. So, now here we had to make a decision between get g 5 and g 6 we explored first g 5 we failed we backtrack and then we explored another possibility that is through g 6 and we succeed and it gave us the test vector. So, that means here at every point you have to maintain or a stack wherein at least there must be a d 1 d or d bar must exist in the circuit. So, for that here we define a set that is called as d frontier, d frontier is the set of all the gates whose output value is currently x. So that means output is no determined, but at least one of the input is faulty value that means d or d bar. So, that means those are the potential gates through which you can transfer or propagate the fault effect to one of the primary outputs. So, always at every means any point in time there must be at least one gate in the d frontier otherwise you block the fault effect propagation and hence your algorithm cannot progress. So, and that tells you that that fault is is nonsensitizable or it is a redundant fault. So, this gives you some understanding about how we can make a decision for the fault propagation. Now, another decision you need to make during the line justification let us see how we make decision during the line justification. So, now here say in this circuit you may need to have test for a stuck at one fault at line edge. So, in order to have that I need to assign a symbol d bar. So, in order to excite the this stuck at one fault here h must be 0. If h is 0 then in order to then you have to propagate it and in order to propagate you need to have f as 1 and e as 1. So, if you have both this in that case case here this will propagate as d bar if e is 1 in that case here simply by implication o would be be 0. Now, this is not the primary output. So, you have to propagate to one of the primary output and there is one possibility you have to propagate through this end gate to output as in order to propagate that here what you need to justify non controlling value at q and r and non controlling value for this gate is 1. So, hence you have to have q equal to 1 and r equal to 1. Let us take means now you have to sequentialize it. So, let us take first you want to assign q equal to 1. What do you need to do? Because if q is equal to 1 now here how you this is decision making point because this gate can give you q equal to 1 if either k is 1 or l is 1. Now, let us explore that make a decision in favor of l. So, assign l equal to 1 if l equal to 1 in that case here again you reach to the implication that l can be 1 only when c and d both are 1. Now, let us see what happens if both c and d both are 1 in that case here this c 1 implies m equal to 1 and d is implies n equal to sorry c 1 implies m equal to 0 d implies d equal to 1 implies n equal to 0 e equal to 1 implies m equal to 0 all 3 inputs of this or gate are 0 hence output would be 0 and then this will block the propagation of fault effect. So, now it results into conflict because here you wanted to have 1 here and then you happen to get 0 and so now now you have to go back to the previous decision point. Now, where I made decision was there decision here there was no decision, but when I was assigning one at the input of this or gate I made a decision in favor of l that was wrong. So, I have to make I have to correct that decision or make an alternate choice and that is k equal to 1. If I say k equal to 1 then by implication your a should be 1 and b should be 1 and then there is no conflict. So, now here k equal to 1, a equal to 1 and b equal to 1 give you k equal to 1 that will give you q equal to 1 is still here r equal to 1 is unjustified value. So, in order to do that here what you want at least one of the input of this gate must be 1. So, now here say o is 1 if o is 1 in that k, k, k here that implies that c must be 0. If c is 0, c equal to 0 implies that l is 0 that does not block the propagation because output q is still remain as 1 and now this q equal to 1 is justified r equal to 1 is justified and now here that justifies the propagation of the fault effect to the primary output. Hence, now my test vector is a equal to 1, b equal to 1, c is 0, d can be any value x, e must be 1, f must be 1 and h must be 0. So, this 1, 1, 0, x 1, 1, 0 is the test vector. So, now here in order to track the decision when you are going backward here you need to maintain a set and that set is called as j frontier it is set of all the gates whose output is determined but that is not implied by the input value. So, like here you want output equal to say 0, but both of the inputs are x, x of any gate. So, now here though so through those gate you can justify these values. Now, so now here you made a decision that q equal to 1 from there you made another decision l equal to 1 wherein you failed. So, you came back to another previous decision making point k equal to 1 when you made k equal to 1 then here this objective was justified then you made another decision then r equal to 1 for r equal to 1 you made a decision that m is should be equal to 1 and that succeed and then you are done. So, this way you explored the decision tree. Let us take a small example that consider both fault propagation and line justification. So, let us there is a stuck at 1 fault at this fault side. So, that means just after find out branch here. So, if there is a stuck at 0 fault here we need to have d bar is sorry stuck at 1 fault. So, we need to have a symbol d bar here in order to excite that fault you need to have 0 value at the primary input a and then if then now here your fault is activated you have to propagate that. So, in order to propagate here you need to have non controlling value at b and c and since these are primary input you can always assign these values. So, now here this will propagate this fault effect to the prime to the output of this gate and now this was d bar that can be propagated as d at g. Now here if you look at this is fan out point and then there are 3 fan out branches. So, if you look at the d frontier d frontier consist of those gates whose one of the input is d and output is not determined yet. So, now here one of the input of this gate is d one of the input of this gate is d one of the input of this gate is d. So, now here gate i k and m are in the d frontier you have to choose 1 and pass or propagate your fault effects through that gate. At the same time if you look at the implication if a is 0. So, that means here one of the this input of this and gate is 0 that means here as will always be b 1 by implication. Now you select to propagate your fault effects through this NAND gate. So, if the then in order to propagate through this what you need you need to have non controlling value at the off input of this gate and that is d is the primary input. So, you can always assign one and this will propagate a d bar here. So, now here if you look at the d frontier then like this in one of the input of this gate is already d one of the input of this gate is already d and output is not determined yet and now here one of the input of this gate is also d. So, now here these 3 gates are in the d frontier k m and n and now you have to choose one gate through which you can easily propagate fault effect to the one of the primary outputs and that gate is n because that is pretty close to the primary output. So, now you choose to propagate through this this is inverting gate. So, now here d bar can be propagated here as d. So, now you propagate this as d in order to do that you need to assign all the off inputs to the non controlling value. So, that means, j must be 1, k must be 1, l must be 1 and m must be 1 right. If all these things are there then you can propagate d as on the primary output n now let us see how I can justify that. So, say I justify the first value. So, now say we want to justify j equal to 1 in order to justify j equal to 1 what you need to do because here one of the input to this gate is already 1. So, that means, the other input must be 0 right. So, that means, e bar must be 0 if e bar is 0 in that case here e must be 1 and if e is 1 in that case here this d bar sorry this d will propagate here at k output as d bar and then there is a conflict because you wanted 1 and then you happen to get d bar that is conflict and you have to backtrack. So, now here what do you do in been backtracking. So, you have to come back to your d frontier now in d frontier you have the gate k and m. So, you have to choose 1. So, in order to choose 1 now you want to propagate the fault effect through gate k and now in order to do that in order to propagate through this one again you want 1 here. If e is 1 in that case here this will allow you to propagate fault effect through this one and then this e is equal to 1 gives you e, e bar as 0 and then here j would be 1. Now you will get this h 1 i is d bar j equal to 1 and k is your d bar right. Now here and then here output of this gate is not yet determined, output of this gate is not yet determined. Now again here you have 2 gates in the d frontier one is m and another is n because here there are 2 d bars at the input of this gate. So, now again you need to choose 1 out of these 2 and then of course, you would like to choose gate n because it is closer to the primary output. So, now here in order to do that what again you need you need 1 here and 1 from here. So, say you want to justify 1 here in order to justify 1 here what you want you want f is equal to 1 and when f equal to 1 in that case here that will give f bar equal to 0 this also propagate here d bar, but now here when you have d bar here 1 d bar here 1 and d bar that also at the same time this will give you d at output and now here you are able to propagate d at the primary output and you are done. So, now here what test vector can test this particular fault that test vector is a equal to 0, b equal to 1, c equal to 1, d equal to 1, e equal to 1 and f equal to 1. So, now here 0, 1, 1, 1, 1, 1 is the test vector for this fault. This way we can detect or we can generate test vector for a given fault. And so as I said that this is very directed approach in worst possible case it may need to explore all possible combinations. So, if you look at the complexity I do not want to go in that detail, but this is NP complete problem. So, in worst case it may need to explore exponentially or entire search space, but observation says that most of the time you because this is a directed approach you can quickly generate test and hence this is scalable approach. You can handle large number of gates in a circuit. Then there means one of the issue here is always you need to justify or assign some non-controlling value at the intermediate points and because you cannot assign non-controlling value at the intermediate point you have to go back all the way to the primary input to assign those values. This problem was further looked at by Goyal from IBM and he came up with another algorithm that was known as Podem in which he says that when we cannot assign any value at the primary intermediate point why we are looking at intermediate point why not we go all the way to one of the primary input assign some value forward implicate it and see whether it allows you to propagate the fault effect or not if it does not allow if it blocks then you change that value and that algorithm Podem became almost 100 times faster than the algorithm. Then further the problems of Podem algorithms were or in other way I should say that some of the new concepts were introduced on top of the Podem algorithm by Professor Fujiwara that is known as fan out oriented test generation and that was almost 100 times faster than the Podem algorithm. So, these are the various algorithms you can go through the literature and look at the various recent algorithms and as I said that here most of the test generation engines are based on either Podem or fan mostly fan. This summarizes the decision making process you can look at all the steps that we discussed earlier. So, these were the this was the decision tree which we made here in earlier the your D frontier has gate k l m then we have chosen one and then l and then we introduce another gate n in the D frontier we had chosen n we failed then we came back to the previous decision point wherein you had m and n in the D frontier you had chosen n again you failed then you come back and had chosen m and then you succeed. So, now here there were 2 back tracks in this. So, now here as I said that theoretically test generation complexity of a combinational automatic test pattern generator is NP complete, but observation says that you can generate test in reasonable time. The big problem is redundant faults. So, if fault test vector axis these algorithms can generate test vector pretty fast, but if it is redundant it may need to not necessary all the time, but may need to explore the entire decision tree and that may not be practical. So, now in general what these practical ATPG tools does all these practical ATPG tools are based on is they keep a back track limit if say a back track limit is 1000 then if it exceed 1000 it will abort that and idea is that most of the time again keep in mind I said most of the time most of the time that fault may be redundant fault, but it is not sure and that is the reason we it is difficult to get very high coverage that means 100 percent fault coverage because we have to about that if your decision making points are exceeding or back tracks are exceeding beyond the assigned limit. So, that means if your abort limit is lower you can generate test quickly because then if it exceed beyond that limit it abort that and generate test for the next fault. If you increase the abort limit it will take longer time and then here this time is not proportional it grows exponentially. This was the test generation for combinational logic. Now in general we do not have combinational circuit we have sequential circuit and how sequential circuits are different from combinational circuit sequential circuits have additional memory element in that. So, now the bigger problem we may end up to is your fault effect may propagate to the flip-flops or memory elements rather than propagating to one of the primary outputs. Look at the structure this is your combinational logic and this is your flip-flop you are getting input from this one these are your primary input primary output these inputs from the flip-flop are known as pseudo primary input and the output from the circuit which are going to the flip-flop are known as pseudo primary output. So, your fault effect may fault may be here and then this may propagate to the one of the pseudo primary output and I cannot observe that. So, now here what you need to do you have to run your circuit again. So, the until the time when you it propagates to the primary output where you can observe. Another issue is that here when you are generating test for this you may demand some value from the pseudo primary input or from the flip-flops and that those flip-flops may be in any state when you are when you power up your circuit. So, that means here you have to initialize your circuit to some fixed value in the primary in this flip-flops. So, it demands. So, test for a fault in the sequential circuit is a sequence of vectors rather than a single vector and that sequence comes from first thing is you need to initialize circuit to a non-state then you have to activate the fault and if that fault effect is not propagating to the primary output and propagates to the one of the pseudo primary output in that case you have to run your circuit in several cycle to propagate the fault effect to the primary output. So, that means here you need a sequence of vectors rather than a single vector. In order to handle this problem there are two methods one is the time frame expansion method another is simulation based method time frame expansion method I will explain you briefly. So, let us look at this example this is brief example say the I guess all of you are familiar with the serial adder this adder has say two inputs A and B and then two outputs one is the output and another is the carry. So, now here carry would be storing the flip-flop and then every cycle you are getting new inputs and giving the output of that cycle. So, now here say there is a stuck at 0 fault here for a stuck at 0 fault here what you demand you demand 1 from here and then by implication you say that A n and B n must be 1. In order to propagate this fault effect here there is a D and then here propagate that as D bar here what you demand you demand 1 from here that is fulfilled by implication A n equal to 1 and B n equal to 1 will give you this as 1. Now your fault effect is here. So, now here there are two part you can you have to propagate that fault effect through this gate or through this gate. In order to propagate you need to have known controlling value here. So, here there must be 1 and here there must be 0, but because your circuit can power up in any state in that case here you have x and then once you have x here as 1 of the inputs to these gates output would be x and then your primary output would be x and then you will assign value 1 in the flip-flop. So, that means, here you are not able to propagate fault effect to the primary output if you start from value x. Now, here what is the solution and solution is that here you have to initialize this flip-flop into a non-state and that non-state is 1 that you are demanding. So, that means, here you have to unroll your circuit in multiple time frames. Unroll means here you have to have 2 copies of this circuit. 2 copies of this circuit does not mean that you implement or fabricate 2 copies you are fabricating only 1 copy of the circuit, but now here for the test generation purpose you replicate that copy. So, now here in this and in both of the copies because here the same fault accessed here as well as here. So, now in order to excite that here you need to have 1 as input from here and then you are demanding 1 from this one. In order to have 1 here you need to you demand 1 from here and in order to demand 1 here you need to have 1 and 1 here. So, that means, here you need to have a sequence of 2 inputs 1 1 followed by 1 1 that can test this fault. So, that means, here this tells you that how complex test generation for sequential circuit is. So, here what we need to do? We need n vectors. So, we need to replicate our circuit n times and now here the same fault may exist in n copies. So, that means, in total combination of circuit that I have, I have n number of faults. So, now here this is the instance of multiple faults rather than single stack at fault. Now, the time when I excite the fault that we say vector 0 and then here time frame that we used to initialize our circuit we call at minus 1 minus 2 minus 3 minus n and how many times I need to unroll I need to unroll until I reach to a point wherein I start from all axis from the memory elements or flip flops. And then here because the fault effect may propagate to the pseudo primary output in that case again I need to unroll and I need to unroll until I am able to propagate fault effect to 1 of the primary outputs. So, I need to unroll it multiple times. So, now here the typical ATP implementation select the 1 of the primary output based on the drivability I skip that for a while, but here say to randomly 1 of the primary output it places logical value 1 or 0 or 0 or 1 depends. So, these are the composite values d or d bar depending on the fault type. You justify output from the primary inputs considering all necessary paths and adding the backward time frames. If justification is impossible in that case you need to select another primary output to propagate and you repeat all these things. If your procedure fails for all reachable primary output in that case here you have to say that fault is untestable. Now here you are unrolling this in multiple time frame and now the question is in worst possible case how many times you need to unroll it and this gives you some scary numbers. Your circuit may be cycle free or may have cycle. So, that means, here you may have feedback or you may not have feedback. If circuit is cycle free in that case you need to unroll your circuit maximum sequential depth of the circuit plus 1 and sequential depth of circuit is defined as maximum number of flip flop appears in any pair of input output. So, if you say in one of the path if there are maximum 3 flip flops are appearing in that case here total force psi you need to unroll your circuit and you can easily understand that because if your circuit has sequential depth 3 that means here in 3 time frames you may be able to to initialize all the flip flop because there is no feedback there is only feed forward. If circuit is a cyclic circuit and there are n number of flip flops in that case here you need you may need to maximum unroll n raise to the 9 raise to the power number of flip flop times. That is really scary figure because assume that you have only 2 flip flops then you may need to unroll it 81 times. 2 flip flop circuit is pretty small circuit though these numbers are a scary, but most of the time you do not need to unroll that many times you need to unroll pretty small number of times than the these numbers, but in order to give a guarantee you need to explore explore this. So, now here it is very very very difficult to generate test for reasonably large sequential circuit if it has cycles involved in this. Now, what is the solution? And solution so now means the difficulties are poor initializability of the sequential circuit, poor controllability or observability of state variables because you cannot directly control or observe those variables gate counts and number of flip flops are increasing and then sequential depth is increasing and cycles are main responsible for this complexity. If you look at the test generation time and fault coverage so if you have a small circuit then traffic light controller that has as 355 gates and 21 flip flops and sequential depth is say 14 in that case here ATPG time would be something 1247 seconds and fault coverage is still 89 percent whereas the another circuit here you have chip A that has pretty higher number of gates and number of flip flops and sequential depth is 14 but here is still it needs less number of so now here what does this slide tells you that gate count and number of flip flops are really not the determining factor. It is the sequential or cycles which are determining the how much time or how complex this process is. If you look at some of the benchmark circuits some circuits are these are RISCAS 89 benchmark circuit this S 1196 and S 4996 so these two first two circuits are cycle free circuits and last two circuits are cyclic circuits. Though here all are having the similar kind of flip flops like here the cyclic circuits do have 18 flip flops and cyclic circuits do have 6 flip flops. Now you can see the test generation time a cyclic circuit it takes 10 to 15 seconds whereas the cyclic circuits are taking about 20,000 seconds so huge difference and hence here it is not practical to generate test for a significantly large sequential circuit. So, you have to adapt some other technique and as we know that this complexity is coming from the cycles in the circuits and poor initializability and controllability of the circuit. So, if we happen to initialize circuit by any random value and we can observe any value from the flip flops you can always use the same combinational ATPC to generate the test and then your test generation complexity is same as the combinational circuit test generation complexity. With this I stop here today we will continue with the test generation for sequential circuit in the next class. Thank you very much. Good day.