 In our single-cycle architecture, the idea of clock-cycle time and latency was pretty simple. We just saw how long it took to get one instruction all the way through the architecture, and that was it. That told us how long our clock-cycle time needed to be and what the latency for an individual instruction would be. With our pipeline architecture, the matter is a little more complicated. Now we've got five different stages that our instruction needs to go through in order to complete, but our clock-cycle time won't just be one-fifth of that total amount of time because different pipeline stages may take different amounts of time to complete. So in this case, our clock-cycle time is going to be determined by the largest stage, whichever one takes the most amount of time to complete. Then, because every instruction must pass through all five pipeline stages before it's complete, the latency for one instruction will be five times the clock-cycle time. As before, the load-word instruction still uses the most hardware, but we're not going to be able to skip any stages, so all of our instructions are going to take just as much time to complete in this case.