 Hello everyone, welcome to lecture on VHDL module for flip-flops. At the end of this session, students will be able to analyze, design and implement flip-flops. Now before starting with the actual session, let's pause the video and think about what is the attributes. Now the attributes are nothing but which is allowed to extract additional information about an object. For example, if you are having a signal in your VHDL module or in the VHDL code, that signal's additional information is nothing but whether the signal is having positive edge, what is the value of that signal, whether it is negative edge, whether the event is occurring on the signal or not, right. So all that nothing but the additional information of the signal, what is the last bound of the signal, what is the first bound of the signal, high bound of the signal or what is the left bound of the signal, what is the route bound of the signal, these are nothing but the additional information or attributes of the signal. Also as I said an attribute is a value or it is a function, it is a type, it is a range, it is a signal or it is a constant and there are two types of the attributes, one is a predefined attribute and another is a user defined attribute, right. You going to get it that how those attributes are there while we going further in a session, right. Now let us start with the flip-flops, starting with the D flip-flops, this is the D flip-flop, everyone know that this one is a basic flip-flop of your digital design system, you can say that. You can see over here, there are inputs and outputs, inputs are nothing but the clock, D and RST that is nothing but the reset and output is nothing but the queue. Everyone knows the working of the D flip-flop is that whatever the input you are applied on the D will get on the output side that is queue whenever there is a clock event occurring. That depends whether you are having positive H clock or negative H clock, that can be considered while writing the VHDL model. So let us go for the VHDL model, now while writing the VHDL model you have to keep in mind that there are three main part of the VHDL model, first part is a library declaration, second part is a entity, part and third part is a architecture part, right. So first part library declaration in that which library you are using you have to mention that one, from that library what are the packages you are using that also you have to mention. So here I mentioned that I am using library IEEE, from that library I am using package STD logic 1164, this is the package name and from that package I am using all the possible all whatever the declared in that all components I am using. So these two lines supposed to be there, compulsory lines are there, you have to use that one, if using you other than this library if you are using any other library that is for example work library, so that also you have to mention, when you are doing the programming part or VHDL model for writing in a further more complex circuit in that case you going to use that work library, now for D flip flow it is ok with the IEEE, then second part comes is the entity part as I said, so entity this is the syntax entity keyword you have to use then entity name supposed to be there is port, in the entity port declaration is there, port declaration is nothing but the what are the inputs and output to your system or design for which you are writing the VHDL model. So we know that what are the inputs to the D flip loop, so inputs are clock reset D which is a so direction is in and now here it is mentioned that STD logic means the value is not defined initially undefined, if you I write over here instead of STD logic if I write over here bit means it is a type of bit it is having value either 0 or 1, now here it is not bit, so that is why it is STD logic mentioned, so that is why it is when I go for the simulation it shows the undefined right, output is one output that is Q again STD logic, so output is also still not defined what is the type of that, if I write bit over here means it is having either 0 or 1 value, then once you done with the port declaration part you have to end the entity, so end entity entity name supposed to be mentioned, after that architecture third part of the VHDL model architecture architecture name of entity name, same name supposed to be there is architecture begin, now you have to write the here behavior of your D flip flop, how your D flip flop works, so here we have to write inside the process because we using clock, so process then in the in the bracket sensitivity list there that is a clock signal is used then process begin, now here if clock tick event and clock equals to 1, now the tick, so this is a called as a tick clock tick event, event is nothing but the attribute we just saw at the starting of the session what is the attribute, attribute is nothing but the additional parameter or additional information about the signal, if now this can this attribute is nothing but it is checking whether the event is occurring or the not on a signal on this particular clock, if event is occurring and during that event if clock equals to 1, then we are going further, if event is not occurring or clock is not 1 we are not going further, now we if these two conditions are true let us go for a second, if reset is 1 my output is 0, if it is not else part is my output equals to D, Q equals to D and if and this if end process and end architecture, this is the flow to write the VHDL model for D flip flop, you can verify this model with the help of simulation this is the simulation output, see as I said because of while writing the entity part I have used STD logic for inputs and outputs, so that is why it is values undefined, so showing the signal is in a brown color or you can say orange color, once I started the clock over here it is showing pulses right, now because of the simulation time I just compressed, so it is showing the compressed version of the signal but it is having pulses over here crowded one, after that I make a reset signal 1, but because of that a reset 1 my clock output is 0, then I made reset 0 and if D equals to 0 output 0, still reset is 0 means if I change D to 1 output is 1, so whatever the value and D when the reset is 0 that value get reflected on output, if the reset is 1 your output is still 0 right, so this is how you can verify the simulation of the D flip flop, now let us go for the JK flip flop, this is the JK flip flop everyone having the familiar with that one, similar to D1 only the inputs here J and K, another additional inputs are preset clear, output is Q and one more output is Q bar, it is a you can see inverted version of the Q right, so we know the JK flip flop let us go for the VHDM module for that, as I said three important parts a library declaration entity and architecture, so a library we already saw entity is nothing but entity entity name port declaration inputs and outputs, reset clear clock JK are the inputs, stereologic Q and Q bar are the outputs, now here Q is mentioned as a in out, why because for Q bar to generate the Q bar you have to apply a Q you have to use Q as a input, so that is why it is mentioned as a in out to generate the Q bar, you will understand while writing the architecture, so once you done with this part architecture, architecture name of entity name, architecture begin, now the process inside the process sensitivity list is there, preset clear clock these are the sensitivity list, then process begin, now first condition if clear equals to 1, in that case my output equals to 0, but after 10 seconds additional part I am writing over here, you can use the delay in the VHDM module right, if this condition fails let us go for the second one, else if part is again, if preset is 1 output is 1, but after 10 nano seconds, if both condition are false both signals are 0, in that case I am checking whether the clock is there, clock event is occurring and clock equals to 1, 0 sorry clock equals to 0, then my Q equals to now this is the whatever the Boolean expression you are having over here, that you can get with the help of truth table, if you know the JK truth table, you can easily, so Q is nothing but J ended with the not of Q, now here not of Q, means you are using Q as input right, so that is why we used in out, then which is odd with the not of K and Q right, but and this whatever the result you are getting, that result is assigned to Q, but after 10 nano seconds right, you will get this in the simulation, then end if this if is ended over here, then end process, after process we have to update the Qn signal, because the Q only we considered over here, so that Qn is nothing but the not of Q, that is a Q bar and then end architecture, that is the architecture name, so this is the VHDL module for JK flip flop, you can verify with the help of simulation, so this is the simulation window, now here you can see that while I am talking about the delay 10 nano seconds here, if I make preset clear one, clear one over here, it is ended over here, in that case the output is it started over here, but after 10 nano seconds the output is 0, when clear is 1, here I make clear 0 and preset 1, but after 10 nano seconds output becomes 1 and the Q bar is inverse version of your Q, so whatever you are having inverted version is below that right, so this is how you can verify the VHDL module for device or design for you generated with the help of simulation, these are the references, thank you.