 Hello everyone and thanks for attending this webinar. My name is Estella Starr and I'm glad to start this seminar about EMC systems immunity against ESD. As an introduction, let's define what is EMC immunity and what it means for you when you design an electronic printed circuit board. EMC stands for Electromagnetic Compatibility. EMC immunity is the ability for an equipment to properly operate in its electromagnetic environment by limiting the reception of electromagnetic energy that may cause physical damage. Electrostatic discharge called ESD falls into this category. ESD can be either conducted under the form of a transient voltage, but it can be also radiated due to its fast rising time, generating harmonics over full enough to generate erratic behavior of your application by coupling with other signals. It means that ESD is a threat against which your printed circuit board must be protected. Here is an example of EMC immunity. By testing my correctonics, we ensure that our printed circuit board embeds ESD protection for all connectors that may be subjected to electrostatic discharging. As you can see, there are many ESD protection references in this board. So for HWPCB and designer, it can be a tricky job to select the correct ESD protection according to the connector. So let's review today what ESD protection that system level means and what are the different standards behind them will explain you the selection steps for the ESD protection component. And finally, we will detail the layout guidelines to properly fit the ESD protection in your design. In this first part, I would like to remind you how ESD is generated in everyday life and why we should care about it in our electronic applications. ESD is a result of static electricity discharges. Static electricity is a collection of electrically charged particles on the surface of a material. Various materials are the tendency of either giving up electrons and gaining positive charges or attracting electrons and gaining negative charges. The list of these materials in the order of how much they become positive or negative is called the triboelectric series. The discharge of tens of kilovolts may occur and the arc that appears is called ESD. Here are some examples of voltage levels. For instance, walking across a carpet is the worst case generating up to 35 kilovolts of energy charging that amount into integrated circuits is not without risk. Electrostatic discharge will cause potential failure on the integrated circuits of your PCB. These failures are called electrical overstress or EOS resulting in silicon melting, oxide punch through, junction damage, metallization damage or degradation affecting the long-term reliability of your electronic system. A survey from the EOS Industry Council showed that 30% of customer claims are due to ESD or EOS and furthermore the miniaturization of the components is increasing the integrated circuit sensitivity to ESD. Here is a graph showing power supply voltage VDD and breakdown voltage VBD of various semiconductor technologies used for integrated circuits. The breakdown voltage VBD and the power supply line VDD are decreasing year after year. The ESD design window that is the difference between VBD and VDD is also decreasing drastically from 8 volt margin in 1999 to only 2 volt margin in no-dose technology. This illustrates that ESD sensitivity is increasing in integrated circuits and that it is necessary to protect these sensitive devices with a specific external ESD protection. Now there are different standards for ESD and two major cases. The first one on the left side is related to component level ESD. This is to ensure the manufacturability of integrated circuits. These standards reproduce ESD during manufacturing processes which means the ESD risk is mitigated by using specific equipment in a controlled environment for manufacturing. For instance, technician can wear anti-static shoes and they are deionizer to avoid air charging. Each person or equipment must be connected to the ground in order to allow a discharge path. The related standards are HBM, human body model, that simulates ESD to discharge from human being, MM, machine model, that simulates machine ESD discharging through a device to ground and finally CDM, charge device model, that simulates ESD due to mechanical device handling of ESD protection according to the standard concerns in the integrated circuits. It is called unshipped ESD protection. The second case on the right side is related to system level ESD and this is a case that occurs in our everyday life. The IEC 61-4-2 standard simulates a whole system that may be subjected to ESD. For instance, working on a carpet with a veneer suit who generates, on a dry environment, several tens of kilovolt of electrostatic discharging as presented in the introduction. In this case, the only way to manage an ESD event is to add a dedicated ESD protection mounting on the PCB and placed in the critical discharge path. The automotive standard ISO 10605 is also part of system level ESD. What are the main differences between HBM, human body model, and IEC standards? From our experience, people do not often understand the difference between these two standards. On the left side, the electrical circuits modernize the equivalent ESD waveform associated to each standard. The IEC standard is modernized by a larger capacitance discharge, 150 picofarad for IEC, against 100 picofarad for HBM. And this capacitance is discharged through a much lower resistor, 330 ohms for IEC compared to 1.5 kilo ohms for HBM. On the right side, we compare the energy carried by the current waveform of these two standards. For the 8 kilovolt IEC, the current is in red here, and with some 8 kilovolt voltage, HBM current is in green. For 2 kilovolt HBM, that is the most common level specified for integrated circuits, we obtain the blue curve, the energy of ESD that corresponds to the surface below the curve. In much lower than for 2 kilovolt HBM compared to 8 kilovolt IEC 61000-4-2. As a consequence, IEC 61000-4-2 carries more energy than HBM. This is why integrated circuits exposed to ESD and specified with HBM will still require an external ESD position rated per the IEC standard. Now you may wonder why integrated circuits do not feature system-level ESD protection. So let's try to figure out what would be the size of the system-level ESD protection integrated in an IEC. Here we show two integrated circuit protection layouts using the same scale thanks to pad surface. On the right side, you can see the size of an IEC protection 8 kilovolt, which is much bigger than the size of the 2 kilovolt HBM protection at the left. This means integrating 8 kilovolt IEC protection is not cost effective in expensive advanced MOS technologies. This is why the system-level ESD protection is kept external using specific silicon technologies. Now let's review the IEC 61000-4-2 standard. This is a system-level standard. It is not related to components, so it applies to a complete application with its enclosure. This standard defines four stress levels and four levels of results. The most severe level is level 4 with 8 kilovolt contacts and 15 kilovolt air applied. The test result is rated A when the device and the test performs normally without any disturbances. At ST microelectronics, all ESD protection components comply or exceed this level 4. For automotive applications, the ISO 10605 standard applies. It is more severe than IEC standard because of the higher capacitance used for this charge, 330 picofarad instead of 150 picofarad for IEC, a higher number of discharges, 50 instead of 10 for IEC, a higher frequency to apply the ESD pulse to the components, and finally, the higher level of supply voltage up to 25 kilovolt at contact in charge instead of 8 kilovolt for IEC. On top of specific semiconductor reliability testing, automotive ESD protection are usually priced either than ESD protections used in consumer or industrial applications. So now let's review how to sell the right ESD protection components for your application. Thank you Estelle. Now we will present on this section the key parameters of an ESD protection. Oh, these parameters can impact your system performance and at the end, I will give you some basic advices to sell the right ESD protection components. Here are the key electrical symbols and abbreviations you will use so that you can get familiar with the vocabulary. Let's review in detail each parameter. The RM stands for Maximum Reverse Voltage. It corresponds to the maximum voltage of the protected line or normal operating condition. It is associated to IRM, the leakage current of the ESD protection. The current is very low to not impact the system consumption. It is typically much lower than 100 nm. ESD protection starts to conduct at breakdown voltage or VBR. This static voltage is usually measured at 1 milliamp. It can be used to validate that the ESD protection is well mounted on a pretty circuit board. During an ESD event, the surge current is flowing into the ESD protection. The maximum current that can flow into the ESD protection is called a peak surge current. The associated voltage is called a clamping voltage, VCR. The clamping voltage is the remaining voltage measured at the ESD protection. The lower the clamping voltage, the better the protection efficiency. The left key parameter is line capacitance. In the frequency domain, an ESD protection can be modernized with a diode with junction capacitance. This capacitance can impact the signal line integrity as any extra capacitor placed on a signal line. An ESD protection can be unidirectional, like a V-curve on the left or B-directional, like a V-curve on the right. Here is the principle of Cranjant voltage supercell, also called TVS. Keep in mind that ESD protection is subclass of TVS. Let's consider an electrical signal in blue. This is a voltage curve, function of bar, without TVS. Unfortunately, at a voltage higher than the solution value, the system stays. To avoid this system failure, a protection is required. TVS is then used to clamp the voltage in pink and then to protect the system. At VBR or breakdown voltage, the TVS starts to conduct in green. The QN flows into the TVS and the resulting voltage is a clamping voltage. The forward voltage, VF of the TVS, clamps the negative signal for unidirectional protection. Another key parameter is the leakage current of the TVS itself. In the IRM, defined at maximum reverts, DC voltage on normal operating condition, VRM. In case of signal polarity, which is both positive and negative, the TVS might be B-directional. In B-directional TVS, the voltage thresholds are usually the same in both directions. The ESD protection must protect the IC of the application, but must not impact the application in normal operation. For example, the paratheistic capacitance of the ESD protection device must be low enough to allow HDMI 1.4 pK bit per second USB signals to be transmitted without degradation. The high paratheistic capacitance of the ESD protection device would increase too much to signal a rise and fall time and prevent good communications. In one word, if the capacitance is too high, the rise and fall time will be too high and then the signal integrity will be impacted. To guarantee this digital signal integrity, the following equation is used with FC cutoff frequency and TR rise time. The ESD protection cutoff frequency must be lower than the application operating frequency. Lower capacitance allows larger bandwidth and a better signal integrity. In our example, we can see that the orange curve representing 5 pK power capacitance is too high for the HGMI 1.4 pK bit per second signal. We can also see that one pK power DC protection capacitance is OK. Indeed, high diagram or A pattern measurement is a tool to characterize transmission quality. In digital communications, the high diagram is used to visualize how waveforms used to send multiple bits of data can potentially lead to errors in the interpretation of dot bits. A high diagram is produced by repeatedly sampling a digital signal on oscilloscopes that can act as wire, triggering the odd horizontal sweep with the data rates. A digital signal is often defined with the use of a mask here in Boo. The mask usually consists of polygons in the middle of the eye and rectangles above and below the eyes. If the measurement measures traces across the mask boundaries, the signal quality is considered unacceptable. ISP buses, standards like HGMI, USB and so on, often specify high diagram masks. If measure traces across the mask boundaries, the signal quality is considered unacceptable. On the test sheet of the easy protection for ISP buses, high diagram are reported for value standards. In this example, USB 3.4 engine 2 at 10 Gbps per channel is reported. The measurement is performed on a line without easy protection on left and with easy protection on right. In the second view, there is no impact of the HSP 063 that 4M4 on the USB 3.1 at 10 Gbps per channel signal. The signal integrity is respected. Another key parameter for ISP buses is the time-domain-reflectometer impedance, or TDR impedance. It is specified on the standards where long cables are used, such as HGMI, but it is not mentioned on any USB standard. The TDR impedance is measured thanks to an incident step with well-controlled lifetime that is respected on the unmatched load. Both signal are measured with the eye bandwidth and eye sample rate otioscope, and the post-calculation extracts the impedance of the load. ISP is also reported on data sheets of easy protection for ISP buses according to the standard constraints. As an example, a line without HSP 063 that 4M5 is characterized according to HGMI 2.0B TDR spacing. For analog signal, S21 parameter on dB is also reported on data sheets. It corresponds to signal attenuation due to the protection. As an example, SDA RF021BU2CK can be used to protect antennas. It has a negligible impact on major frequencies used for wireless telecommunications. Now let's focus on ISP protection quality. The key parameter is ISP response to an electrostatic discharge of 8000 volts. For example, ISP 051 1BF4 temporal response is presented. There are two noticeable values. The first is a peak voltage at the beginning of the response. It's a low energy impact peak due to the duration of 29 seconds. It was formed corresponding loosely to CDM ISD event. For ISP 051 1BF4 is 23 volts. The second is a clamping voltage defined at 39 seconds. It's 11 volts for the ISD 051 1BF4. It's much more energetic due to the duration. This temporal response at AKV is usually reported on data sheets because it corresponds to the IC61000 TDR-2 Level 4. To perform ISD analysis, transmission line pulse is used. A square current pulse of 100 nanosecond is injected into the production. The remaining voltage is then measured between 70% and 90% of the incident pulse duration. For ISD 051 1BF4 with 16 amps incident current, the TLP voltage is 10.5 volts. It's about a clamping voltage measured with AKV ESC 61000-4-2. With several pulses at various incident currents, it is possible to make a TLP ID curve. For example, ISD 051 1BF4 TLP ID curve is presented on the same graph as the TLP ID curve of microcontroller input is put in blue. Three voltages are noticeable for MCU. The first one is a working voltage 3.3 volts. The second one is absolute maximum writing of this input of 5.5 volts. The third one is the MCU distribution 12.5 volts. TLP distribution voltage of this microcontroller is a yarn on AMR because TLP duration is only 100 nanosecond while AMR is continuous. This graphic shows that current coming from ISD events is shared between MCU internal protection and ISD 051 1BF4. When the sum of current into the ISD 051 1BF4 and MCU is higher than 16A, the system can resist to AKV ISC 61000-4-2. This is a system efficient ISD design methodology or seed methodology. The approach shows the current repetition between external ISD protection and the protected pin. Instead of standard ISD protection, green TLP ID curve, and SNB ID protection can be used. Red TLP ID curve SNB protections present lower clamping voltage than standard protection thanks to the SNB effect that lowers the clamping. Once the protection has turned at 16A, the ISD ZV file 1BF4 presents a clamping voltage merely 2V lower than ISD 051 1BF4. But the protected line DC voltage is present, must be lower than holding voltage of the SNB ISD protection. Indeed, if DC voltage is higher than holding voltage and if ISD event is present, the protection will turn on and the current coming from the DC voltage source will flow continuously into the protection. The protection will then be large. If no DC voltage or no DC voltage higher than holding voltage, there is no large risk. To select the right ISD protection, three parameters must be validated. The ISD protection must be transparent for the application to do so. The protection capacitance must be in line with the application bandwidth or analog or data type. Discounts are reported on the data sheet. The ISD protection must be efficient when ISD event is present. TLP IDQ are present on the ISD data sheet, but there is no TLP information on the circuit to be protected. To select the protection with a good clamping, it is recommended to select an ISD protection with a wiring just above the maximum line voltage. To avoid snapback protection last step, once turned on, holding voltage must be higher than DC line voltage to grant a good system integration. All these information are available on the application notes, fundamentals of ISD protection as system level on ST.com. Thank you, Matthew. Some requirements are becoming more and more well-known and are often defined by rules or standards, as we described so far. To satisfy these requirements, there is in the majority of cases a standard solution or a dedicated protection product. However, knowledge of the disturbances and the use of a suitable protection devices are not sufficient in themselves to solve the problem. In many applications, the correct design of the PCB layout is essential for success. Let's have a look on a particular example for the PCB layout consideration. Let's try to understand why it is very important to have the application PCB layout under control for a good ISD robustness. The circuit presented in this figure shows the classic approach for the protection placement in the application circuit. Here, the protection device is located between the connector and the IC device we want to protect. What is not visible in the first view is the fact that during the ISD disturbance, the PCB track impedance starts to play an important role. High current and the trace impedance causes unwanted overvoltage at the protected IC pin. Depending on the PCB technology, the PCB track impedance of around one nano Henry per its millimeter of length is introduced. This problem is specifically important for the PCB track part colored in red in our figure. Let's consider for the next exercise that the single PCB track inductance L is 5 nano Henry. When an ISD disturbance occurs on the PCB track from the connector on the left side, the protection device clamps the surge at its maximum clamping voltage and thus we expect it protects our sensitive IC. It's not really true in this particular PCB layout because during this clamping action there is a high current going through the protection device and also through the PCB tracks around it. This phenomenon introduces a voltage on the PCB tracks equal to the track impedance and the current change. If we consider 5 nano Henry inductances and the current change of 37.5 amps per nanosecond, the resulting VIC visible by the protected IC pin is simply a sum of the protection device clamping voltage and the voltage introduced on the PCB track. In our case, the VIC is 100 of volt and apparently these levels can be still crucial for the protected IC. So what should we do? The solution is simple. Our application PCB tracks must be under control. In particular, we have to shorten the PCB tracks and route them through the protection device pins as visible in the figure. Connections to the ground must be also short and specifically the wires to the ground planes must be as close as possible to the protection device and to the protected IC ground pins to limit the parasitic inductances. In detail view, the PCB tracks inductance stay out from the risky area and does not contribute to the potential over voltage visible by the protected IC pins during the ESD event. With the optimized PCB layout, the VIC on the protected IC pin is the wanted clamping voltage of the protection device. It is also recommended that the protection device is located as close as possible to the disturbance source. In our example, close to the connector. For more detailed information on the PCB layout recommendations for your ESD robust application PCB design, you can consult our application note called AM1751. Now, let's have a look through several application examples showing recommended protection devices for particular application cases along with the recommended PCB layouts. The application core product is usually a microcontroller. It features many peripherals which are in the final application naturally exposed to the surrounding environment. As an example, we all know many different communication buses like USB, RS232, Ethernet, with their connectors accessible to outside environment. We have also audio connectors, slots for the memory card or just a simple push button in our applications. All of these peripherals should be protected in an ESD robust design. Let's go now through several concrete examples. First example is the USB connector which should be equipped with a protection device which is capable to protect the microcontroller pins against ESD. But also, at the same time, the protection device should not introduce high capacitance to the communication line in order to stay compliant to the USB-I diagram. USB LC6 protection device can do the job and you can find recommended schematic and PCB layout at our reference designs for STM32-L4 microcontrollers. Similar for RS232. In this case, the RS232 transceiver is the most exposed application IC outside the application through the connector. And also, in this case, as it was mentioned for the USB connectivity, there are two main functions or needs for the protection device required. The first one is the ESD protection functionality itself. The second requirement is again the capacitance of the protection devices itself introduced to the communication line which must be low to keep the RS232 protocol compliant. Also, in this case, you can find recommended schematic and layout in our STM32-L4 reference board resources. Last example we selected are the user button and consequently protection of the microcontroller GPIO inputs. Also, these mechanical buttons, being part of the application, are exposed outside to the environment. The buttons are not made from a conductive material. Nevertheless, they are still highly sensitive to the ESD and they are also stressed during the IEC certification test. Beside the ESD robustness level, such protection device requirement is usually also on the size of the package to keep the PCB space occupation small. The small package size is often a general customer requirement for any protection device. Now let's have a closer look on concrete application boards. The first mentioned already at the beginning of our webinar is showing the ESD protections suitable for our STM32 MP1 microprocessor. As you may see, all exposed connectors are equipped with ESD protections. In addition to the connectors, we have also added protections to other sensitive areas such as the user input buttons and the SD card slot. The protections added to this board ensure system level protection in compliance with the previously mentioned ESD standard IEC 6100-4-2. Any electronic board must be protected. This second example is showing a 3D printer control board. On this board, both input power lines of 12-wall and 24-wall are protected against search, means according to IEC 6100-4-5 as you can see on the left side of the PCB layout. In addition, there are several ESD protection devices on the board. ESDA 5V3L is used for the user button. EMIF 06 is protecting the SD card slot including also the EMI filter. And finally, the USB LC6 protection devices are used for all 3 USB connectors populated on the PCB. We have mentioned some application notes already in our webinar. Here is the recommended list of out-document you may check to make your application designer robust and optimized from the beginning, means already at the schematic level. We also invite you to watch our additional video about ESD protection explaining why and how you can protect your application ICs. For example, the microcontrollers in an efficient way. ST Protection Finder is the software application available for Android and iOS that allows you to explore the ST Protection portfolio. You can easily define the device that best fits your application using the parametric or series search engine. You can also find your product thanks to the efficient part number search engine. To find the right device for your application, it is just enough to explore and fill entries through four particular steps. You just need to open the ST Protection Finder application on your phone, entering the product family you want to search in. For example, ESD protection. In the second step, you narrow the parameters needed for your application and you select from the pre-selected protection devices the best fitting product for your needs. Web links to the datasheet and the online documentation are also reachable through this app. Thank you for listening. This is the end of our webinar and we can proceed to the Q&A session now.