 재미免ful to the series of Videolectures on the Subject Digital Techniques for Secondary IT students. I am Dr. Sri Shal Sharad Kashbar. In this video lecture, we will continue the last point of our previous video i.e. Circuit Description Wayes on V Everybody Log with an example. At the end of this session, you will be able to write a very log module for Digital Circuits through behavioral-structural approach. So as mentioned in the previous video in very log there are two widely used approaches for describing a digital circuit and those are behavioral and second one is structural. Now let us see the behavioral description approach in short. In behavioral approach a circuit can be described using its logic expression and very log programming constructs. Here desired behavior of the circuit is described but not its actual structure in terms of logic kids. Behavioral description approach is the more abstract way to define circuits and in this case statements like assign are used. Let us take one example for illustrating the concept of behavioral approach. Here the problem is to write a very log module for implementing the logic expression x is equal to a into b plus c and we have to use the behavioral approach. Now in this case x is our output a b and c are the inputs. Now in this case we will start with the module keyword here the name of the module I have given as a b1. x is the output a b and c are the inputs and do not forget to give the semicolon at the end. Then the next step is to define the inputs and outputs for this circuit. So here our output is x so it is defined as output x then the inputs are three namely a b and c. Then the next step is to write the logic expression in terms of the very log programming constructs and those are in this case this AND operator and this OR operator. And in this case the expression on the right hand side is evaluated first and that is assigned to the output x in our case and that is taken care by this assign keyword which is written here. So in this case a is ANDed with the b and its result is ORed with the c and after its evaluation it is assigned to x and at the end we will write the AND module keyword. So this is the module definition which implements x is equal to a into b plus c. Now in structural description approach a circuit can be described using very log construct that describes the structure of the circuit in terms of circuit elements such as logic gates. Here a larger circuit is defined by writing code that connects such elements together. Here what we mainly use are the instances of built-in primitive gates such as AND gate OR gate NOT gate etc. Now let us take one example. Now in this case suppose we want to write a very log module implementing the previous equation that is x is equal to a AND b ORed with the c using the structural approach. We have seen the bHRL approach previously. Now we will do the same thing using the structural approach. So for the given logic equation x is equal to a into b plus c we can draw the circuit diagram using the interconnection of in terms of gates as follows here. This is the AND gate and this is the OR gate the inputs here are a and b and its output we have renamed as the t1. And this t1 is input to this OR gate and another input to the OR gate is c and at the output you can see here the symbol name is x. So this circuit implements what x is equal to a into b plus c. Now let us write a module definition using structural approach. Now in this case once again we will start with the module keyword. So module here the module name I have given as s1. This is the list of ports so x is the output port a b and c are the input ports. Then we have defined the input and output so output x and the inputs are a b and c and those are defined using these keywords output and input. Then we require an intermediate output namely t1 which is the output of the first AND gate and we have defined it as the wire data type. So wire t1 we have defined this wire here indicates this t1. Then next we describe the circuit in terms of logic gates. So first statement which we have written and the instance name is a1 and inside the bracket we have provided the list of ports for this logic gate. Now in this case t1 is the output which is written first then its inputs are a and b which is written here. Now the next statement will be OR o1 in bracket x,t1,c. Now in this case you can see x is the output for this logic gate. Then the first input to this OR gate is t1 which is written here. Then the second input is c which is also written at the end. So we have defined this circuit in terms of logic gates and we will close the module definition with the end module keyword. Now pause the video for 2 minutes and write down the answer of the given question. So these are the module definition using both behavioral approach as well as structural approach. Now let us describe one more example using both the approaches and in this example we will describe a 2S to 1 multiplexer in very lock using behavioral as well as structural model. Now this is the block diagram of 2S to 1 multiplexer. a and b are the inputs select is another input and out is the output in this case. Multiplexer by its definition it is many inputs and one output circuit. Here depending upon the select input the output is equals to either a or it is equals to b. Now using behavioral approach we require its logic expression and that is equals to out in this case is equals to a multiplied by select bar plus b into select. Select bar in this case is nothing but the complement of select input. Thus the very lock code can be written as follows. The module definition start with the module keyword followed by its name. I have given it as mux to 1 b e h in bracket we provide the list of ports. So here out is the output a b and a c l are the inputs. So output and input are defined in the next two lines. In the following statement we have written the assignment statement. Here assign out is equals to a ended with the not select. And this entire output is odd with the b and a c l. So this statement basically implements this logic expression. Now let us describe the same circuit using the structural description approach. Now in this case we first need to draw the circuit diagram in terms of logic gates. As you can see here a b and select are the inputs. Other than that we require two AND gates and one OR gate. We also require a NOT gate. The NOT gate has input from the select line and its output is connected to the first AND gate. The another input to the first AND gate is a and its output is given to the OR gate. The second AND gate has two inputs namely select and b and its output is also given to the OR gate. And this OR gate has the output namely out. Now before the very lock code for the circuit is written the circuit is redrawn with the necessary labels as shown in this figure. The output of the NOT gate is named as k. The output of the first AND gate is named as t1 and output of the second AND gate is named as t2. Now let us write the very lock module for this case. For your reference the circuit diagram is shown here. Now in this case we start with the module keyword. The name in this case I have given is mux21str. This is the list of the ports. In the next two lines we have defined the output and inputs. We have defined t1, t2 and k as the wire data type. Then in the next statement we have written NOT. The instance name is n1. In bracket we have given the output as k and the input is sl. In the next statement we have written AND a1. In bracket t1, a, k means we have defined the first AND gate. The inputs in this case are a and k which are here and its output is t1. That is written here. In the next statement we have written AND a2. a2 is the instance name in this case in bracket t2, b, sl. In this case t2 is the output, b and select as the input. You can see here b and select as the inputs and t2 is the output. And in the next statement finally we require to describe this OR gate. And it is described in this statement. So OR instance name is o1. In bracket the output in this case is out which is written here. The two inputs to this OR gate are t1 and t2 which are written here. And finally we have written the AND module keyword. These are the references. Thank you very much.