 we will now move ahead with whatever we are doing we were looking at again time switches earlier we have done super multiplex time switch and now we will actually look into time space first and then time space time later on and then how the control structure of this kind of switch is going to be implemented. So let's take a time space switch and obviously I require a space switch so I am taking a 3 by 3 okay so these are the three outgoing ports okay the space part I have done so far these white lines are nothing but the control lines they will control the cross points so if the cross point is on or not on it will be governed by these and interestingly I do not require a row and control row and column control will not be required the way it was there in the cross bar in this case okay I will tell how actually this happens I do not require a row and this thing and these are the input lines so but I also require a time switch this so far if I want a cross connection it is okay 3 by 3 so when I mean time and space this actually means time is already slotted in each voice slot there will be a separate connection which should be operating for this switch so far even frame every 125 microsecond 32 out of which two does not you never bother about them actually also basically for that 30 slots for each of those 30 slots in which we want the switching to happen there will be a specific cross connection pattern which have to be here there will be 30 patterns so they have to change every time slot okay so what we will do is we will actually now address these as 0 1 and 2 that's usually it will be done and I will use this there will be a control memory I will also have a time switch with this I am showing a speech memory each one of them will be controlled through a control memory so I am not drawing all of the circuits which are there as per the time switch design which we have done earlier okay so same thing so this is a serial line this will be converted to parallel time switching will happen it will be converted to a serial line again so it is not a parallel bus it is a serial line that is what I am assuming that is why there are three ports here okay on time scale this will be 0 to 125 microsecond there will be first slot second slot third slot and so on like these and these are the frame boundaries so you will have 8 bits coming in the first slot okay then you will have again 8 bits coming corresponding to second voice circuit and so on so they will be going from 0 1 2 3 and 31 two slots I am usually will not be bothered about whatever switching you do for those does not matter because they anyway will be stripped off at the input and they will be inserted back at the output okay inside the switch now this kind of configuration because what we have done was write cyclic and read a cyclic okay so write cyclic and read a cyclic this kind of configuration was discussed by me in the earlier lectures one of them so this actually means now you want to implement a switching there will be corresponding three frames coming here so what you have to specify always for a switch map input port number which is 0 1 and 2 and slot number and you will be having an outgoing port number and slot number the map has to be generated for this now let us look at first of all how the switch will operate now in the first time slot because I am doing right cyclic kind of configuration and this need not be having more number of ports more number of slots per frame I am keeping it same in this case okay so what will happen is you will have 30 frames 30 slots here you still will have 30 slots here 32 basically so you need to create first of all you need to you will be given these things are given by your switching requirement these are not governed by the switch now you have to just generate a map for these so once I give you this something so for example you say that for 0 number port slot number 25 this should be mapped on to port number 1 slot number 2 this kind of scenario so how this will be done so one thing is sure that when I am doing this only this time switch can change the slot here the actually only the physical port number can only be changed you cannot change this time slot because this is a space switch okay these are two stage switch so far so in this case what you require is your time slot should actually map from in 0th port from 25th slot to second slot and remember in speech memory I will be writing in which location I will be writing in 25th location because that's it's a right cyclic while I am writing I am writing in the location corresponding to the time slot number that counter which will be there which is counting time slot so I will be writing here in somewhere in 25th location but while reading I have to read in the second slot okay 0 1 2 in the second slot I have to do the reading so who will govern the reading reading will be governed by the control memory now it actually means in the second location of the control memory I should write what value I should be written 25th so in the second slot read from the 25th location because it's a cyclic read so in the second slot if I am reading from 25th location this location was filled in the 25th slot of the input so I had already done the time switching I have moved the thing from 25th slot to second slot once that is done I need to now put this thing to 0 1 and 2 so on the first slot I have to put it now remember in this column only one of these can be active even 2 can be active there is not an issue there is but I am assuming there is no multicast now there can be multicast but these all these three will never be connected at the same time because three inputs cannot go to the same output at any point of time that's like mixing the signals they will interfere with each other and you cannot make out anything one input I can go to multiple outputs okay so for example if I would have done this kind of scenario this control is implemented in such a way because I know that single input can go to multiple outputs but multiple inputs cannot go to single output that's not possible so I have to select the inputs not the outputs actually so for each column each output I am selecting the corresponding input only one input has to be selected so this is 0 1 2 so now I am reading in say I am worried about the second slot so in the second location because whenever the same my counter is counting 0 1 2 in the second slot I will be reading out from this control memory from the second location this should actually have a value 0 once this has a value 0 so during what value it should have yes 0 this 0 cross point will be connected for the second slot duration and the second slot is what was your octet was coming here so this octet will be routed to this output if you want to implement a multicast this actually should go to second slot for all outgoing ports then all second locations in all three control memory will contain 0 so you require the number of bits which is required for memory what will depend on how many cross points are there for each outgoing port or in each column column corresponds to an outgoing port row corresponds to an incoming port in this cross bar okay now this is the time multiplex which remember this is one kind of 3 by 3 switch in 0 slot it takes one configuration first slot 0 slot is no more existing time they are mutually exclusive when slot 1 is happening slot 0 and any other slot cannot happen so this is like 30 different switches which are operating in time multiplex mode 32 to again two configurations are useless because you will not be switching them so this is like 32 time space switches but I am using one single switch to emulate those two 32 space switches I could have done a TDM here and then product created a space output 30 space output then I would have required 32 space switches and of course this is obviously is a blocking switch you can always figure out a configuration where you cannot connect even when input and output is free can you think of some configuration where it will be blocking it has to be it is a two stage network it is not three stage particular time slots of course more than one channel want to send it on the same no that is the output contention that certainly only one will be permitted but there has to be a case where input and output are available but you cannot make the connection I think it will become clear you can build it if I build up a space switch because that is so this is a 30 0 to 31 space switch three of them okay and then you have three by three this is equivalent to this so I have just converted my time switch to the space switch here so I then required 0 to 31 and I think I should put it 0 to 2 that is the best way so both are equivalent actually except now I am not using a time switch now as you can find out a one corresponding blocking configuration here is very simple let 0 be connected to this particular port okay this actually means 0th port time slot number 0 getting connected to now this corresponds to the physical port and switch number corresponds to the time switch okay a time slot so this corresponds to 0 31 slot if this mapping is done this particular connection is gone now you want to connect slot number 1 to 1 31 now is it possible not possible because you have to first of all put that thing into 31 slot that 31 slot is already occupied so now look the same thing here now one thing is sure that I cannot set up this link this gets blocked so coming here what I am saying is this is the last slot okay this 0 0 actually 0 0 is this one this one was mapped to 31 and then during the 31st slot I have actually connected this as 0 in the 31st location so this gets rooted on this output you get this what I want is now on the second on the first one on the second output I want to connect root here from the second slot this can only be done if the second can be moved to 31 31 is not available that's like this line is there is only one connection which is possible here and it's a blocking system now immediately probably you should be able to correlate between the two scenarios when you want to for example this equivalent scenario that 01 has to be connected to 131 if you want to do that this one has to be moved to slot number 31 here but this slot number 31 on this line has all been already occupied okay slot number 31 is already occupied because of previous connection this is like this line has been occupied one line connecting this switch to this switch this is a switch switch blocking input and output both are available input is free output is free but you cannot set up a root exactly same principles will follow in this configuration also in time space configurations so with two stages it is not possible so what we do is we go for a three stage configuration then because I can use whatever logic which I have we have learnt earlier and I can say okay let me put a switch here let me put a switch here let me put a switch here and there will be correspondingly the control memories fine okay and once you have this I will be able to take care of that contention how that will be done so I have done 0 to 31 switching what same thing from here this 31 remains 31 when I want to switch to 131 so this from there I can take to any slot which is available in this case so this might be this one say so 15 which is available okay so I map from 1 to 15 to this time switch so in this case at 15th location I will write one at 15th location I will write one so during the 15 time slot to read from location one which is written during the slot one so I am able to do time slot change actually through this TSI it is known as time slot interchange here also so when this comes so at that point I can now switch here so I can now put at 15th location I have to now connect switch number 0 okay that 31 0 remains here 15 0 which has to be put so 15th slot what will be coming here and now I can swap over using this control memory so in location number again if it is a right cyclic and read a cyclic same kind of switch what will happen is it will be writing on the 15th location inside this case memory and this has to be read out at 31st so here 31st location I will read from 15th my only problem is that I cannot use one single clock which is derived from the at the input of this whole block this this whole thing is known as switch block this whole unit is known as switch block actually and each of these element is a switch basic unit so there is a complication because here it is 15 here it is 15 here it is 31 can I also make here this thing also as a 15 that will keep the life very simple actually so whatever is current slot running I can just use that of course this will be a there will be a problem if I expand the number of slots here then this will not be true in that case because the number of locations here will be larger currently this is rearrangeably non-blocking switch okay and so I will change this so this is equivalent to 0 to 31 another one 0 to 31 another one 0 to 31 yeah 31 outputs and uf so this is 1 2 3 1 2 and 3 both switches are equivalent now this is a space space space configuration and as per the slap and do it theorem this satisfies the condition of rearrangeable non-blocking property here r2 is greater than or equal to maximum of m1 and m3 so 31 32 are there and r2 is equal to 32 so it is a non-blocking configuration is it both are equivalent both are all three are space switches I am saying this configuration and this configuration are equivalent you have these 32 space switches these 32 are being emulated by one single 3 by 3 here because now time multiplexed so every 125 microsecond it has 32 possible configurations emulating these switches so important thing is the amount of hardware reduces drastically each one of them is now converted to time that is the only thing but this is a time multiplex thing so instead of 32 you require only one so it is a big advantage actually it is a big advantage here now this problem is still has to be resolved otherwise switch block control cannot be simplified because remember when I am going to build up a packet switch packets will keep on coming at the input and packets come for a very narrow duration so depending on whatever are the input packets which are there I have to immediately figure out for that slot a interconnection input to output mapping which has to be implemented for that slot all packets will be routed out to the outgoing ports and by the time you have to compute for the next incoming slot what should be the new configuration so it will be very fast switching which will be done control it is not like circuit switch you set up a path and it remains no there is also one very important phenomena which will happen is in case of circuit switching there is already some connections are set up you set up some new connection without disturbing the older ones you release some connections some connections will still remain no that situation is not there in packet switching system because at the beginning of the slot it is like fresh all connections are made fresh depending on how the packets have to be routed to the output okay and of course my assumption is that there will not be in this case there will not be any line problem only problem which can happen is the output contention when two packets try to go to the same output in same slot simultaneously that will not be permitted but this now this kind of switch will operate at much much higher rates much higher frequency actually so every time slot it will change every packet time slot so if it's a ATM system so whatever is a 40 53 byte ATM cell for every ATM cell there will be different switch configuration usually switches will be synchronous all input packets will be aligned they will be usually of same size output will be also of in same way aligned but in real life packets are actually are not of same size no IP packet are of same size but that reduces efficiency of switching if I start using variable length packets then it becomes usually you chop it off make it everything equal and synchronously I can start operating the switch okay the only problem is all packet headers have to be analyzed they have to be aligned and all action have to be done in all control memories have to be configured and then the packet will go out and before the next packet is pushed in again you have to reset change all the control memories correspondingly have to be written the only problem is for the whole slot all these 30 locations have to be rewritten all these 30 locations so before a new frame starts now that's a complication because this whole memory this whole memory so in this case they have actually total nine memories each one consisting of 32 locations all this word has to be written before the next batch of packets can be inserted all the packets now this is the only complication which is there well of course you can still use the switch but it is going to be complicated because you have got there is no that 125 microsecond thing is not there anymore okay usually it will be shorter duration when packets comes into picture so what will happen is this is the packet slot duration so switching has happened in this very small fraction of time all the control memories has to be rewritten parallelly so you have to write all 32 words inside the memory within this short period so the switching can happen there will be some period when you cannot do any you cannot pass through any packet so there will be a small gap or a guard band which has to be there again this has to be done in very short thing now this is one of the crucial thing to implement circuit switching it's fine when you want to set up a circuit only one memory location you have to write or something is fine then the circuit remains for a long period so packet switching system that's the reason why packet switching systems are not usually implemented in this fashion unless you can write this control memory in a large bust the whole memory has to be written not a single word actually now coming to this solving this but to the problem for circuit switching is still it becomes important so I will do that I have given you a quiz actually yesterday and I asked you to write a draw a schematic for write a cyclic and read cyclic configuration so what was the beauty in that in that case you had a speech memory you were writing into it and you were also having your counter which is generating the address but remember now you have to read cyclically so this address has to be used for reading purpose not for writing for writing you will be picking up address from the control memory okay so control memory whatever is written actually tells where it has to be in what location it has to be written actually so I think there was it was pretty simple there was a clock here which was also driving the counter and there was the frame clock which was driving the which was resetting the counter every frame period and once this thing comes this clock during positive cycle I can write and during negative cycle I can read and I had a selector here so output of the control memory goes into this this counter address actually goes into this this actually means is the outgoing thing this clock will also be driving this particular RAM it has to if the number of frames are same otherwise you have to go for dual system dual memory otherwise okay so a thumb rule is that whenever these clock rates input and output both are same you can actually go for single memory option whenever the clock rates are different you have to always go for dual memory option you cannot work with single memory in that case so this clock will be selecting so when it is one it has to write for writing it has to take from this address so one will be here and zero will be here in the design which I have taught earlier which was ride cyclic and read a cyclic this was the reverse actually I have just inverted ones and zeros circuit actually remains the same only zero one have to be swapped so that was also the answer to the quiz which you did yesterday is exactly same circuit has to be copied and zeros ones have to be swapped nothing else okay so this address what goes here clock anyway goes in this case so whenever this clock is positive you are going to use this and read write bar so you are in the right mode only thing this which address you are going to write is going to change that's the only thing that's everything remains the same okay and same counter also goes I can write but usually I will not be using even because once I make this change there in actually my block control switch block control I will not be using a separate address coming from the control that will not be done but I am still drawing it okay now during this has to be zero again this is controlled from same clock so when it is zero this address has been pumped here whatever is coming out it is zero it goes into this that's what it means and during one you will be writing here and again correspondingly there will be a read write bar okay so that's how it's going to work is as simple as that you have to again I have changed here you have to see so here earlier it was one it was zero it was zero and it was one that's also fine that also is fine but usually circuits are always read write bar 885 circuit you might have done it was always read write bar it was never read bar R read bar W so I just use the convention all solutions are correct so far it is going to function on the chip or hardware system is fine well it should function without any problem and other people who are using your thing as a module should actually get the same module abstraction independent of how you implement it you should never actually implement something in such a way that it's different than the abstraction itself because when they are building up their system using your some module subsystem they always conceive they always think of an abstraction and if it is different their system will become wrong because they always consider your box as a black box to certain designated behavior so that black box whatever is visible to outside should remain same how you do internally is your problem system should work consistently as per the abstraction model centered there is a lot of abstraction you must be observing which I have been also using here now using this what will be the address here I have to use now because in 31st slot it will anyway will be reading in 15th slot I will write at 31st location so once I do this I have got 15 I got 15 I got 15 here also all three so you use write cyclic read a cyclic here instead of WCRA move to write a cyclic read cyclic so I have got the same addresses actually okay so now coming to the switch block control how that will be done once this is clear I can move to switch block control thing was clear right now we are converting sir all times which is WS no no the first stage is write cyclic read a cyclic all three of them the third stage it is write a cyclic and read cyclic these are example which I am showing this true for any combination you take any mapping from here to here you will find out you will require same location everywhere you take any mapping well you can take another example you tell me is one say 128 had to map to say 314 let's try this out so I have to do 128 so 128 is going to be in this thing somewhere here now I only know the input port and slot number and output port and slot number which particular slot number will be used in between this and this for transporting I have to decide whatever is available and if it is not available there is no common slot available which can be used I can make the rearrangements and always find one again using that slip into the theorem and then the method by which we do the rearrangements we can find that because remember this switch is equivalent to that rearrangement on blocking a space switch anytime you have a confusion write that draw that thing because theorems have been done with that and then from there you find out the rearrangements do the slot change whatever it is find out the vacant slot you can always find a vacant slot which is common to this as well as this third one basically you need a common slot because some slots will be occupied here some slots will be occupied here whichever slot which is free in both of these and which is same number only that you need so far you can find one you can use that initially when the third stage was also WC then also yes yes then also the same procedure advantage approved because we are changing it to no with this memory addresses all three will have now 15 otherwise you are using 15 15 and 31 here yeah there is a implementing control is a control implementation issue now switching will still function switching has nothing no issues mathematically everything is correct okay because i am trying to reduce the hardware so why we have completely removed this which one second step super multiplex time switch was that see instead of that three one even i was using 16 evens on this side i created super multiplex switch structure and i got 16 evens out so i am not here doing super multiplexing see super multiplexing also has a limitation you cannot keep on doing it ultimately for a very large size sometimes you will go for a space hardware requirement is more in a time switch it is not less always it is always less only thing your clock frequency changes what it what is in this one is compared to whom this is just another option if given if i can implement everything using a super multiplex time switch i will always go for that but your clock issues synchronization issues if you can maintain that that's the best you are using in something which is in time only thing cost is that i am actually there you are storing reading and writing in a different sequence see this cost actually becomes huge if you start using for example optical switches optical switch if i want to do all optical implementation i require a delay line a fiber delay line for memory a rhyme is pretty simple for you it's these are flip flops electronic flip flops fiber there are no flip flops you can actually build it's not you can build optical flip flops also but these will be they're actually switching speed is an issue and then of course for how long you can store really is delay lines is the most common technique which is used but this make the switch cumbersome if you want to build up a time slot interchanger you can do optically it's not that you cannot do it but then this will actually have problems so building up a space switch in the optical domain is going to be much much better because more compact in size so that's the reason in fact there is nothing like a best solution i cannot give you a best solution which will fit everywhere as an engineer you have to look at all of possible options depending on your application where you are for which you are implementing you have to choose the best thing out of all possibilities okay so yeah i was doing this 128 so maybe you find out say 11 is free slot number 11 my only question is how do you find out that 11 slot number no that's against lep and duke theorem no see when you are setting up connections here how many inputs are there 32 but there is one slot which is free which you are trying to connect one input so only 31 can be occupied here so there is at least one slot which will be free here okay look at this output again your one output is free let rest everything is busy so there has to be one slot which is free here also in worst case scenario the slot which is free here and slot which is free here are not same this same thing see the element in the row which is present actually and element in the column you cannot find out a common element which is missing from both if you take both the sets all are occupied that's what is happening all slots here taken here all slots taken here make union of those all slots are occupied then you can always find a pair element in the row which is not present here but present in the column element in the column which is not present in the column but present in the row there is already a pair i have proved that and then i can use that same algorithm a roll column thing and then find out and do all the swaps then you can always build up a slot which is free in both use that that algorithm in the back end will keep on running algorithm is going to be same what was there for space switches it will not change as far as the software abstraction is concerned abstraction remains the same how you implement the switch is different no there is a rearrangement algorithm which comes because of in the slip into good theorem a controller will be running separately now there is a separate command control there is a separate processor which has to figure out somebody has to tell them you have when you are stripping the signaling that is going to come into that computer there is a microprocessor setting there which is running the algorithm so all signaling information come will come here signaling information will tell that which particular path has to be set up to be connected to which particular port here a your port map will be generated by that that always happens in telephony when are you dial a number it goes to exchange exchange looks into table it has to go to this particular line any port on this on the output side it has to go to one specific outgoing port and any incoming port when it depends whether you are on transit or both users are connected to same action if both users are on the same action the ports are fixed which have to be connected and then they have to run a what we call routing algorithm and switching algorithm is required after that so that I am assuming is already running in some other processor and that processor through a bus mechanism is able to write into these I am coming to that actually now how this will be done there will be three kind of messages which are implemented which are actually used for this kind of communication it only says that r2 has to be greater than equal to maximum of this thing then after there is a algorithm rearrangement algorithm which I told which was this looping is only for 2 by 2 elements looping cannot be set in general in general you cannot form loops actually so you have to find out cd and then corresponding cd this is algorithm I am talking about yeah again that's a Paul's theorem Paul's theorem only says that how many a rearrangements are required that's again a theorem but the arrangement procedure is part of the slip and do it thing so it not only says that what is minimum required but how it also will be done so you for example find out the slot number say 10 which is available here as well as here once you know this I am going to write cyclically so I will be writing at 28 location okay so but while reading it has to be read at the 10th location the value will be 28 10th location here switching has to happen sorry this one 10th location switching has to happen at this point one and at 10th location I should write on to location number 14 in this case this is a 10th location I have to write at location number 14 14th I will be reading out cyclically so it will be ultimately coming at the 14th location here so this will get mapped on to 14th location this one go there all locations are 10 10 10 7 is where this instead of this 10 okay you do 7 but then this also has to switch at the 7th only here also the 7 will come and also then you have to move here also at the 7 because you cannot do times switching here so here also it will be at the 7th location so everywhere it will change so the location or the control memory location is identified by the slot which is being used as an intermediary to transport the voice sample okay I think this already 10 955 I have to close so I think switch block control is what I will do in the next class and then we will move with the packet switching system